rx82 0.1.0

An emulator for the RX82 retro computer system.
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159

use crate::{
    bus::{Bus, State},
    cpu::Phase::{Execute, FetchOperand},
    device::Device,
    instructions::{INSTRUCTIONS, Instruction},
    regs::{Reg8::A, Regs},
};

/// The phase of the CPU.
#[non_exhaustive]
#[derive(Debug, Default, PartialEq)]
pub enum Phase {
    /// Decodes the opcode on the data bus.
    Decode,
    /// Executes the current instruction.
    Execute,
    /// Requests the next opcode from memory.
    #[default]
    FetchOpcode,
    /// Requests an operand from memory.
    FetchOperand,
    /// Waits for memory to respond.
    MemWait,
    /// Reads an operand from the data bus.
    ReadOperand,
}

/// The system CPU.
#[non_exhaustive]
#[derive(Debug, Default)]
pub struct Cpu {
    /// The current instruction.
    pub ins: &'static Instruction,
    /// Do we need to fetch an operand?
    pub need_operand: bool,
    /// The current opcode.
    pub opcode: u8,
    /// The current operand.
    pub operand: u8,
    /// The program counter.
    pub pc: u16,
    /// The current phase.
    pub phase: Phase,
    /// The CPU's registers.
    pub regs: Regs,
}

impl Device for Cpu {
    /// Performs the current phase, and set the next phase.
    #[inline]
    fn tick(&mut self, bus: &mut Bus) {
        self.phase = match self.phase {
            Phase::Decode => {
                self.opcode = bus.data;
                bus.defer_write(vec![State::Mem(false)]);
                self.pc = self.pc.wrapping_add(1);
                self.decode()
            }
            Phase::Execute => {
                self.need_operand = false;
                println!("execute");
                self.debug_print();
                if let Some(ins) = INSTRUCTIONS.get(&self.opcode) {
                    (ins.execute)(self);
                }
                Phase::FetchOpcode
            }
            Phase::FetchOpcode => {
                bus.defer_write(vec![State::Addr(self.pc), State::Mem(true)]);
                Phase::MemWait
            }
            Phase::FetchOperand => {
                self.operand = bus.data;
                bus.defer_write(vec![State::Addr(self.pc), State::Mem(true)]);
                self.need_operand = true;
                Phase::MemWait
            }
            Phase::MemWait => {
                if self.need_operand {
                    Phase::ReadOperand
                } else {
                    Phase::Decode
                }
            }
            Phase::ReadOperand => {
                self.operand = bus.data;
                bus.defer_write(vec![State::Mem(false)]);
                Phase::Execute
            }
        };
    }
}

impl Cpu {
    /// Prints the CPU's state and registers.
    #[expect(clippy::use_debug, reason = "it's for debugging")]
    #[inline]
    pub fn debug_print(&self) {
        println!(
            "PC {:04X} A {:02X} OC {:02X} O1 {:02X} Phase {:?}",
            self.pc,
            self.regs.get8(A),
            self.opcode,
            self.operand,
            self.phase,
        );
    }

    /// Decodes the current opcode and decides whether an operand is needed.
    fn decode(&mut self) -> Phase {
        println!("decoding {:02X}", self.opcode);
        self.ins = INSTRUCTIONS.get(&self.opcode).unwrap_or_default();
        match self.ins.bytes {
            2 => FetchOperand,
            _ => Execute,
        }
    }
}

#[cfg(test)]
mod tests {
    use crate::instructions::LDA_N;

    use super::*;

    #[test]
    fn cpu_phases_are_correct_for_zero_operand_instruction() {
        let mut cpu = Cpu::default();
        let mut bus = Bus::default();
        assert_eq!(cpu.phase, Phase::FetchOpcode);
        cpu.tick(&mut bus);
        assert_eq!(cpu.phase, Phase::MemWait);
        bus.data = 0x00; // nop
        cpu.tick(&mut bus);
        assert_eq!(cpu.phase, Phase::Decode);
        cpu.tick(&mut bus);
        assert_eq!(cpu.phase, Phase::Execute);
    }

    #[test]
    fn cpu_phases_are_correct_for_one_operand_instruction() {
        let mut cpu = Cpu::default();
        let mut bus = Bus::default();
        assert_eq!(cpu.phase, Phase::FetchOpcode);
        cpu.tick(&mut bus);
        assert_eq!(cpu.phase, Phase::MemWait);
        bus.data = LDA_N; // ld a, N
        cpu.tick(&mut bus);
        assert_eq!(cpu.phase, Phase::Decode);
        cpu.tick(&mut bus);
        assert_eq!(cpu.phase, Phase::FetchOperand);
        cpu.tick(&mut bus);
        assert_eq!(cpu.phase, Phase::MemWait);
        cpu.tick(&mut bus);
        assert_eq!(cpu.phase, Phase::ReadOperand);
        cpu.tick(&mut bus);
        assert_eq!(cpu.phase, Phase::Execute);
    }
}