rvsim-core 2.0.0

A cycle-level RISC-V 64-bit system simulator.
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//! Backend pipeline stages.
//!
//! The backend covers: Issue -> Execute -> Memory1 -> Memory2 -> Writeback -> Commit.
//! Shared stages (Memory1, Memory2, Writeback, Commit) are common free functions.
//! Issue and Execute differ between in-order and O3 backends.

pub mod inorder;
pub mod o3;
pub mod shared;