rvsim-core 2.0.0

A cycle-level RISC-V 64-bit system simulator.
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//! Bus arbitration and device lookup tests.
//!
//! Tests in this module used the deleted `Memory` device + synchronous
//! `bus.read_u*/write_u*` API. Bus dispatch and IRQ aggregation are now
//! exercised end-to-end via the packet-based `Simulator` integration tests.