rvsim-core 2.0.0

A cycle-level RISC-V 64-bit system simulator.
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//! # CSR Unit Tests
//!
//! This module serves as the entry point for unit tests related to the RISC-V
//! Control and Status Registers (CSRs). It organizes tests into logical groups
//! covering access control, performance counters, and trap setup.

pub mod access_control;
pub mod cbo_gates;
pub mod counters;
pub mod cpu_csr_operations;
pub mod misa_string;
pub mod trap_setup;