rvsim-core 2.0.0

A cycle-level RISC-V 64-bit system simulator.
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//! The whole simulated system: building it, running it, saving it.
//!
//! The `Simulator` owns the chip (harts, cores, uncore) and the bench-side
//! state; this layer also loads programs, generates the device tree, and
//! saves and restores checkpoints.

pub mod cache_audit;
pub mod checkpoint;
pub mod coherence_audit;
pub mod dtb;
pub mod loader;
pub mod simulator;
pub mod snapshot;
pub(crate) mod state;

pub(crate) use self::state::SystemState;
pub use crate::soc::uncore::{StatsDump, StatsEpoch, TraceControl};