rvsim-core 2.0.0

A cycle-level RISC-V 64-bit system simulator.
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//! Hardware Prefetcher implementations.
//!
//! This module contains the interface and implementations for various
//! hardware prefetchers used to hide memory latency.

pub mod next_line;

pub mod store_stream;

pub mod stream;

pub mod stride;

pub mod tagged;

pub use self::next_line::NextLinePrefetcher;
pub use self::store_stream::StoreStreamPrefetcher;
pub use self::stream::StreamPrefetcher;
pub use self::stride::StridePrefetcher;
pub use self::tagged::TaggedPrefetcher;

use crate::common::VirtAddr;

/// Trait for cache prefetcher implementations.
///
/// Prefetchers observe memory access patterns and generate prefetch
/// requests to reduce cache miss penalties.
pub trait Prefetcher: Send + Sync {
    /// Observes a memory access and generates prefetch addresses.
    ///
    /// Called by the cache on each access to allow the prefetcher to
    /// learn access patterns and generate prefetch requests.
    ///
    /// # Arguments
    ///
    /// * `addr` - The address that was accessed
    /// * `pc` - The PC of the instruction that made the access, if it has one
    /// * `hit` - Whether the access was a cache hit
    ///
    /// # Returns
    ///
    /// A vector of addresses to prefetch. Empty if no prefetches are needed.
    fn observe(&mut self, addr: u64, pc: Option<VirtAddr>, hit: bool) -> Vec<u64>;
}