rvsim-core 2.0.0

A cycle-level RISC-V 64-bit system simulator.
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//! The simulation kernel every timed component is built on.
//!
//! The event queue and the `Handle` components receive events through, the
//! packets they exchange, the identifiers that address them, the memory
//! image accesses perform against, and statistics.

pub mod components;
pub mod events;
pub mod handle;
pub mod memory;
pub mod packet;
pub mod stats;