rvsim-core 2.0.0

A cycle-level RISC-V 64-bit system simulator.
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//! RISC-V Base Integer Instruction Set (I).
//!
//! Defines the fundamental integer instructions required by any RISC-V implementation.
//!
//! # Structure
//!
//! - `opcodes`: Major opcodes (Load, Store, Branch, Jal, `OpImm`, `OpReg`, etc.).
//! - `funct3`: Minor opcodes distinguishing instructions within a major opcode.
//! - `funct7`: Additional opcode bits for R-type instructions.
//! - `decode`: Logic to decode raw instruction bits into a structured format.

pub mod funct3;

pub mod funct7;

pub mod opcodes;