rvsim-core 2.0.0

A cycle-level RISC-V 64-bit system simulator.
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//! Memory access type classification (Fetch / Read / Write).

/// Type of memory access operation.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum AccessType {
    /// Instruction fetch access — requires X permission.
    Fetch,
    /// Data read access — requires R permission.
    Read,
    /// Data write access — requires W permission.
    Write,
}