1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
//! The emulator module represents an entire computer.
use crate::cpu::Cpu;
use crate::exception::Trap;
/// The emulator to hold a CPU.
pub struct Emulator {
/// The CPU which is the core implementation of this emulator.
pub cpu: Cpu,
/// The debug flag. Output messages if it's true, otherwise output nothing.
pub is_debug: bool,
/// The test flag for riscv/riscv-tests.
pub is_test: bool,
}
impl Emulator {
/// Constructor for an emulator.
pub fn new() -> Emulator {
Self {
cpu: Cpu::new(),
is_debug: false,
is_test: false,
}
}
/// Reset CPU state.
pub fn reset(&mut self) {
self.cpu.reset()
}
/// Set binary data to the beginning of the DRAM from the emulator console.
pub fn initialize_dram(&mut self, data: Vec<u8>) {
self.cpu.bus.initialize_dram(data);
}
/// Set binary data to the virtio disk from the emulator console.
pub fn initialize_disk(&mut self, data: Vec<u8>) {
self.cpu.bus.initialize_disk(data);
}
/// Set the program counter to the CPU field.
pub fn initialize_pc(&mut self, pc: u64) {
self.cpu.pc = pc;
}
/// Start executing the emulator.
pub fn start(&mut self) {
let mut count = 0;
loop {
count += 1;
// This is a workaround for unit tests to finish the execution.
if self.is_test && count > 10000 {
return;
}
if self.cpu.is_count && count > 50000000 {
return;
}
// Run a cycle on peripheral devices.
self.cpu.devices_increment();
// Take an interrupt.
match self.cpu.check_pending_interrupt() {
Some(interrupt) => interrupt.take_trap(&mut self.cpu),
None => {}
}
// Execute a fetched instruction.
let trap = match self.cpu.execute() {
Ok(inst) => {
if self.is_debug {
dbg!(format!(
"pc: {:#x} , inst: {:#x}, is_inst 16? {}",
self.cpu.pc,
inst,
// Check if an instruction is one of the compressed instructions.
(inst & 0xffff_0000) == 0,
));
}
// Return a dummy trap.
Trap::Requested
}
Err(exception) => exception.take_trap(&mut self.cpu),
};
match trap {
Trap::Fatal => {
println!("pc: {:#x}, trap {:#?}", self.cpu.pc, trap);
return;
}
_ => {}
}
}
}
}