rvdasm 0.2.3

A RISC-V disassembler written in Rust
Documentation
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/* Automatically generated by parse_opcodes */
use once_cell::sync::Lazy;
use crate::args::*;

#[derive(Debug, Clone)]
pub struct Spec {
  pub name: String,
  pub mask_bits: u32,
  pub match_bits: u32,
  pub args: Vec<fn(u32)->(Arg, String)>,
}

impl Spec {    
    pub fn new(name: &str, mask_bits: u32, match_bits: u32, args: Vec<fn(u32)->(Arg, String)>) -> Self {
        Self { name: name.to_string(), mask_bits, match_bits, args }
    }

    pub fn compare(&self, code: u32) -> bool {
        (code & self.mask_bits) == self.match_bits
    }
}

// Compressed instructions (16-bit) - general (not XLEN-specific)
pub static RV_ISA_SPECS_GENERIC_COMPRESSED: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("c.add", 0xf003, 0x9002, vec![rd_n0, rs1_n0, c_rs2_n0]),
    Spec::new("c.addi", 0xe003, 0x1, vec![rd_n0, rs1_n0, c_nzimm6lo, c_nzimm6hi]),
    Spec::new("c.addi16sp", 0xef83, 0x6101, vec![c_nzimm10hi, c_nzimm10lo]),
    Spec::new("c.addi4spn", 0xe003, 0x0, vec![rd_p, c_nzuimm10]),
    Spec::new("c.and", 0xfc63, 0x8c61, vec![rd_p, rs1_p, rs2_p]),
    Spec::new("c.andi", 0xec03, 0x8801, vec![rd_p, rs1_p, c_imm6hi, c_imm6lo]),
    Spec::new("c.beqz", 0xe003, 0xc001, vec![rs1_p, c_bimm9lo, c_bimm9hi]),
    Spec::new("c.bnez", 0xe003, 0xe001, vec![rs1_p, c_bimm9lo, c_bimm9hi]),
    Spec::new("c.ebreak", 0xffff, 0x9002, vec![]),
    Spec::new("c.fld", 0xe003, 0x2000, vec![rd_p, rs1_p, c_uimm8lo, c_uimm8hi]),
    Spec::new("c.fldsp", 0xe003, 0x2002, vec![rd, c_uimm9sphi, c_uimm9splo]),
    Spec::new("c.fsd", 0xe003, 0xa000, vec![rs1_p, rs2_p, c_uimm8lo, c_uimm8hi]),
    Spec::new("c.fsdsp", 0xe003, 0xa002, vec![c_rs2, c_uimm9sp_s]),
    Spec::new("c.j", 0xe003, 0xa001, vec![c_imm12]),
    Spec::new("c.jalr", 0xf07f, 0x9002, vec![c_rs1_n0]),
    Spec::new("c.jr", 0xf07f, 0x8002, vec![rs1_n0]),
    Spec::new("c.li", 0xe003, 0x4001, vec![rd_n0, c_imm6lo, c_imm6hi]),
    Spec::new("c.lui", 0xe003, 0x6001, vec![rd_n2, c_nzimm18hi, c_nzimm18lo]),
    Spec::new("c.lw", 0xe003, 0x4000, vec![rd_p, rs1_p, c_uimm7lo, c_uimm7hi]),
    Spec::new("c.lwsp", 0xe003, 0x4002, vec![rd_n0, c_uimm8sphi, c_uimm8splo]),
    Spec::new("c.mv", 0xf003, 0x8002, vec![rd_n0, c_rs2_n0]),
    Spec::new("c.nop", 0xef83, 0x1, vec![c_nzimm6hi, c_nzimm6lo]),
    Spec::new("c.or", 0xfc63, 0x8c41, vec![rd_p, rs1_p, rs2_p]),
    Spec::new("c.sub", 0xfc63, 0x8c01, vec![rd_p, rs1_p, rs2_p]),
    Spec::new("c.sw", 0xe003, 0xc000, vec![rs1_p, rs2_p, c_uimm7lo, c_uimm7hi]),
    Spec::new("c.swsp", 0xe003, 0xc002, vec![c_rs2, c_uimm8sp_s]),
    Spec::new("c.xor", 0xfc63, 0x8c21, vec![rd_p, rs1_p, rs2_p]),
]);

// Compressed instructions (16-bit) - 32-bit specific
pub static RV_ISA_SPECS_32_COMPRESSED: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("c.flw", 0xe003, 0x6000, vec![rd_p, rs1_p, c_uimm7lo, c_uimm7hi]),
    Spec::new("c.flwsp", 0xe003, 0x6002, vec![rd, c_uimm8sphi, c_uimm8splo]),
    Spec::new("c.fsw", 0xe003, 0xe000, vec![rs1_p, rs2_p, c_uimm7lo, c_uimm7hi]),
    Spec::new("c.fswsp", 0xe003, 0xe002, vec![c_rs2, c_uimm8sp_s]),
    Spec::new("c.jal", 0xe003, 0x2001, vec![c_imm12]),
]);

// Compressed instructions (16-bit) - 64-bit specific
pub static RV_ISA_SPECS_64_COMPRESSED: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("c.addiw", 0xe003, 0x2001, vec![rd_n0, rs1_n0, c_imm6lo, c_imm6hi]),
    Spec::new("c.addw", 0xfc63, 0x9c21, vec![rd_p, rs1_p, rs2_p]),
    Spec::new("c.ld", 0xe003, 0x6000, vec![rd_p, rs1_p, c_uimm8lo, c_uimm8hi]),
    Spec::new("c.ldsp", 0xe003, 0x6002, vec![rd_n0, c_uimm9sphi, c_uimm9splo]),
    Spec::new("c.sd", 0xe003, 0xe000, vec![rs1_p, rs2_p, c_uimm8hi, c_uimm8lo]),
    Spec::new("c.sdsp", 0xe003, 0xe002, vec![c_rs2, c_uimm9sp_s]),
    Spec::new("c.slli", 0xe003, 0x2, vec![rd_n0, rs1_n0, c_nzuimm6hi, c_nzuimm6lo]),
    Spec::new("c.srai", 0xec03, 0x8401, vec![rd_p, rs1_p, c_nzuimm6lo, c_nzuimm6hi]),
    Spec::new("c.srli", 0xec03, 0x8001, vec![rd_p, rs1_p, c_nzuimm6lo, c_nzuimm6hi]),
    Spec::new("c.subw", 0xfc63, 0x9c01, vec![rd_p, rs1_p, rs2_p]),
]);

// Full instructions (32-bit) - general (not XLEN-specific) grouped by opcode
pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_03: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("lb", 0x707f, 0x3, vec![rd, rs1, imm12]),
    Spec::new("lbu", 0x707f, 0x4003, vec![rd, rs1, imm12]),
    Spec::new("lh", 0x707f, 0x1003, vec![rd, rs1, imm12]),
    Spec::new("lhu", 0x707f, 0x5003, vec![rd, rs1, imm12]),
    Spec::new("lw", 0x707f, 0x2003, vec![rd, rs1, imm12]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_07: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("fld", 0x707f, 0x3007, vec![fd, rs1, imm12]),
    Spec::new("flw", 0x707f, 0x2007, vec![fd, rs1, imm12]),
    Spec::new("vl1re16.v", 0xfff0707f, 0x2805007, vec![rs1, vd]),
    Spec::new("vl1re32.v", 0xfff0707f, 0x2806007, vec![rs1, vd]),
    Spec::new("vl1re64.v", 0xfff0707f, 0x2807007, vec![rs1, vd]),
    Spec::new("vl1re8.v", 0xfff0707f, 0x2800007, vec![rs1, vd]),
    Spec::new("vl2re16.v", 0xfff0707f, 0x22805007, vec![rs1, vd]),
    Spec::new("vl2re32.v", 0xfff0707f, 0x22806007, vec![rs1, vd]),
    Spec::new("vl2re64.v", 0xfff0707f, 0x22807007, vec![rs1, vd]),
    Spec::new("vl2re8.v", 0xfff0707f, 0x22800007, vec![rs1, vd]),
    Spec::new("vl4re16.v", 0xfff0707f, 0x62805007, vec![rs1, vd]),
    Spec::new("vl4re32.v", 0xfff0707f, 0x62806007, vec![rs1, vd]),
    Spec::new("vl4re64.v", 0xfff0707f, 0x62807007, vec![rs1, vd]),
    Spec::new("vl4re8.v", 0xfff0707f, 0x62800007, vec![rs1, vd]),
    Spec::new("vl8re16.v", 0xfff0707f, 0xe2805007, vec![rs1, vd]),
    Spec::new("vl8re32.v", 0xfff0707f, 0xe2806007, vec![rs1, vd]),
    Spec::new("vl8re64.v", 0xfff0707f, 0xe2807007, vec![rs1, vd]),
    Spec::new("vl8re8.v", 0xfff0707f, 0xe2800007, vec![rs1, vd]),
    Spec::new("vle16.v", 0xfdf0707f, 0x5007, vec![vm, rs1, vd]),
    Spec::new("vle16ff.v", 0xfdf0707f, 0x1005007, vec![vm, rs1, vd]),
    Spec::new("vle32.v", 0xfdf0707f, 0x6007, vec![vm, rs1, vd]),
    Spec::new("vle32ff.v", 0xfdf0707f, 0x1006007, vec![vm, rs1, vd]),
    Spec::new("vle64.v", 0xfdf0707f, 0x7007, vec![vm, rs1, vd]),
    Spec::new("vle64ff.v", 0xfdf0707f, 0x1007007, vec![vm, rs1, vd]),
    Spec::new("vle8.v", 0xfdf0707f, 0x7, vec![vm, rs1, vd]),
    Spec::new("vle8ff.v", 0xfdf0707f, 0x1000007, vec![vm, rs1, vd]),
    Spec::new("vlm.v", 0xfff0707f, 0x2b00007, vec![rs1, vd]),
    Spec::new("vloxei16.v", 0xfc00707f, 0xc005007, vec![vm, vs2, rs1, vd]),
    Spec::new("vloxei32.v", 0xfc00707f, 0xc006007, vec![vm, vs2, rs1, vd]),
    Spec::new("vloxei64.v", 0xfc00707f, 0xc007007, vec![vm, vs2, rs1, vd]),
    Spec::new("vloxei8.v", 0xfc00707f, 0xc000007, vec![vm, vs2, rs1, vd]),
    Spec::new("vlse16.v", 0xfc00707f, 0x8005007, vec![vm, rs2, rs1, vd]),
    Spec::new("vlse32.v", 0xfc00707f, 0x8006007, vec![vm, rs2, rs1, vd]),
    Spec::new("vlse64.v", 0xfc00707f, 0x8007007, vec![vm, rs2, rs1, vd]),
    Spec::new("vlse8.v", 0xfc00707f, 0x8000007, vec![vm, rs2, rs1, vd]),
    Spec::new("vluxei16.v", 0xfc00707f, 0x4005007, vec![vm, vs2, rs1, vd]),
    Spec::new("vluxei32.v", 0xfc00707f, 0x4006007, vec![vm, vs2, rs1, vd]),
    Spec::new("vluxei64.v", 0xfc00707f, 0x4007007, vec![vm, vs2, rs1, vd]),
    Spec::new("vluxei8.v", 0xfc00707f, 0x4000007, vec![vm, vs2, rs1, vd]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_0F: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("fence", 0x707f, 0xf, vec![fm, pred, succ, rs1, rd]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_13: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("addi", 0x707f, 0x13, vec![rd, rs1, imm12]),
    Spec::new("andi", 0x707f, 0x7013, vec![rd, rs1, imm12]),
    Spec::new("ori", 0x707f, 0x6013, vec![rd, rs1, imm12]),
    Spec::new("slti", 0x707f, 0x2013, vec![rd, rs1, imm12]),
    Spec::new("sltiu", 0x707f, 0x3013, vec![rd, rs1, imm12]),
    Spec::new("xori", 0x707f, 0x4013, vec![rd, rs1, imm12]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_17: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("auipc", 0x7f, 0x17, vec![rd, imm20]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_23: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("sb", 0x707f, 0x23, vec![imm12hi, rs1, rs2, imm12lo]),
    Spec::new("sh", 0x707f, 0x1023, vec![imm12hi, rs1, rs2, imm12lo]),
    Spec::new("sw", 0x707f, 0x2023, vec![imm12hi, rs1, rs2, imm12lo]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_27: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("fsd", 0x707f, 0x3027, vec![imm12hi, rs1, fs2, imm12lo]),
    Spec::new("fsw", 0x707f, 0x2027, vec![imm12hi, rs1, fs2, imm12lo]),
    Spec::new("vs1r.v", 0xfff0707f, 0x2800027, vec![rs1, vs3]),
    Spec::new("vs2r.v", 0xfff0707f, 0x22800027, vec![rs1, vs3]),
    Spec::new("vs4r.v", 0xfff0707f, 0x62800027, vec![rs1, vs3]),
    Spec::new("vs8r.v", 0xfff0707f, 0xe2800027, vec![rs1, vs3]),
    Spec::new("vse16.v", 0xfdf0707f, 0x5027, vec![vm, rs1, vs3]),
    Spec::new("vse32.v", 0xfdf0707f, 0x6027, vec![vm, rs1, vs3]),
    Spec::new("vse64.v", 0xfdf0707f, 0x7027, vec![vm, rs1, vs3]),
    Spec::new("vse8.v", 0xfdf0707f, 0x27, vec![vm, rs1, vs3]),
    Spec::new("vsm.v", 0xfff0707f, 0x2b00027, vec![rs1, vs3]),
    Spec::new("vsoxei16.v", 0xfc00707f, 0xc005027, vec![vm, vs2, rs1, vs3]),
    Spec::new("vsoxei32.v", 0xfc00707f, 0xc006027, vec![vm, vs2, rs1, vs3]),
    Spec::new("vsoxei64.v", 0xfc00707f, 0xc007027, vec![vm, vs2, rs1, vs3]),
    Spec::new("vsoxei8.v", 0xfc00707f, 0xc000027, vec![vm, vs2, rs1, vs3]),
    Spec::new("vsse16.v", 0xfc00707f, 0x8005027, vec![vm, rs2, rs1, vs3]),
    Spec::new("vsse32.v", 0xfc00707f, 0x8006027, vec![vm, rs2, rs1, vs3]),
    Spec::new("vsse64.v", 0xfc00707f, 0x8007027, vec![vm, rs2, rs1, vs3]),
    Spec::new("vsse8.v", 0xfc00707f, 0x8000027, vec![vm, rs2, rs1, vs3]),
    Spec::new("vsuxei16.v", 0xfc00707f, 0x4005027, vec![vm, vs2, rs1, vs3]),
    Spec::new("vsuxei32.v", 0xfc00707f, 0x4006027, vec![vm, vs2, rs1, vs3]),
    Spec::new("vsuxei64.v", 0xfc00707f, 0x4007027, vec![vm, vs2, rs1, vs3]),
    Spec::new("vsuxei8.v", 0xfc00707f, 0x4000027, vec![vm, vs2, rs1, vs3]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_2F: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("amoadd.w", 0xf800707f, 0x202f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amoand.w", 0xf800707f, 0x6000202f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amomax.w", 0xf800707f, 0xa000202f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amomaxu.w", 0xf800707f, 0xe000202f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amomin.w", 0xf800707f, 0x8000202f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amominu.w", 0xf800707f, 0xc000202f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amoor.w", 0xf800707f, 0x4000202f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amoswap.w", 0xf800707f, 0x800202f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amoxor.w", 0xf800707f, 0x2000202f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("lr.w", 0xf9f0707f, 0x1000202f, vec![rd, rs1, aq, rl]),
    Spec::new("sc.w", 0xf800707f, 0x1800202f, vec![rd, rs1, rs2, aq, rl]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_33: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("add", 0xfe00707f, 0x33, vec![rd, rs1, rs2]),
    Spec::new("and", 0xfe00707f, 0x7033, vec![rd, rs1, rs2]),
    Spec::new("div", 0xfe00707f, 0x2004033, vec![rd, rs1, rs2]),
    Spec::new("divu", 0xfe00707f, 0x2005033, vec![rd, rs1, rs2]),
    Spec::new("mul", 0xfe00707f, 0x2000033, vec![rd, rs1, rs2]),
    Spec::new("mulh", 0xfe00707f, 0x2001033, vec![rd, rs1, rs2]),
    Spec::new("mulhsu", 0xfe00707f, 0x2002033, vec![rd, rs1, rs2]),
    Spec::new("mulhu", 0xfe00707f, 0x2003033, vec![rd, rs1, rs2]),
    Spec::new("or", 0xfe00707f, 0x6033, vec![rd, rs1, rs2]),
    Spec::new("rem", 0xfe00707f, 0x2006033, vec![rd, rs1, rs2]),
    Spec::new("remu", 0xfe00707f, 0x2007033, vec![rd, rs1, rs2]),
    Spec::new("sll", 0xfe00707f, 0x1033, vec![rd, rs1, rs2]),
    Spec::new("slt", 0xfe00707f, 0x2033, vec![rd, rs1, rs2]),
    Spec::new("sltu", 0xfe00707f, 0x3033, vec![rd, rs1, rs2]),
    Spec::new("sra", 0xfe00707f, 0x40005033, vec![rd, rs1, rs2]),
    Spec::new("srl", 0xfe00707f, 0x5033, vec![rd, rs1, rs2]),
    Spec::new("sub", 0xfe00707f, 0x40000033, vec![rd, rs1, rs2]),
    Spec::new("xor", 0xfe00707f, 0x4033, vec![rd, rs1, rs2]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_37: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("lui", 0x7f, 0x37, vec![rd, imm20]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_43: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("fmadd.d", 0x600007f, 0x2000043, vec![fd, fs1, fs2, fs3, rm]),
    Spec::new("fmadd.s", 0x600007f, 0x43, vec![fd, fs1, fs2, fs3, rm]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_47: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("fmsub.d", 0x600007f, 0x2000047, vec![fd, fs1, fs2, fs3, rm]),
    Spec::new("fmsub.s", 0x600007f, 0x47, vec![fd, fs1, fs2, fs3, rm]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_4B: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("fnmsub.d", 0x600007f, 0x200004b, vec![fd, fs1, fs2, fs3, rm]),
    Spec::new("fnmsub.s", 0x600007f, 0x4b, vec![fd, fs1, fs2, fs3, rm]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_4F: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("fnmadd.d", 0x600007f, 0x200004f, vec![fd, fs1, fs2, fs3, rm]),
    Spec::new("fnmadd.s", 0x600007f, 0x4f, vec![fd, fs1, fs2, fs3, rm]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_53: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("fadd.d", 0xfe00007f, 0x2000053, vec![fd, fs1, fs2, rm]),
    Spec::new("fadd.s", 0xfe00007f, 0x53, vec![fd, fs1, fs2, rm]),
    Spec::new("fclass.d", 0xfff0707f, 0xe2001053, vec![rd, fs1]),
    Spec::new("fclass.s", 0xfff0707f, 0xe0001053, vec![rd, fs1]),
    Spec::new("fcvt.d.s", 0xfff0007f, 0x42000053, vec![rd, fs1, rm]),
    Spec::new("fcvt.d.w", 0xfff0007f, 0xd2000053, vec![fd, rs1, rm]),
    Spec::new("fcvt.d.wu", 0xfff0007f, 0xd2100053, vec![fd, rs1, rm]),
    Spec::new("fcvt.s.d", 0xfff0007f, 0x40100053, vec![rd, fs1, rm]),
    Spec::new("fcvt.s.w", 0xfff0007f, 0xd0000053, vec![fd, rs1, rm]),
    Spec::new("fcvt.s.wu", 0xfff0007f, 0xd0100053, vec![fd, rs1, rm]),
    Spec::new("fcvt.w.d", 0xfff0007f, 0xc2000053, vec![rd, fs1, rm]),
    Spec::new("fcvt.w.s", 0xfff0007f, 0xc0000053, vec![rd, fs1, rm]),
    Spec::new("fcvt.wu.d", 0xfff0007f, 0xc2100053, vec![fd, rs1, rm]),
    Spec::new("fcvt.wu.s", 0xfff0007f, 0xc0100053, vec![rd, fs1, rm]),
    Spec::new("fdiv.d", 0xfe00007f, 0x1a000053, vec![fd, fs1, fs2, rm]),
    Spec::new("fdiv.s", 0xfe00007f, 0x18000053, vec![fd, fs1, fs2, rm]),
    Spec::new("feq.d", 0xfe00707f, 0xa2002053, vec![fd, fs1, fs2]),
    Spec::new("feq.s", 0xfe00707f, 0xa0002053, vec![fd, fs1, fs2]),
    Spec::new("fle.d", 0xfe00707f, 0xa2000053, vec![fd, fs1, fs2]),
    Spec::new("fle.s", 0xfe00707f, 0xa0000053, vec![fd, fs1, fs2]),
    Spec::new("flt.d", 0xfe00707f, 0xa2001053, vec![fd, fs1, fs2]),
    Spec::new("flt.s", 0xfe00707f, 0xa0001053, vec![fd, fs1, fs2]),
    Spec::new("fmax.d", 0xfe00707f, 0x2a001053, vec![fd, fs1, fs2]),
    Spec::new("fmax.s", 0xfe00707f, 0x28001053, vec![fd, fs1, fs2]),
    Spec::new("fmin.d", 0xfe00707f, 0x2a000053, vec![fd, fs1, fs2]),
    Spec::new("fmin.s", 0xfe00707f, 0x28000053, vec![fd, fs1, fs2]),
    Spec::new("fmul.d", 0xfe00007f, 0x12000053, vec![fd, fs1, fs2, rm]),
    Spec::new("fmul.s", 0xfe00007f, 0x10000053, vec![fd, fs1, fs2, rm]),
    Spec::new("fmv.w.x", 0xfff0707f, 0xf0000053, vec![fd, rs1]),
    Spec::new("fmv.x.w", 0xfff0707f, 0xe0000053, vec![rd, fs1]),
    Spec::new("fsgnj.d", 0xfe00707f, 0x22000053, vec![fd, fs1, fs2]),
    Spec::new("fsgnj.s", 0xfe00707f, 0x20000053, vec![fd, fs1, fs2]),
    Spec::new("fsgnjn.d", 0xfe00707f, 0x22001053, vec![fd, fs1, fs2]),
    Spec::new("fsgnjn.s", 0xfe00707f, 0x20001053, vec![fd, fs1, fs2]),
    Spec::new("fsgnjx.d", 0xfe00707f, 0x22002053, vec![fd, fs1, fs2]),
    Spec::new("fsgnjx.s", 0xfe00707f, 0x20002053, vec![fd, fs1, fs2]),
    Spec::new("fsqrt.d", 0xfff0007f, 0x5a000053, vec![fd, fs1, rm]),
    Spec::new("fsqrt.s", 0xfff0007f, 0x58000053, vec![fd, fs1, rm]),
    Spec::new("fsub.d", 0xfe00007f, 0xa000053, vec![fd, fs1, fs2, rm]),
    Spec::new("fsub.s", 0xfe00007f, 0x8000053, vec![fd, fs1, fs2, rm]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_57: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("vaadd.vv", 0xfc00707f, 0x24002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vaadd.vx", 0xfc00707f, 0x24006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vaaddu.vv", 0xfc00707f, 0x20002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vaaddu.vx", 0xfc00707f, 0x20006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vadc.vim", 0xfe00707f, 0x40003057, vec![vs2, simm5, vd]),
    Spec::new("vadc.vvm", 0xfe00707f, 0x40000057, vec![vs2, vs1, vd]),
    Spec::new("vadc.vxm", 0xfe00707f, 0x40004057, vec![vs2, rs1, vd]),
    Spec::new("vadd.vi", 0xfc00707f, 0x3057, vec![vm, vs2, simm5, vd]),
    Spec::new("vadd.vv", 0xfc00707f, 0x57, vec![vm, vs2, vs1, vd]),
    Spec::new("vadd.vx", 0xfc00707f, 0x4057, vec![vm, vs2, rs1, vd]),
    Spec::new("vand.vi", 0xfc00707f, 0x24003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vand.vv", 0xfc00707f, 0x24000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vand.vx", 0xfc00707f, 0x24004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vasub.vv", 0xfc00707f, 0x2c002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vasub.vx", 0xfc00707f, 0x2c006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vasubu.vv", 0xfc00707f, 0x28002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vasubu.vx", 0xfc00707f, 0x28006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vcompress.vm", 0xfe00707f, 0x5e002057, vec![vs2, vs1, vd]),
    Spec::new("vcpop.m", 0xfc0ff07f, 0x40082057, vec![vm, vs2, rd]),
    Spec::new("vdiv.vv", 0xfc00707f, 0x84002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vdiv.vx", 0xfc00707f, 0x84006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vdivu.vv", 0xfc00707f, 0x80002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vdivu.vx", 0xfc00707f, 0x80006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfadd.vf", 0xfc00707f, 0x5057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfadd.vv", 0xfc00707f, 0x1057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfclass.v", 0xfc0ff07f, 0x4c081057, vec![vm, vs2, vd]),
    Spec::new("vfcvt.f.x.v", 0xfc0ff07f, 0x48019057, vec![vm, vs2, vd]),
    Spec::new("vfcvt.f.xu.v", 0xfc0ff07f, 0x48011057, vec![vm, vs2, vd]),
    Spec::new("vfcvt.rtz.x.f.v", 0xfc0ff07f, 0x48039057, vec![vm, vs2, vd]),
    Spec::new("vfcvt.rtz.xu.f.v", 0xfc0ff07f, 0x48031057, vec![vm, vs2, vd]),
    Spec::new("vfcvt.x.f.v", 0xfc0ff07f, 0x48009057, vec![vm, vs2, vd]),
    Spec::new("vfcvt.xu.f.v", 0xfc0ff07f, 0x48001057, vec![vm, vs2, vd]),
    Spec::new("vfdiv.vf", 0xfc00707f, 0x80005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfdiv.vv", 0xfc00707f, 0x80001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfirst.m", 0xfc0ff07f, 0x4008a057, vec![vm, vs2, rd]),
    Spec::new("vfmacc.vf", 0xfc00707f, 0xb0005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfmacc.vv", 0xfc00707f, 0xb0001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfmadd.vf", 0xfc00707f, 0xa0005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfmadd.vv", 0xfc00707f, 0xa0001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfmax.vf", 0xfc00707f, 0x18005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfmax.vv", 0xfc00707f, 0x18001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfmerge.vfm", 0xfe00707f, 0x5c005057, vec![vs2, rs1, vd]),
    Spec::new("vfmin.vf", 0xfc00707f, 0x10005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfmin.vv", 0xfc00707f, 0x10001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfmsac.vf", 0xfc00707f, 0xb8005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfmsac.vv", 0xfc00707f, 0xb8001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfmsub.vf", 0xfc00707f, 0xa8005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfmsub.vv", 0xfc00707f, 0xa8001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfmul.vf", 0xfc00707f, 0x90005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfmul.vv", 0xfc00707f, 0x90001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfmv.f.s", 0xfe0ff07f, 0x42001057, vec![vs2, rd]),
    Spec::new("vfmv.s.f", 0xfff0707f, 0x42005057, vec![rs1, vd]),
    Spec::new("vfmv.v.f", 0xfff0707f, 0x5e005057, vec![rs1, vd]),
    Spec::new("vfncvt.f.f.w", 0xfc0ff07f, 0x480a1057, vec![vm, vs2, vd]),
    Spec::new("vfncvt.f.x.w", 0xfc0ff07f, 0x48099057, vec![vm, vs2, vd]),
    Spec::new("vfncvt.f.xu.w", 0xfc0ff07f, 0x48091057, vec![vm, vs2, vd]),
    Spec::new("vfncvt.rod.f.f.w", 0xfc0ff07f, 0x480a9057, vec![vm, vs2, vd]),
    Spec::new("vfncvt.rtz.x.f.w", 0xfc0ff07f, 0x480b9057, vec![vm, vs2, vd]),
    Spec::new("vfncvt.rtz.xu.f.w", 0xfc0ff07f, 0x480b1057, vec![vm, vs2, vd]),
    Spec::new("vfncvt.x.f.w", 0xfc0ff07f, 0x48089057, vec![vm, vs2, vd]),
    Spec::new("vfncvt.xu.f.w", 0xfc0ff07f, 0x48081057, vec![vm, vs2, vd]),
    Spec::new("vfnmacc.vf", 0xfc00707f, 0xb4005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfnmacc.vv", 0xfc00707f, 0xb4001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfnmadd.vf", 0xfc00707f, 0xa4005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfnmadd.vv", 0xfc00707f, 0xa4001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfnmsac.vf", 0xfc00707f, 0xbc005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfnmsac.vv", 0xfc00707f, 0xbc001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfnmsub.vf", 0xfc00707f, 0xac005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfnmsub.vv", 0xfc00707f, 0xac001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfrdiv.vf", 0xfc00707f, 0x84005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfrec7.v", 0xfc0ff07f, 0x4c029057, vec![vm, vs2, vd]),
    Spec::new("vfredmax.vs", 0xfc00707f, 0x1c001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfredmin.vs", 0xfc00707f, 0x14001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfredosum.vs", 0xfc00707f, 0xc001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfredusum.vs", 0xfc00707f, 0x4001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfrsqrt7.v", 0xfc0ff07f, 0x4c021057, vec![vm, vs2, vd]),
    Spec::new("vfrsub.vf", 0xfc00707f, 0x9c005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfsgnj.vf", 0xfc00707f, 0x20005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfsgnj.vv", 0xfc00707f, 0x20001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfsgnjn.vf", 0xfc00707f, 0x24005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfsgnjn.vv", 0xfc00707f, 0x24001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfsgnjx.vf", 0xfc00707f, 0x28005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfsgnjx.vv", 0xfc00707f, 0x28001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfslide1down.vf", 0xfc00707f, 0x3c005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfslide1up.vf", 0xfc00707f, 0x38005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfsqrt.v", 0xfc0ff07f, 0x4c001057, vec![vm, vs2, vd]),
    Spec::new("vfsub.vf", 0xfc00707f, 0x8005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfsub.vv", 0xfc00707f, 0x8001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfwadd.vf", 0xfc00707f, 0xc0005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfwadd.vv", 0xfc00707f, 0xc0001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfwadd.wf", 0xfc00707f, 0xd0005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfwadd.wv", 0xfc00707f, 0xd0001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfwcvt.f.f.v", 0xfc0ff07f, 0x48061057, vec![vm, vs2, vd]),
    Spec::new("vfwcvt.f.x.v", 0xfc0ff07f, 0x48059057, vec![vm, vs2, vd]),
    Spec::new("vfwcvt.f.xu.v", 0xfc0ff07f, 0x48051057, vec![vm, vs2, vd]),
    Spec::new("vfwcvt.rtz.x.f.v", 0xfc0ff07f, 0x48079057, vec![vm, vs2, vd]),
    Spec::new("vfwcvt.rtz.xu.f.v", 0xfc0ff07f, 0x48071057, vec![vm, vs2, vd]),
    Spec::new("vfwcvt.x.f.v", 0xfc0ff07f, 0x48049057, vec![vm, vs2, vd]),
    Spec::new("vfwcvt.xu.f.v", 0xfc0ff07f, 0x48041057, vec![vm, vs2, vd]),
    Spec::new("vfwmacc.vf", 0xfc00707f, 0xf0005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfwmacc.vv", 0xfc00707f, 0xf0001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfwmsac.vf", 0xfc00707f, 0xf8005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfwmsac.vv", 0xfc00707f, 0xf8001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfwmul.vf", 0xfc00707f, 0xe0005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfwmul.vv", 0xfc00707f, 0xe0001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfwnmacc.vf", 0xfc00707f, 0xf4005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfwnmacc.vv", 0xfc00707f, 0xf4001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfwnmsac.vf", 0xfc00707f, 0xfc005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfwnmsac.vv", 0xfc00707f, 0xfc001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfwredosum.vs", 0xfc00707f, 0xcc001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfwredusum.vs", 0xfc00707f, 0xc4001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfwsub.vf", 0xfc00707f, 0xc8005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfwsub.vv", 0xfc00707f, 0xc8001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vfwsub.wf", 0xfc00707f, 0xd8005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vfwsub.wv", 0xfc00707f, 0xd8001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vid.v", 0xfdfff07f, 0x5008a057, vec![vm, vd]),
    Spec::new("viota.m", 0xfc0ff07f, 0x50082057, vec![vm, vs2, vd]),
    Spec::new("vmacc.vv", 0xfc00707f, 0xb4002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmacc.vx", 0xfc00707f, 0xb4006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmadc.vi", 0xfe00707f, 0x46003057, vec![vs2, simm5, vd]),
    Spec::new("vmadc.vim", 0xfe00707f, 0x44003057, vec![vs2, simm5, vd]),
    Spec::new("vmadc.vv", 0xfe00707f, 0x46000057, vec![vs2, vs1, vd]),
    Spec::new("vmadc.vvm", 0xfe00707f, 0x44000057, vec![vs2, vs1, vd]),
    Spec::new("vmadc.vx", 0xfe00707f, 0x46004057, vec![vs2, rs1, vd]),
    Spec::new("vmadc.vxm", 0xfe00707f, 0x44004057, vec![vs2, rs1, vd]),
    Spec::new("vmadd.vv", 0xfc00707f, 0xa4002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmadd.vx", 0xfc00707f, 0xa4006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmand.mm", 0xfe00707f, 0x66002057, vec![vs2, vs1, vd]),
    Spec::new("vmandn.mm", 0xfe00707f, 0x62002057, vec![vs2, vs1, vd]),
    Spec::new("vmax.vv", 0xfc00707f, 0x1c000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmax.vx", 0xfc00707f, 0x1c004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmaxu.vv", 0xfc00707f, 0x18000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmaxu.vx", 0xfc00707f, 0x18004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmerge.vim", 0xfe00707f, 0x5c003057, vec![vs2, simm5, vd]),
    Spec::new("vmerge.vvm", 0xfe00707f, 0x5c000057, vec![vs2, vs1, vd]),
    Spec::new("vmerge.vxm", 0xfe00707f, 0x5c004057, vec![vs2, rs1, vd]),
    Spec::new("vmfeq.vf", 0xfc00707f, 0x60005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmfeq.vv", 0xfc00707f, 0x60001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmfge.vf", 0xfc00707f, 0x7c005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmfgt.vf", 0xfc00707f, 0x74005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmfle.vf", 0xfc00707f, 0x64005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmfle.vv", 0xfc00707f, 0x64001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmflt.vf", 0xfc00707f, 0x6c005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmflt.vv", 0xfc00707f, 0x6c001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmfne.vf", 0xfc00707f, 0x70005057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmfne.vv", 0xfc00707f, 0x70001057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmin.vv", 0xfc00707f, 0x14000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmin.vx", 0xfc00707f, 0x14004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vminu.vv", 0xfc00707f, 0x10000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vminu.vx", 0xfc00707f, 0x10004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmnand.mm", 0xfe00707f, 0x76002057, vec![vs2, vs1, vd]),
    Spec::new("vmnor.mm", 0xfe00707f, 0x7a002057, vec![vs2, vs1, vd]),
    Spec::new("vmor.mm", 0xfe00707f, 0x6a002057, vec![vs2, vs1, vd]),
    Spec::new("vmorn.mm", 0xfe00707f, 0x72002057, vec![vs2, vs1, vd]),
    Spec::new("vmsbc.vv", 0xfe00707f, 0x4e000057, vec![vs2, vs1, vd]),
    Spec::new("vmsbc.vvm", 0xfe00707f, 0x4c000057, vec![vs2, vs1, vd]),
    Spec::new("vmsbc.vx", 0xfe00707f, 0x4e004057, vec![vs2, rs1, vd]),
    Spec::new("vmsbc.vxm", 0xfe00707f, 0x4c004057, vec![vs2, rs1, vd]),
    Spec::new("vmsbf.m", 0xfc0ff07f, 0x5000a057, vec![vm, vs2, vd]),
    Spec::new("vmseq.vi", 0xfc00707f, 0x60003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vmseq.vv", 0xfc00707f, 0x60000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmseq.vx", 0xfc00707f, 0x60004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmsgt.vi", 0xfc00707f, 0x7c003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vmsgt.vx", 0xfc00707f, 0x7c004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmsgtu.vi", 0xfc00707f, 0x78003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vmsgtu.vx", 0xfc00707f, 0x78004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmsif.m", 0xfc0ff07f, 0x5001a057, vec![vm, vs2, vd]),
    Spec::new("vmsle.vi", 0xfc00707f, 0x74003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vmsle.vv", 0xfc00707f, 0x74000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmsle.vx", 0xfc00707f, 0x74004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmsleu.vi", 0xfc00707f, 0x70003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vmsleu.vv", 0xfc00707f, 0x70000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmsleu.vx", 0xfc00707f, 0x70004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmslt.vv", 0xfc00707f, 0x6c000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmslt.vx", 0xfc00707f, 0x6c004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmsltu.vv", 0xfc00707f, 0x68000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmsltu.vx", 0xfc00707f, 0x68004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmsne.vi", 0xfc00707f, 0x64003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vmsne.vv", 0xfc00707f, 0x64000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmsne.vx", 0xfc00707f, 0x64004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmsof.m", 0xfc0ff07f, 0x50012057, vec![vm, vs2, vd]),
    Spec::new("vmul.vv", 0xfc00707f, 0x94002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmul.vx", 0xfc00707f, 0x94006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmulh.vv", 0xfc00707f, 0x9c002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmulh.vx", 0xfc00707f, 0x9c006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmulhsu.vv", 0xfc00707f, 0x98002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmulhsu.vx", 0xfc00707f, 0x98006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmulhu.vv", 0xfc00707f, 0x90002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vmulhu.vx", 0xfc00707f, 0x90006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vmv1r.v", 0xfe0ff07f, 0x9e003057, vec![vs2, vd]),
    Spec::new("vmv2r.v", 0xfe0ff07f, 0x9e00b057, vec![vs2, vd]),
    Spec::new("vmv4r.v", 0xfe0ff07f, 0x9e01b057, vec![vs2, vd]),
    Spec::new("vmv8r.v", 0xfe0ff07f, 0x9e03b057, vec![vs2, vd]),
    Spec::new("vmv.s.x", 0xfff0707f, 0x42006057, vec![rs1, vd]),
    Spec::new("vmv.v.i", 0xfff0707f, 0x5e003057, vec![simm5, vd]),
    Spec::new("vmv.v.v", 0xfff0707f, 0x5e000057, vec![vs1, vd]),
    Spec::new("vmv.v.x", 0xfff0707f, 0x5e004057, vec![rs1, vd]),
    Spec::new("vmv.x.s", 0xfe0ff07f, 0x42002057, vec![vs2, rd]),
    Spec::new("vmxnor.mm", 0xfe00707f, 0x7e002057, vec![vs2, vs1, vd]),
    Spec::new("vmxor.mm", 0xfe00707f, 0x6e002057, vec![vs2, vs1, vd]),
    Spec::new("vnclip.wi", 0xfc00707f, 0xbc003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vnclip.wv", 0xfc00707f, 0xbc000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vnclip.wx", 0xfc00707f, 0xbc004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vnclipu.wi", 0xfc00707f, 0xb8003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vnclipu.wv", 0xfc00707f, 0xb8000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vnclipu.wx", 0xfc00707f, 0xb8004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vnmsac.vv", 0xfc00707f, 0xbc002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vnmsac.vx", 0xfc00707f, 0xbc006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vnmsub.vv", 0xfc00707f, 0xac002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vnmsub.vx", 0xfc00707f, 0xac006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vnsra.wi", 0xfc00707f, 0xb4003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vnsra.wv", 0xfc00707f, 0xb4000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vnsra.wx", 0xfc00707f, 0xb4004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vnsrl.wi", 0xfc00707f, 0xb0003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vnsrl.wv", 0xfc00707f, 0xb0000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vnsrl.wx", 0xfc00707f, 0xb0004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vor.vi", 0xfc00707f, 0x28003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vor.vv", 0xfc00707f, 0x28000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vor.vx", 0xfc00707f, 0x28004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vredand.vs", 0xfc00707f, 0x4002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vredmax.vs", 0xfc00707f, 0x1c002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vredmaxu.vs", 0xfc00707f, 0x18002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vredmin.vs", 0xfc00707f, 0x14002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vredminu.vs", 0xfc00707f, 0x10002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vredor.vs", 0xfc00707f, 0x8002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vredsum.vs", 0xfc00707f, 0x2057, vec![vm, vs2, vs1, vd]),
    Spec::new("vredxor.vs", 0xfc00707f, 0xc002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vrem.vv", 0xfc00707f, 0x8c002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vrem.vx", 0xfc00707f, 0x8c006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vremu.vv", 0xfc00707f, 0x88002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vremu.vx", 0xfc00707f, 0x88006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vrgather.vi", 0xfc00707f, 0x30003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vrgather.vv", 0xfc00707f, 0x30000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vrgather.vx", 0xfc00707f, 0x30004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vrgatherei16.vv", 0xfc00707f, 0x38000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vrsub.vi", 0xfc00707f, 0xc003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vrsub.vx", 0xfc00707f, 0xc004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vsadd.vi", 0xfc00707f, 0x84003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vsadd.vv", 0xfc00707f, 0x84000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vsadd.vx", 0xfc00707f, 0x84004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vsaddu.vi", 0xfc00707f, 0x80003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vsaddu.vv", 0xfc00707f, 0x80000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vsaddu.vx", 0xfc00707f, 0x80004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vsbc.vvm", 0xfe00707f, 0x48000057, vec![vs2, vs1, vd]),
    Spec::new("vsbc.vxm", 0xfe00707f, 0x48004057, vec![vs2, rs1, vd]),
    Spec::new("vsetivli", 0xc000707f, 0xc0007057, vec![zimm10, zimm5, rd]),
    Spec::new("vsetvl", 0xfe00707f, 0x80007057, vec![rs2, rs1, rd]),
    Spec::new("vsetvli", 0x8000707f, 0x7057, vec![zimm11, rs1, rd]),
    Spec::new("vsext.vf2", 0xfc0ff07f, 0x4803a057, vec![vm, vs2, vd]),
    Spec::new("vsext.vf4", 0xfc0ff07f, 0x4802a057, vec![vm, vs2, vd]),
    Spec::new("vsext.vf8", 0xfc0ff07f, 0x4801a057, vec![vm, vs2, vd]),
    Spec::new("vslide1down.vx", 0xfc00707f, 0x3c006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vslide1up.vx", 0xfc00707f, 0x38006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vslidedown.vi", 0xfc00707f, 0x3c003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vslidedown.vx", 0xfc00707f, 0x3c004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vslideup.vi", 0xfc00707f, 0x38003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vslideup.vx", 0xfc00707f, 0x38004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vsll.vi", 0xfc00707f, 0x94003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vsll.vv", 0xfc00707f, 0x94000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vsll.vx", 0xfc00707f, 0x94004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vsmul.vv", 0xfc00707f, 0x9c000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vsmul.vx", 0xfc00707f, 0x9c004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vsra.vi", 0xfc00707f, 0xa4003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vsra.vv", 0xfc00707f, 0xa4000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vsra.vx", 0xfc00707f, 0xa4004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vsrl.vi", 0xfc00707f, 0xa0003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vsrl.vv", 0xfc00707f, 0xa0000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vsrl.vx", 0xfc00707f, 0xa0004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vssra.vi", 0xfc00707f, 0xac003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vssra.vv", 0xfc00707f, 0xac000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vssra.vx", 0xfc00707f, 0xac004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vssrl.vi", 0xfc00707f, 0xa8003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vssrl.vv", 0xfc00707f, 0xa8000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vssrl.vx", 0xfc00707f, 0xa8004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vssub.vv", 0xfc00707f, 0x8c000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vssub.vx", 0xfc00707f, 0x8c004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vssubu.vv", 0xfc00707f, 0x88000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vssubu.vx", 0xfc00707f, 0x88004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vsub.vv", 0xfc00707f, 0x8000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vsub.vx", 0xfc00707f, 0x8004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwadd.vv", 0xfc00707f, 0xc4002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwadd.vx", 0xfc00707f, 0xc4006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwadd.wv", 0xfc00707f, 0xd4002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwadd.wx", 0xfc00707f, 0xd4006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwaddu.vv", 0xfc00707f, 0xc0002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwaddu.vx", 0xfc00707f, 0xc0006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwaddu.wv", 0xfc00707f, 0xd0002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwaddu.wx", 0xfc00707f, 0xd0006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwmacc.vv", 0xfc00707f, 0xf4002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwmacc.vx", 0xfc00707f, 0xf4006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwmaccsu.vv", 0xfc00707f, 0xfc002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwmaccsu.vx", 0xfc00707f, 0xfc006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwmaccu.vv", 0xfc00707f, 0xf0002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwmaccu.vx", 0xfc00707f, 0xf0006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwmaccus.vx", 0xfc00707f, 0xf8006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwmul.vv", 0xfc00707f, 0xec002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwmul.vx", 0xfc00707f, 0xec006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwmulsu.vv", 0xfc00707f, 0xe8002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwmulsu.vx", 0xfc00707f, 0xe8006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwmulu.vv", 0xfc00707f, 0xe0002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwmulu.vx", 0xfc00707f, 0xe0006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwredsum.vs", 0xfc00707f, 0xc4000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwredsumu.vs", 0xfc00707f, 0xc0000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwsub.vv", 0xfc00707f, 0xcc002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwsub.vx", 0xfc00707f, 0xcc006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwsub.wv", 0xfc00707f, 0xdc002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwsub.wx", 0xfc00707f, 0xdc006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwsubu.vv", 0xfc00707f, 0xc8002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwsubu.vx", 0xfc00707f, 0xc8006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vwsubu.wv", 0xfc00707f, 0xd8002057, vec![vm, vs2, vs1, vd]),
    Spec::new("vwsubu.wx", 0xfc00707f, 0xd8006057, vec![vm, vs2, rs1, vd]),
    Spec::new("vxor.vi", 0xfc00707f, 0x2c003057, vec![vm, vs2, simm5, vd]),
    Spec::new("vxor.vv", 0xfc00707f, 0x2c000057, vec![vm, vs2, vs1, vd]),
    Spec::new("vxor.vx", 0xfc00707f, 0x2c004057, vec![vm, vs2, rs1, vd]),
    Spec::new("vzext.vf2", 0xfc0ff07f, 0x48032057, vec![vm, vs2, vd]),
    Spec::new("vzext.vf4", 0xfc0ff07f, 0x48022057, vec![vm, vs2, vd]),
    Spec::new("vzext.vf8", 0xfc0ff07f, 0x48012057, vec![vm, vs2, vd]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_63: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("beq", 0x707f, 0x63, vec![bimm12hi, rs1, rs2, bimm12lo]),
    Spec::new("bge", 0x707f, 0x5063, vec![bimm12hi, rs1, rs2, bimm12lo]),
    Spec::new("bgeu", 0x707f, 0x7063, vec![bimm12hi, rs1, rs2, bimm12lo]),
    Spec::new("blt", 0x707f, 0x4063, vec![bimm12hi, rs1, rs2, bimm12lo]),
    Spec::new("bltu", 0x707f, 0x6063, vec![bimm12hi, rs1, rs2, bimm12lo]),
    Spec::new("bne", 0x707f, 0x1063, vec![bimm12hi, rs1, rs2, bimm12lo]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_67: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("jalr", 0x707f, 0x67, vec![rd, rs1, imm12]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_6F: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("jal", 0x7f, 0x6f, vec![rd, jimm20]),
]);

pub static RV_ISA_SPECS_GENERIC_FULL_OPCODE_73: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("csrrc", 0x707f, 0x3073, vec![rd, rs1, csr]),
    Spec::new("csrrci", 0x707f, 0x7073, vec![rd, csr, zimm5]),
    Spec::new("csrrs", 0x707f, 0x2073, vec![rd, rs1, csr]),
    Spec::new("csrrsi", 0x707f, 0x6073, vec![rd, csr, zimm5]),
    Spec::new("csrrw", 0x707f, 0x1073, vec![rd, rs1, csr]),
    Spec::new("csrrwi", 0x707f, 0x5073, vec![rd, csr, zimm5]),
    Spec::new("ebreak", 0xffffffff, 0x100073, vec![]),
    Spec::new("ecall", 0xffffffff, 0x73, vec![]),
    Spec::new("mret", 0xffffffff, 0x30200073, vec![]),
    Spec::new("sfence.vma", 0xfe007fff, 0x12000073, vec![rs1, rs2]),
    Spec::new("sret", 0xffffffff, 0x10200073, vec![]),
    Spec::new("wfi", 0xffffffff, 0x10500073, vec![]),
]);


// Full instructions (32-bit) - 32-bit specific grouped by opcode

// Full instructions (32-bit) - 64-bit specific grouped by opcode
pub static RV_ISA_SPECS_64_FULL_OPCODE_03: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("ld", 0x707f, 0x3003, vec![rd, rs1, imm12]),
    Spec::new("lwu", 0x707f, 0x6003, vec![rd, rs1, imm12]),
]);

pub static RV_ISA_SPECS_64_FULL_OPCODE_13: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("slli", 0xfc00707f, 0x1013, vec![rd, rs1, shamtd]),
    Spec::new("srai", 0xfc00707f, 0x40005013, vec![rd, rs1, shamtd]),
    Spec::new("srli", 0xfc00707f, 0x5013, vec![rd, rs1, shamtd]),
]);

pub static RV_ISA_SPECS_64_FULL_OPCODE_1B: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("addiw", 0x707f, 0x1b, vec![rd, rs1, imm12]),
    Spec::new("slliw", 0xfe00707f, 0x101b, vec![rd, rs1, shamtw]),
    Spec::new("sraiw", 0xfe00707f, 0x4000501b, vec![rd, rs1, shamtw]),
    Spec::new("srliw", 0xfe00707f, 0x501b, vec![rd, rs1, shamtw]),
]);

pub static RV_ISA_SPECS_64_FULL_OPCODE_23: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("sd", 0x707f, 0x3023, vec![imm12hi, rs1, rs2, imm12lo]),
]);

pub static RV_ISA_SPECS_64_FULL_OPCODE_2F: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("amoadd.d", 0xf800707f, 0x302f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amoand.d", 0xf800707f, 0x6000302f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amomax.d", 0xf800707f, 0xa000302f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amomaxu.d", 0xf800707f, 0xe000302f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amomin.d", 0xf800707f, 0x8000302f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amominu.d", 0xf800707f, 0xc000302f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amoor.d", 0xf800707f, 0x4000302f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amoswap.d", 0xf800707f, 0x800302f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("amoxor.d", 0xf800707f, 0x2000302f, vec![rd, rs1, rs2, aq, rl]),
    Spec::new("lr.d", 0xf9f0707f, 0x1000302f, vec![rd, rs1, aq, rl]),
    Spec::new("sc.d", 0xf800707f, 0x1800302f, vec![rd, rs1, rs2, aq, rl]),
]);

pub static RV_ISA_SPECS_64_FULL_OPCODE_3B: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("addw", 0xfe00707f, 0x3b, vec![rd, rs1, rs2]),
    Spec::new("divuw", 0xfe00707f, 0x200503b, vec![rd, rs1, rs2]),
    Spec::new("divw", 0xfe00707f, 0x200403b, vec![rd, rs1, rs2]),
    Spec::new("mulw", 0xfe00707f, 0x200003b, vec![rd, rs1, rs2]),
    Spec::new("remuw", 0xfe00707f, 0x200703b, vec![rd, rs1, rs2]),
    Spec::new("remw", 0xfe00707f, 0x200603b, vec![rd, rs1, rs2]),
    Spec::new("sllw", 0xfe00707f, 0x103b, vec![rd, rs1, rs2]),
    Spec::new("sraw", 0xfe00707f, 0x4000503b, vec![rd, rs1, rs2]),
    Spec::new("srlw", 0xfe00707f, 0x503b, vec![rd, rs1, rs2]),
    Spec::new("subw", 0xfe00707f, 0x4000003b, vec![rd, rs1, rs2]),
]);

pub static RV_ISA_SPECS_64_FULL_OPCODE_53: Lazy<Vec<Spec>> = Lazy::new(|| vec![
    Spec::new("fcvt.d.l", 0xfff0007f, 0xd2200053, vec![rd, rs1, rm]),
    Spec::new("fcvt.d.lu", 0xfff0007f, 0xd2300053, vec![rd, rs1, rm]),
    Spec::new("fcvt.l.d", 0xfff0007f, 0xc2200053, vec![rd, rs1, rm]),
    Spec::new("fcvt.l.s", 0xfff0007f, 0xc0200053, vec![rd, rs1, rm]),
    Spec::new("fcvt.lu.d", 0xfff0007f, 0xc2300053, vec![rd, rs1, rm]),
    Spec::new("fcvt.lu.s", 0xfff0007f, 0xc0300053, vec![rd, rs1, rm]),
    Spec::new("fcvt.s.l", 0xfff0007f, 0xd0200053, vec![rd, rs1, rm]),
    Spec::new("fcvt.s.lu", 0xfff0007f, 0xd0300053, vec![rd, rs1, rm]),
    Spec::new("fmv.d.x", 0xfff0707f, 0xf2000053, vec![rd, rs1]),
    Spec::new("fmv.x.d", 0xfff0707f, 0xe2000053, vec![rd, rs1]),
]);




// Opcode lookup API - dynamically generated lookup functions

/// Get generic full instruction specs by opcode
pub fn get_generic_full_specs_by_opcode(opcode: u8) -> Option<&'static Lazy<Vec<Spec>>> {
    match opcode {
        0x3 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_03),
        0x7 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_07),
        0xf => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_0F),
        0x13 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_13),
        0x17 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_17),
        0x23 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_23),
        0x27 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_27),
        0x2f => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_2F),
        0x33 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_33),
        0x37 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_37),
        0x43 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_43),
        0x47 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_47),
        0x4b => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_4B),
        0x4f => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_4F),
        0x53 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_53),
        0x57 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_57),
        0x63 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_63),
        0x67 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_67),
        0x6f => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_6F),
        0x73 => Some(&RV_ISA_SPECS_GENERIC_FULL_OPCODE_73),
        _ => None,
    }
}

/// Get 32-bit specific full instruction specs by opcode
pub fn get_32_full_specs_by_opcode(opcode: u8) -> Option<&'static Lazy<Vec<Spec>>> {
    match opcode {
        _ => None,
    }
}

/// Get 64-bit specific full instruction specs by opcode
pub fn get_64_full_specs_by_opcode(opcode: u8) -> Option<&'static Lazy<Vec<Spec>>> {
    match opcode {
        0x3 => Some(&RV_ISA_SPECS_64_FULL_OPCODE_03),
        0x13 => Some(&RV_ISA_SPECS_64_FULL_OPCODE_13),
        0x1b => Some(&RV_ISA_SPECS_64_FULL_OPCODE_1B),
        0x23 => Some(&RV_ISA_SPECS_64_FULL_OPCODE_23),
        0x2f => Some(&RV_ISA_SPECS_64_FULL_OPCODE_2F),
        0x3b => Some(&RV_ISA_SPECS_64_FULL_OPCODE_3B),
        0x53 => Some(&RV_ISA_SPECS_64_FULL_OPCODE_53),
        _ => None,
    }
}