rv32m1_ri5cy_pac/lpuart0/
ctrl.rs

1#[doc = "Reader of register CTRL"]
2pub type R = crate::R<u32, super::CTRL>;
3#[doc = "Writer for register CTRL"]
4pub type W = crate::W<u32, super::CTRL>;
5#[doc = "Register CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTRL {
7  type Type = u32;
8  #[inline(always)]
9  fn reset_value() -> Self::Type {
10    0
11  }
12}
13#[doc = "Parity Type\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15pub enum PT_A {
16  #[doc = "0: Even parity."]
17  PT_0,
18  #[doc = "1: Odd parity."]
19  PT_1,
20}
21impl From<PT_A> for bool {
22  #[inline(always)]
23  fn from(variant: PT_A) -> Self {
24    match variant {
25      PT_A::PT_0 => false,
26      PT_A::PT_1 => true,
27    }
28  }
29}
30#[doc = "Reader of field `PT`"]
31pub type PT_R = crate::R<bool, PT_A>;
32impl PT_R {
33  #[doc = r"Get enumerated values variant"]
34  #[inline(always)]
35  pub fn variant(&self) -> PT_A {
36    match self.bits {
37      false => PT_A::PT_0,
38      true => PT_A::PT_1,
39    }
40  }
41  #[doc = "Checks if the value of the field is `PT_0`"]
42  #[inline(always)]
43  pub fn is_pt_0(&self) -> bool {
44    *self == PT_A::PT_0
45  }
46  #[doc = "Checks if the value of the field is `PT_1`"]
47  #[inline(always)]
48  pub fn is_pt_1(&self) -> bool {
49    *self == PT_A::PT_1
50  }
51}
52#[doc = "Write proxy for field `PT`"]
53pub struct PT_W<'a> {
54  w: &'a mut W,
55}
56impl<'a> PT_W<'a> {
57  #[doc = r"Writes `variant` to the field"]
58  #[inline(always)]
59  pub fn variant(self, variant: PT_A) -> &'a mut W {
60    {
61      self.bit(variant.into())
62    }
63  }
64  #[doc = "Even parity."]
65  #[inline(always)]
66  pub fn pt_0(self) -> &'a mut W {
67    self.variant(PT_A::PT_0)
68  }
69  #[doc = "Odd parity."]
70  #[inline(always)]
71  pub fn pt_1(self) -> &'a mut W {
72    self.variant(PT_A::PT_1)
73  }
74  #[doc = r"Sets the field bit"]
75  #[inline(always)]
76  pub fn set_bit(self) -> &'a mut W {
77    self.bit(true)
78  }
79  #[doc = r"Clears the field bit"]
80  #[inline(always)]
81  pub fn clear_bit(self) -> &'a mut W {
82    self.bit(false)
83  }
84  #[doc = r"Writes raw bits to the field"]
85  #[inline(always)]
86  pub fn bit(self, value: bool) -> &'a mut W {
87    self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
88    self.w
89  }
90}
91#[doc = "Parity Enable\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq)]
93pub enum PE_A {
94  #[doc = "0: No hardware parity generation or checking."]
95  PE_0,
96  #[doc = "1: Parity enabled."]
97  PE_1,
98}
99impl From<PE_A> for bool {
100  #[inline(always)]
101  fn from(variant: PE_A) -> Self {
102    match variant {
103      PE_A::PE_0 => false,
104      PE_A::PE_1 => true,
105    }
106  }
107}
108#[doc = "Reader of field `PE`"]
109pub type PE_R = crate::R<bool, PE_A>;
110impl PE_R {
111  #[doc = r"Get enumerated values variant"]
112  #[inline(always)]
113  pub fn variant(&self) -> PE_A {
114    match self.bits {
115      false => PE_A::PE_0,
116      true => PE_A::PE_1,
117    }
118  }
119  #[doc = "Checks if the value of the field is `PE_0`"]
120  #[inline(always)]
121  pub fn is_pe_0(&self) -> bool {
122    *self == PE_A::PE_0
123  }
124  #[doc = "Checks if the value of the field is `PE_1`"]
125  #[inline(always)]
126  pub fn is_pe_1(&self) -> bool {
127    *self == PE_A::PE_1
128  }
129}
130#[doc = "Write proxy for field `PE`"]
131pub struct PE_W<'a> {
132  w: &'a mut W,
133}
134impl<'a> PE_W<'a> {
135  #[doc = r"Writes `variant` to the field"]
136  #[inline(always)]
137  pub fn variant(self, variant: PE_A) -> &'a mut W {
138    {
139      self.bit(variant.into())
140    }
141  }
142  #[doc = "No hardware parity generation or checking."]
143  #[inline(always)]
144  pub fn pe_0(self) -> &'a mut W {
145    self.variant(PE_A::PE_0)
146  }
147  #[doc = "Parity enabled."]
148  #[inline(always)]
149  pub fn pe_1(self) -> &'a mut W {
150    self.variant(PE_A::PE_1)
151  }
152  #[doc = r"Sets the field bit"]
153  #[inline(always)]
154  pub fn set_bit(self) -> &'a mut W {
155    self.bit(true)
156  }
157  #[doc = r"Clears the field bit"]
158  #[inline(always)]
159  pub fn clear_bit(self) -> &'a mut W {
160    self.bit(false)
161  }
162  #[doc = r"Writes raw bits to the field"]
163  #[inline(always)]
164  pub fn bit(self, value: bool) -> &'a mut W {
165    self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
166    self.w
167  }
168}
169#[doc = "Idle Line Type Select\n\nValue on reset: 0"]
170#[derive(Clone, Copy, Debug, PartialEq)]
171pub enum ILT_A {
172  #[doc = "0: Idle character bit count starts after start bit."]
173  ILT_0,
174  #[doc = "1: Idle character bit count starts after stop bit."]
175  ILT_1,
176}
177impl From<ILT_A> for bool {
178  #[inline(always)]
179  fn from(variant: ILT_A) -> Self {
180    match variant {
181      ILT_A::ILT_0 => false,
182      ILT_A::ILT_1 => true,
183    }
184  }
185}
186#[doc = "Reader of field `ILT`"]
187pub type ILT_R = crate::R<bool, ILT_A>;
188impl ILT_R {
189  #[doc = r"Get enumerated values variant"]
190  #[inline(always)]
191  pub fn variant(&self) -> ILT_A {
192    match self.bits {
193      false => ILT_A::ILT_0,
194      true => ILT_A::ILT_1,
195    }
196  }
197  #[doc = "Checks if the value of the field is `ILT_0`"]
198  #[inline(always)]
199  pub fn is_ilt_0(&self) -> bool {
200    *self == ILT_A::ILT_0
201  }
202  #[doc = "Checks if the value of the field is `ILT_1`"]
203  #[inline(always)]
204  pub fn is_ilt_1(&self) -> bool {
205    *self == ILT_A::ILT_1
206  }
207}
208#[doc = "Write proxy for field `ILT`"]
209pub struct ILT_W<'a> {
210  w: &'a mut W,
211}
212impl<'a> ILT_W<'a> {
213  #[doc = r"Writes `variant` to the field"]
214  #[inline(always)]
215  pub fn variant(self, variant: ILT_A) -> &'a mut W {
216    {
217      self.bit(variant.into())
218    }
219  }
220  #[doc = "Idle character bit count starts after start bit."]
221  #[inline(always)]
222  pub fn ilt_0(self) -> &'a mut W {
223    self.variant(ILT_A::ILT_0)
224  }
225  #[doc = "Idle character bit count starts after stop bit."]
226  #[inline(always)]
227  pub fn ilt_1(self) -> &'a mut W {
228    self.variant(ILT_A::ILT_1)
229  }
230  #[doc = r"Sets the field bit"]
231  #[inline(always)]
232  pub fn set_bit(self) -> &'a mut W {
233    self.bit(true)
234  }
235  #[doc = r"Clears the field bit"]
236  #[inline(always)]
237  pub fn clear_bit(self) -> &'a mut W {
238    self.bit(false)
239  }
240  #[doc = r"Writes raw bits to the field"]
241  #[inline(always)]
242  pub fn bit(self, value: bool) -> &'a mut W {
243    self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
244    self.w
245  }
246}
247#[doc = "Receiver Wakeup Method Select\n\nValue on reset: 0"]
248#[derive(Clone, Copy, Debug, PartialEq)]
249pub enum WAKE_A {
250  #[doc = "0: Configures RWU for idle-line wakeup."]
251  WAKE_0,
252  #[doc = "1: Configures RWU with address-mark wakeup."]
253  WAKE_1,
254}
255impl From<WAKE_A> for bool {
256  #[inline(always)]
257  fn from(variant: WAKE_A) -> Self {
258    match variant {
259      WAKE_A::WAKE_0 => false,
260      WAKE_A::WAKE_1 => true,
261    }
262  }
263}
264#[doc = "Reader of field `WAKE`"]
265pub type WAKE_R = crate::R<bool, WAKE_A>;
266impl WAKE_R {
267  #[doc = r"Get enumerated values variant"]
268  #[inline(always)]
269  pub fn variant(&self) -> WAKE_A {
270    match self.bits {
271      false => WAKE_A::WAKE_0,
272      true => WAKE_A::WAKE_1,
273    }
274  }
275  #[doc = "Checks if the value of the field is `WAKE_0`"]
276  #[inline(always)]
277  pub fn is_wake_0(&self) -> bool {
278    *self == WAKE_A::WAKE_0
279  }
280  #[doc = "Checks if the value of the field is `WAKE_1`"]
281  #[inline(always)]
282  pub fn is_wake_1(&self) -> bool {
283    *self == WAKE_A::WAKE_1
284  }
285}
286#[doc = "Write proxy for field `WAKE`"]
287pub struct WAKE_W<'a> {
288  w: &'a mut W,
289}
290impl<'a> WAKE_W<'a> {
291  #[doc = r"Writes `variant` to the field"]
292  #[inline(always)]
293  pub fn variant(self, variant: WAKE_A) -> &'a mut W {
294    {
295      self.bit(variant.into())
296    }
297  }
298  #[doc = "Configures RWU for idle-line wakeup."]
299  #[inline(always)]
300  pub fn wake_0(self) -> &'a mut W {
301    self.variant(WAKE_A::WAKE_0)
302  }
303  #[doc = "Configures RWU with address-mark wakeup."]
304  #[inline(always)]
305  pub fn wake_1(self) -> &'a mut W {
306    self.variant(WAKE_A::WAKE_1)
307  }
308  #[doc = r"Sets the field bit"]
309  #[inline(always)]
310  pub fn set_bit(self) -> &'a mut W {
311    self.bit(true)
312  }
313  #[doc = r"Clears the field bit"]
314  #[inline(always)]
315  pub fn clear_bit(self) -> &'a mut W {
316    self.bit(false)
317  }
318  #[doc = r"Writes raw bits to the field"]
319  #[inline(always)]
320  pub fn bit(self, value: bool) -> &'a mut W {
321    self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
322    self.w
323  }
324}
325#[doc = "9-Bit or 8-Bit Mode Select\n\nValue on reset: 0"]
326#[derive(Clone, Copy, Debug, PartialEq)]
327pub enum M_A {
328  #[doc = "0: Receiver and transmitter use 8-bit data characters."]
329  M_0,
330  #[doc = "1: Receiver and transmitter use 9-bit data characters."]
331  M_1,
332}
333impl From<M_A> for bool {
334  #[inline(always)]
335  fn from(variant: M_A) -> Self {
336    match variant {
337      M_A::M_0 => false,
338      M_A::M_1 => true,
339    }
340  }
341}
342#[doc = "Reader of field `M`"]
343pub type M_R = crate::R<bool, M_A>;
344impl M_R {
345  #[doc = r"Get enumerated values variant"]
346  #[inline(always)]
347  pub fn variant(&self) -> M_A {
348    match self.bits {
349      false => M_A::M_0,
350      true => M_A::M_1,
351    }
352  }
353  #[doc = "Checks if the value of the field is `M_0`"]
354  #[inline(always)]
355  pub fn is_m_0(&self) -> bool {
356    *self == M_A::M_0
357  }
358  #[doc = "Checks if the value of the field is `M_1`"]
359  #[inline(always)]
360  pub fn is_m_1(&self) -> bool {
361    *self == M_A::M_1
362  }
363}
364#[doc = "Write proxy for field `M`"]
365pub struct M_W<'a> {
366  w: &'a mut W,
367}
368impl<'a> M_W<'a> {
369  #[doc = r"Writes `variant` to the field"]
370  #[inline(always)]
371  pub fn variant(self, variant: M_A) -> &'a mut W {
372    {
373      self.bit(variant.into())
374    }
375  }
376  #[doc = "Receiver and transmitter use 8-bit data characters."]
377  #[inline(always)]
378  pub fn m_0(self) -> &'a mut W {
379    self.variant(M_A::M_0)
380  }
381  #[doc = "Receiver and transmitter use 9-bit data characters."]
382  #[inline(always)]
383  pub fn m_1(self) -> &'a mut W {
384    self.variant(M_A::M_1)
385  }
386  #[doc = r"Sets the field bit"]
387  #[inline(always)]
388  pub fn set_bit(self) -> &'a mut W {
389    self.bit(true)
390  }
391  #[doc = r"Clears the field bit"]
392  #[inline(always)]
393  pub fn clear_bit(self) -> &'a mut W {
394    self.bit(false)
395  }
396  #[doc = r"Writes raw bits to the field"]
397  #[inline(always)]
398  pub fn bit(self, value: bool) -> &'a mut W {
399    self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
400    self.w
401  }
402}
403#[doc = "Receiver Source Select\n\nValue on reset: 0"]
404#[derive(Clone, Copy, Debug, PartialEq)]
405pub enum RSRC_A {
406  #[doc = "0: Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin."]
407  RSRC_0,
408  #[doc = "1: Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input."]
409  RSRC_1,
410}
411impl From<RSRC_A> for bool {
412  #[inline(always)]
413  fn from(variant: RSRC_A) -> Self {
414    match variant {
415      RSRC_A::RSRC_0 => false,
416      RSRC_A::RSRC_1 => true,
417    }
418  }
419}
420#[doc = "Reader of field `RSRC`"]
421pub type RSRC_R = crate::R<bool, RSRC_A>;
422impl RSRC_R {
423  #[doc = r"Get enumerated values variant"]
424  #[inline(always)]
425  pub fn variant(&self) -> RSRC_A {
426    match self.bits {
427      false => RSRC_A::RSRC_0,
428      true => RSRC_A::RSRC_1,
429    }
430  }
431  #[doc = "Checks if the value of the field is `RSRC_0`"]
432  #[inline(always)]
433  pub fn is_rsrc_0(&self) -> bool {
434    *self == RSRC_A::RSRC_0
435  }
436  #[doc = "Checks if the value of the field is `RSRC_1`"]
437  #[inline(always)]
438  pub fn is_rsrc_1(&self) -> bool {
439    *self == RSRC_A::RSRC_1
440  }
441}
442#[doc = "Write proxy for field `RSRC`"]
443pub struct RSRC_W<'a> {
444  w: &'a mut W,
445}
446impl<'a> RSRC_W<'a> {
447  #[doc = r"Writes `variant` to the field"]
448  #[inline(always)]
449  pub fn variant(self, variant: RSRC_A) -> &'a mut W {
450    {
451      self.bit(variant.into())
452    }
453  }
454  #[doc = "Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin."]
455  #[inline(always)]
456  pub fn rsrc_0(self) -> &'a mut W {
457    self.variant(RSRC_A::RSRC_0)
458  }
459  #[doc = "Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input."]
460  #[inline(always)]
461  pub fn rsrc_1(self) -> &'a mut W {
462    self.variant(RSRC_A::RSRC_1)
463  }
464  #[doc = r"Sets the field bit"]
465  #[inline(always)]
466  pub fn set_bit(self) -> &'a mut W {
467    self.bit(true)
468  }
469  #[doc = r"Clears the field bit"]
470  #[inline(always)]
471  pub fn clear_bit(self) -> &'a mut W {
472    self.bit(false)
473  }
474  #[doc = r"Writes raw bits to the field"]
475  #[inline(always)]
476  pub fn bit(self, value: bool) -> &'a mut W {
477    self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
478    self.w
479  }
480}
481#[doc = "Doze Enable\n\nValue on reset: 0"]
482#[derive(Clone, Copy, Debug, PartialEq)]
483pub enum DOZEEN_A {
484  #[doc = "0: LPUART is enabled in Doze mode."]
485  DOZEEN_0,
486  #[doc = "1: LPUART is disabled in Doze mode."]
487  DOZEEN_1,
488}
489impl From<DOZEEN_A> for bool {
490  #[inline(always)]
491  fn from(variant: DOZEEN_A) -> Self {
492    match variant {
493      DOZEEN_A::DOZEEN_0 => false,
494      DOZEEN_A::DOZEEN_1 => true,
495    }
496  }
497}
498#[doc = "Reader of field `DOZEEN`"]
499pub type DOZEEN_R = crate::R<bool, DOZEEN_A>;
500impl DOZEEN_R {
501  #[doc = r"Get enumerated values variant"]
502  #[inline(always)]
503  pub fn variant(&self) -> DOZEEN_A {
504    match self.bits {
505      false => DOZEEN_A::DOZEEN_0,
506      true => DOZEEN_A::DOZEEN_1,
507    }
508  }
509  #[doc = "Checks if the value of the field is `DOZEEN_0`"]
510  #[inline(always)]
511  pub fn is_dozeen_0(&self) -> bool {
512    *self == DOZEEN_A::DOZEEN_0
513  }
514  #[doc = "Checks if the value of the field is `DOZEEN_1`"]
515  #[inline(always)]
516  pub fn is_dozeen_1(&self) -> bool {
517    *self == DOZEEN_A::DOZEEN_1
518  }
519}
520#[doc = "Write proxy for field `DOZEEN`"]
521pub struct DOZEEN_W<'a> {
522  w: &'a mut W,
523}
524impl<'a> DOZEEN_W<'a> {
525  #[doc = r"Writes `variant` to the field"]
526  #[inline(always)]
527  pub fn variant(self, variant: DOZEEN_A) -> &'a mut W {
528    {
529      self.bit(variant.into())
530    }
531  }
532  #[doc = "LPUART is enabled in Doze mode."]
533  #[inline(always)]
534  pub fn dozeen_0(self) -> &'a mut W {
535    self.variant(DOZEEN_A::DOZEEN_0)
536  }
537  #[doc = "LPUART is disabled in Doze mode."]
538  #[inline(always)]
539  pub fn dozeen_1(self) -> &'a mut W {
540    self.variant(DOZEEN_A::DOZEEN_1)
541  }
542  #[doc = r"Sets the field bit"]
543  #[inline(always)]
544  pub fn set_bit(self) -> &'a mut W {
545    self.bit(true)
546  }
547  #[doc = r"Clears the field bit"]
548  #[inline(always)]
549  pub fn clear_bit(self) -> &'a mut W {
550    self.bit(false)
551  }
552  #[doc = r"Writes raw bits to the field"]
553  #[inline(always)]
554  pub fn bit(self, value: bool) -> &'a mut W {
555    self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
556    self.w
557  }
558}
559#[doc = "Loop Mode Select\n\nValue on reset: 0"]
560#[derive(Clone, Copy, Debug, PartialEq)]
561pub enum LOOPS_A {
562  #[doc = "0: Normal operation - RXD and TXD use separate pins."]
563  LOOPS_0,
564  #[doc = "1: Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit)."]
565  LOOPS_1,
566}
567impl From<LOOPS_A> for bool {
568  #[inline(always)]
569  fn from(variant: LOOPS_A) -> Self {
570    match variant {
571      LOOPS_A::LOOPS_0 => false,
572      LOOPS_A::LOOPS_1 => true,
573    }
574  }
575}
576#[doc = "Reader of field `LOOPS`"]
577pub type LOOPS_R = crate::R<bool, LOOPS_A>;
578impl LOOPS_R {
579  #[doc = r"Get enumerated values variant"]
580  #[inline(always)]
581  pub fn variant(&self) -> LOOPS_A {
582    match self.bits {
583      false => LOOPS_A::LOOPS_0,
584      true => LOOPS_A::LOOPS_1,
585    }
586  }
587  #[doc = "Checks if the value of the field is `LOOPS_0`"]
588  #[inline(always)]
589  pub fn is_loops_0(&self) -> bool {
590    *self == LOOPS_A::LOOPS_0
591  }
592  #[doc = "Checks if the value of the field is `LOOPS_1`"]
593  #[inline(always)]
594  pub fn is_loops_1(&self) -> bool {
595    *self == LOOPS_A::LOOPS_1
596  }
597}
598#[doc = "Write proxy for field `LOOPS`"]
599pub struct LOOPS_W<'a> {
600  w: &'a mut W,
601}
602impl<'a> LOOPS_W<'a> {
603  #[doc = r"Writes `variant` to the field"]
604  #[inline(always)]
605  pub fn variant(self, variant: LOOPS_A) -> &'a mut W {
606    {
607      self.bit(variant.into())
608    }
609  }
610  #[doc = "Normal operation - RXD and TXD use separate pins."]
611  #[inline(always)]
612  pub fn loops_0(self) -> &'a mut W {
613    self.variant(LOOPS_A::LOOPS_0)
614  }
615  #[doc = "Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit)."]
616  #[inline(always)]
617  pub fn loops_1(self) -> &'a mut W {
618    self.variant(LOOPS_A::LOOPS_1)
619  }
620  #[doc = r"Sets the field bit"]
621  #[inline(always)]
622  pub fn set_bit(self) -> &'a mut W {
623    self.bit(true)
624  }
625  #[doc = r"Clears the field bit"]
626  #[inline(always)]
627  pub fn clear_bit(self) -> &'a mut W {
628    self.bit(false)
629  }
630  #[doc = r"Writes raw bits to the field"]
631  #[inline(always)]
632  pub fn bit(self, value: bool) -> &'a mut W {
633    self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
634    self.w
635  }
636}
637#[doc = "Idle Configuration\n\nValue on reset: 0"]
638#[derive(Clone, Copy, Debug, PartialEq)]
639pub enum IDLECFG_A {
640  #[doc = "0: 1 idle character"]
641  IDLECFG_0,
642  #[doc = "1: 2 idle characters"]
643  IDLECFG_1,
644  #[doc = "2: 4 idle characters"]
645  IDLECFG_2,
646  #[doc = "3: 8 idle characters"]
647  IDLECFG_3,
648  #[doc = "4: 16 idle characters"]
649  IDLECFG_4,
650  #[doc = "5: 32 idle characters"]
651  IDLECFG_5,
652  #[doc = "6: 64 idle characters"]
653  IDLECFG_6,
654  #[doc = "7: 128 idle characters"]
655  IDLECFG_7,
656}
657impl From<IDLECFG_A> for u8 {
658  #[inline(always)]
659  fn from(variant: IDLECFG_A) -> Self {
660    match variant {
661      IDLECFG_A::IDLECFG_0 => 0,
662      IDLECFG_A::IDLECFG_1 => 1,
663      IDLECFG_A::IDLECFG_2 => 2,
664      IDLECFG_A::IDLECFG_3 => 3,
665      IDLECFG_A::IDLECFG_4 => 4,
666      IDLECFG_A::IDLECFG_5 => 5,
667      IDLECFG_A::IDLECFG_6 => 6,
668      IDLECFG_A::IDLECFG_7 => 7,
669    }
670  }
671}
672#[doc = "Reader of field `IDLECFG`"]
673pub type IDLECFG_R = crate::R<u8, IDLECFG_A>;
674impl IDLECFG_R {
675  #[doc = r"Get enumerated values variant"]
676  #[inline(always)]
677  pub fn variant(&self) -> IDLECFG_A {
678    match self.bits {
679      0 => IDLECFG_A::IDLECFG_0,
680      1 => IDLECFG_A::IDLECFG_1,
681      2 => IDLECFG_A::IDLECFG_2,
682      3 => IDLECFG_A::IDLECFG_3,
683      4 => IDLECFG_A::IDLECFG_4,
684      5 => IDLECFG_A::IDLECFG_5,
685      6 => IDLECFG_A::IDLECFG_6,
686      7 => IDLECFG_A::IDLECFG_7,
687      _ => unreachable!(),
688    }
689  }
690  #[doc = "Checks if the value of the field is `IDLECFG_0`"]
691  #[inline(always)]
692  pub fn is_idlecfg_0(&self) -> bool {
693    *self == IDLECFG_A::IDLECFG_0
694  }
695  #[doc = "Checks if the value of the field is `IDLECFG_1`"]
696  #[inline(always)]
697  pub fn is_idlecfg_1(&self) -> bool {
698    *self == IDLECFG_A::IDLECFG_1
699  }
700  #[doc = "Checks if the value of the field is `IDLECFG_2`"]
701  #[inline(always)]
702  pub fn is_idlecfg_2(&self) -> bool {
703    *self == IDLECFG_A::IDLECFG_2
704  }
705  #[doc = "Checks if the value of the field is `IDLECFG_3`"]
706  #[inline(always)]
707  pub fn is_idlecfg_3(&self) -> bool {
708    *self == IDLECFG_A::IDLECFG_3
709  }
710  #[doc = "Checks if the value of the field is `IDLECFG_4`"]
711  #[inline(always)]
712  pub fn is_idlecfg_4(&self) -> bool {
713    *self == IDLECFG_A::IDLECFG_4
714  }
715  #[doc = "Checks if the value of the field is `IDLECFG_5`"]
716  #[inline(always)]
717  pub fn is_idlecfg_5(&self) -> bool {
718    *self == IDLECFG_A::IDLECFG_5
719  }
720  #[doc = "Checks if the value of the field is `IDLECFG_6`"]
721  #[inline(always)]
722  pub fn is_idlecfg_6(&self) -> bool {
723    *self == IDLECFG_A::IDLECFG_6
724  }
725  #[doc = "Checks if the value of the field is `IDLECFG_7`"]
726  #[inline(always)]
727  pub fn is_idlecfg_7(&self) -> bool {
728    *self == IDLECFG_A::IDLECFG_7
729  }
730}
731#[doc = "Write proxy for field `IDLECFG`"]
732pub struct IDLECFG_W<'a> {
733  w: &'a mut W,
734}
735impl<'a> IDLECFG_W<'a> {
736  #[doc = r"Writes `variant` to the field"]
737  #[inline(always)]
738  pub fn variant(self, variant: IDLECFG_A) -> &'a mut W {
739    {
740      self.bits(variant.into())
741    }
742  }
743  #[doc = "1 idle character"]
744  #[inline(always)]
745  pub fn idlecfg_0(self) -> &'a mut W {
746    self.variant(IDLECFG_A::IDLECFG_0)
747  }
748  #[doc = "2 idle characters"]
749  #[inline(always)]
750  pub fn idlecfg_1(self) -> &'a mut W {
751    self.variant(IDLECFG_A::IDLECFG_1)
752  }
753  #[doc = "4 idle characters"]
754  #[inline(always)]
755  pub fn idlecfg_2(self) -> &'a mut W {
756    self.variant(IDLECFG_A::IDLECFG_2)
757  }
758  #[doc = "8 idle characters"]
759  #[inline(always)]
760  pub fn idlecfg_3(self) -> &'a mut W {
761    self.variant(IDLECFG_A::IDLECFG_3)
762  }
763  #[doc = "16 idle characters"]
764  #[inline(always)]
765  pub fn idlecfg_4(self) -> &'a mut W {
766    self.variant(IDLECFG_A::IDLECFG_4)
767  }
768  #[doc = "32 idle characters"]
769  #[inline(always)]
770  pub fn idlecfg_5(self) -> &'a mut W {
771    self.variant(IDLECFG_A::IDLECFG_5)
772  }
773  #[doc = "64 idle characters"]
774  #[inline(always)]
775  pub fn idlecfg_6(self) -> &'a mut W {
776    self.variant(IDLECFG_A::IDLECFG_6)
777  }
778  #[doc = "128 idle characters"]
779  #[inline(always)]
780  pub fn idlecfg_7(self) -> &'a mut W {
781    self.variant(IDLECFG_A::IDLECFG_7)
782  }
783  #[doc = r"Writes raw bits to the field"]
784  #[inline(always)]
785  pub fn bits(self, value: u8) -> &'a mut W {
786    self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
787    self.w
788  }
789}
790#[doc = "7-Bit Mode Select\n\nValue on reset: 0"]
791#[derive(Clone, Copy, Debug, PartialEq)]
792pub enum M7_A {
793  #[doc = "0: Receiver and transmitter use 8-bit to 10-bit data characters."]
794  M7_0,
795  #[doc = "1: Receiver and transmitter use 7-bit data characters."]
796  M7_1,
797}
798impl From<M7_A> for bool {
799  #[inline(always)]
800  fn from(variant: M7_A) -> Self {
801    match variant {
802      M7_A::M7_0 => false,
803      M7_A::M7_1 => true,
804    }
805  }
806}
807#[doc = "Reader of field `M7`"]
808pub type M7_R = crate::R<bool, M7_A>;
809impl M7_R {
810  #[doc = r"Get enumerated values variant"]
811  #[inline(always)]
812  pub fn variant(&self) -> M7_A {
813    match self.bits {
814      false => M7_A::M7_0,
815      true => M7_A::M7_1,
816    }
817  }
818  #[doc = "Checks if the value of the field is `M7_0`"]
819  #[inline(always)]
820  pub fn is_m7_0(&self) -> bool {
821    *self == M7_A::M7_0
822  }
823  #[doc = "Checks if the value of the field is `M7_1`"]
824  #[inline(always)]
825  pub fn is_m7_1(&self) -> bool {
826    *self == M7_A::M7_1
827  }
828}
829#[doc = "Write proxy for field `M7`"]
830pub struct M7_W<'a> {
831  w: &'a mut W,
832}
833impl<'a> M7_W<'a> {
834  #[doc = r"Writes `variant` to the field"]
835  #[inline(always)]
836  pub fn variant(self, variant: M7_A) -> &'a mut W {
837    {
838      self.bit(variant.into())
839    }
840  }
841  #[doc = "Receiver and transmitter use 8-bit to 10-bit data characters."]
842  #[inline(always)]
843  pub fn m7_0(self) -> &'a mut W {
844    self.variant(M7_A::M7_0)
845  }
846  #[doc = "Receiver and transmitter use 7-bit data characters."]
847  #[inline(always)]
848  pub fn m7_1(self) -> &'a mut W {
849    self.variant(M7_A::M7_1)
850  }
851  #[doc = r"Sets the field bit"]
852  #[inline(always)]
853  pub fn set_bit(self) -> &'a mut W {
854    self.bit(true)
855  }
856  #[doc = r"Clears the field bit"]
857  #[inline(always)]
858  pub fn clear_bit(self) -> &'a mut W {
859    self.bit(false)
860  }
861  #[doc = r"Writes raw bits to the field"]
862  #[inline(always)]
863  pub fn bit(self, value: bool) -> &'a mut W {
864    self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
865    self.w
866  }
867}
868#[doc = "Match 2 Interrupt Enable\n\nValue on reset: 0"]
869#[derive(Clone, Copy, Debug, PartialEq)]
870pub enum MA2IE_A {
871  #[doc = "0: MA2F interrupt disabled"]
872  MA2IE_0,
873  #[doc = "1: MA2F interrupt enabled"]
874  MA2IE_1,
875}
876impl From<MA2IE_A> for bool {
877  #[inline(always)]
878  fn from(variant: MA2IE_A) -> Self {
879    match variant {
880      MA2IE_A::MA2IE_0 => false,
881      MA2IE_A::MA2IE_1 => true,
882    }
883  }
884}
885#[doc = "Reader of field `MA2IE`"]
886pub type MA2IE_R = crate::R<bool, MA2IE_A>;
887impl MA2IE_R {
888  #[doc = r"Get enumerated values variant"]
889  #[inline(always)]
890  pub fn variant(&self) -> MA2IE_A {
891    match self.bits {
892      false => MA2IE_A::MA2IE_0,
893      true => MA2IE_A::MA2IE_1,
894    }
895  }
896  #[doc = "Checks if the value of the field is `MA2IE_0`"]
897  #[inline(always)]
898  pub fn is_ma2ie_0(&self) -> bool {
899    *self == MA2IE_A::MA2IE_0
900  }
901  #[doc = "Checks if the value of the field is `MA2IE_1`"]
902  #[inline(always)]
903  pub fn is_ma2ie_1(&self) -> bool {
904    *self == MA2IE_A::MA2IE_1
905  }
906}
907#[doc = "Write proxy for field `MA2IE`"]
908pub struct MA2IE_W<'a> {
909  w: &'a mut W,
910}
911impl<'a> MA2IE_W<'a> {
912  #[doc = r"Writes `variant` to the field"]
913  #[inline(always)]
914  pub fn variant(self, variant: MA2IE_A) -> &'a mut W {
915    {
916      self.bit(variant.into())
917    }
918  }
919  #[doc = "MA2F interrupt disabled"]
920  #[inline(always)]
921  pub fn ma2ie_0(self) -> &'a mut W {
922    self.variant(MA2IE_A::MA2IE_0)
923  }
924  #[doc = "MA2F interrupt enabled"]
925  #[inline(always)]
926  pub fn ma2ie_1(self) -> &'a mut W {
927    self.variant(MA2IE_A::MA2IE_1)
928  }
929  #[doc = r"Sets the field bit"]
930  #[inline(always)]
931  pub fn set_bit(self) -> &'a mut W {
932    self.bit(true)
933  }
934  #[doc = r"Clears the field bit"]
935  #[inline(always)]
936  pub fn clear_bit(self) -> &'a mut W {
937    self.bit(false)
938  }
939  #[doc = r"Writes raw bits to the field"]
940  #[inline(always)]
941  pub fn bit(self, value: bool) -> &'a mut W {
942    self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
943    self.w
944  }
945}
946#[doc = "Match 1 Interrupt Enable\n\nValue on reset: 0"]
947#[derive(Clone, Copy, Debug, PartialEq)]
948pub enum MA1IE_A {
949  #[doc = "0: MA1F interrupt disabled"]
950  MA1IE_0,
951  #[doc = "1: MA1F interrupt enabled"]
952  MA1IE_1,
953}
954impl From<MA1IE_A> for bool {
955  #[inline(always)]
956  fn from(variant: MA1IE_A) -> Self {
957    match variant {
958      MA1IE_A::MA1IE_0 => false,
959      MA1IE_A::MA1IE_1 => true,
960    }
961  }
962}
963#[doc = "Reader of field `MA1IE`"]
964pub type MA1IE_R = crate::R<bool, MA1IE_A>;
965impl MA1IE_R {
966  #[doc = r"Get enumerated values variant"]
967  #[inline(always)]
968  pub fn variant(&self) -> MA1IE_A {
969    match self.bits {
970      false => MA1IE_A::MA1IE_0,
971      true => MA1IE_A::MA1IE_1,
972    }
973  }
974  #[doc = "Checks if the value of the field is `MA1IE_0`"]
975  #[inline(always)]
976  pub fn is_ma1ie_0(&self) -> bool {
977    *self == MA1IE_A::MA1IE_0
978  }
979  #[doc = "Checks if the value of the field is `MA1IE_1`"]
980  #[inline(always)]
981  pub fn is_ma1ie_1(&self) -> bool {
982    *self == MA1IE_A::MA1IE_1
983  }
984}
985#[doc = "Write proxy for field `MA1IE`"]
986pub struct MA1IE_W<'a> {
987  w: &'a mut W,
988}
989impl<'a> MA1IE_W<'a> {
990  #[doc = r"Writes `variant` to the field"]
991  #[inline(always)]
992  pub fn variant(self, variant: MA1IE_A) -> &'a mut W {
993    {
994      self.bit(variant.into())
995    }
996  }
997  #[doc = "MA1F interrupt disabled"]
998  #[inline(always)]
999  pub fn ma1ie_0(self) -> &'a mut W {
1000    self.variant(MA1IE_A::MA1IE_0)
1001  }
1002  #[doc = "MA1F interrupt enabled"]
1003  #[inline(always)]
1004  pub fn ma1ie_1(self) -> &'a mut W {
1005    self.variant(MA1IE_A::MA1IE_1)
1006  }
1007  #[doc = r"Sets the field bit"]
1008  #[inline(always)]
1009  pub fn set_bit(self) -> &'a mut W {
1010    self.bit(true)
1011  }
1012  #[doc = r"Clears the field bit"]
1013  #[inline(always)]
1014  pub fn clear_bit(self) -> &'a mut W {
1015    self.bit(false)
1016  }
1017  #[doc = r"Writes raw bits to the field"]
1018  #[inline(always)]
1019  pub fn bit(self, value: bool) -> &'a mut W {
1020    self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
1021    self.w
1022  }
1023}
1024#[doc = "Send Break\n\nValue on reset: 0"]
1025#[derive(Clone, Copy, Debug, PartialEq)]
1026pub enum SBK_A {
1027  #[doc = "0: Normal transmitter operation."]
1028  SBK_0,
1029  #[doc = "1: Queue break character(s) to be sent."]
1030  SBK_1,
1031}
1032impl From<SBK_A> for bool {
1033  #[inline(always)]
1034  fn from(variant: SBK_A) -> Self {
1035    match variant {
1036      SBK_A::SBK_0 => false,
1037      SBK_A::SBK_1 => true,
1038    }
1039  }
1040}
1041#[doc = "Reader of field `SBK`"]
1042pub type SBK_R = crate::R<bool, SBK_A>;
1043impl SBK_R {
1044  #[doc = r"Get enumerated values variant"]
1045  #[inline(always)]
1046  pub fn variant(&self) -> SBK_A {
1047    match self.bits {
1048      false => SBK_A::SBK_0,
1049      true => SBK_A::SBK_1,
1050    }
1051  }
1052  #[doc = "Checks if the value of the field is `SBK_0`"]
1053  #[inline(always)]
1054  pub fn is_sbk_0(&self) -> bool {
1055    *self == SBK_A::SBK_0
1056  }
1057  #[doc = "Checks if the value of the field is `SBK_1`"]
1058  #[inline(always)]
1059  pub fn is_sbk_1(&self) -> bool {
1060    *self == SBK_A::SBK_1
1061  }
1062}
1063#[doc = "Write proxy for field `SBK`"]
1064pub struct SBK_W<'a> {
1065  w: &'a mut W,
1066}
1067impl<'a> SBK_W<'a> {
1068  #[doc = r"Writes `variant` to the field"]
1069  #[inline(always)]
1070  pub fn variant(self, variant: SBK_A) -> &'a mut W {
1071    {
1072      self.bit(variant.into())
1073    }
1074  }
1075  #[doc = "Normal transmitter operation."]
1076  #[inline(always)]
1077  pub fn sbk_0(self) -> &'a mut W {
1078    self.variant(SBK_A::SBK_0)
1079  }
1080  #[doc = "Queue break character(s) to be sent."]
1081  #[inline(always)]
1082  pub fn sbk_1(self) -> &'a mut W {
1083    self.variant(SBK_A::SBK_1)
1084  }
1085  #[doc = r"Sets the field bit"]
1086  #[inline(always)]
1087  pub fn set_bit(self) -> &'a mut W {
1088    self.bit(true)
1089  }
1090  #[doc = r"Clears the field bit"]
1091  #[inline(always)]
1092  pub fn clear_bit(self) -> &'a mut W {
1093    self.bit(false)
1094  }
1095  #[doc = r"Writes raw bits to the field"]
1096  #[inline(always)]
1097  pub fn bit(self, value: bool) -> &'a mut W {
1098    self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
1099    self.w
1100  }
1101}
1102#[doc = "Receiver Wakeup Control\n\nValue on reset: 0"]
1103#[derive(Clone, Copy, Debug, PartialEq)]
1104pub enum RWU_A {
1105  #[doc = "0: Normal receiver operation."]
1106  RWU_0,
1107  #[doc = "1: LPUART receiver in standby waiting for wakeup condition."]
1108  RWU_1,
1109}
1110impl From<RWU_A> for bool {
1111  #[inline(always)]
1112  fn from(variant: RWU_A) -> Self {
1113    match variant {
1114      RWU_A::RWU_0 => false,
1115      RWU_A::RWU_1 => true,
1116    }
1117  }
1118}
1119#[doc = "Reader of field `RWU`"]
1120pub type RWU_R = crate::R<bool, RWU_A>;
1121impl RWU_R {
1122  #[doc = r"Get enumerated values variant"]
1123  #[inline(always)]
1124  pub fn variant(&self) -> RWU_A {
1125    match self.bits {
1126      false => RWU_A::RWU_0,
1127      true => RWU_A::RWU_1,
1128    }
1129  }
1130  #[doc = "Checks if the value of the field is `RWU_0`"]
1131  #[inline(always)]
1132  pub fn is_rwu_0(&self) -> bool {
1133    *self == RWU_A::RWU_0
1134  }
1135  #[doc = "Checks if the value of the field is `RWU_1`"]
1136  #[inline(always)]
1137  pub fn is_rwu_1(&self) -> bool {
1138    *self == RWU_A::RWU_1
1139  }
1140}
1141#[doc = "Write proxy for field `RWU`"]
1142pub struct RWU_W<'a> {
1143  w: &'a mut W,
1144}
1145impl<'a> RWU_W<'a> {
1146  #[doc = r"Writes `variant` to the field"]
1147  #[inline(always)]
1148  pub fn variant(self, variant: RWU_A) -> &'a mut W {
1149    {
1150      self.bit(variant.into())
1151    }
1152  }
1153  #[doc = "Normal receiver operation."]
1154  #[inline(always)]
1155  pub fn rwu_0(self) -> &'a mut W {
1156    self.variant(RWU_A::RWU_0)
1157  }
1158  #[doc = "LPUART receiver in standby waiting for wakeup condition."]
1159  #[inline(always)]
1160  pub fn rwu_1(self) -> &'a mut W {
1161    self.variant(RWU_A::RWU_1)
1162  }
1163  #[doc = r"Sets the field bit"]
1164  #[inline(always)]
1165  pub fn set_bit(self) -> &'a mut W {
1166    self.bit(true)
1167  }
1168  #[doc = r"Clears the field bit"]
1169  #[inline(always)]
1170  pub fn clear_bit(self) -> &'a mut W {
1171    self.bit(false)
1172  }
1173  #[doc = r"Writes raw bits to the field"]
1174  #[inline(always)]
1175  pub fn bit(self, value: bool) -> &'a mut W {
1176    self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
1177    self.w
1178  }
1179}
1180#[doc = "Receiver Enable\n\nValue on reset: 0"]
1181#[derive(Clone, Copy, Debug, PartialEq)]
1182pub enum RE_A {
1183  #[doc = "0: Receiver disabled."]
1184  RE_0,
1185  #[doc = "1: Receiver enabled."]
1186  RE_1,
1187}
1188impl From<RE_A> for bool {
1189  #[inline(always)]
1190  fn from(variant: RE_A) -> Self {
1191    match variant {
1192      RE_A::RE_0 => false,
1193      RE_A::RE_1 => true,
1194    }
1195  }
1196}
1197#[doc = "Reader of field `RE`"]
1198pub type RE_R = crate::R<bool, RE_A>;
1199impl RE_R {
1200  #[doc = r"Get enumerated values variant"]
1201  #[inline(always)]
1202  pub fn variant(&self) -> RE_A {
1203    match self.bits {
1204      false => RE_A::RE_0,
1205      true => RE_A::RE_1,
1206    }
1207  }
1208  #[doc = "Checks if the value of the field is `RE_0`"]
1209  #[inline(always)]
1210  pub fn is_re_0(&self) -> bool {
1211    *self == RE_A::RE_0
1212  }
1213  #[doc = "Checks if the value of the field is `RE_1`"]
1214  #[inline(always)]
1215  pub fn is_re_1(&self) -> bool {
1216    *self == RE_A::RE_1
1217  }
1218}
1219#[doc = "Write proxy for field `RE`"]
1220pub struct RE_W<'a> {
1221  w: &'a mut W,
1222}
1223impl<'a> RE_W<'a> {
1224  #[doc = r"Writes `variant` to the field"]
1225  #[inline(always)]
1226  pub fn variant(self, variant: RE_A) -> &'a mut W {
1227    {
1228      self.bit(variant.into())
1229    }
1230  }
1231  #[doc = "Receiver disabled."]
1232  #[inline(always)]
1233  pub fn re_0(self) -> &'a mut W {
1234    self.variant(RE_A::RE_0)
1235  }
1236  #[doc = "Receiver enabled."]
1237  #[inline(always)]
1238  pub fn re_1(self) -> &'a mut W {
1239    self.variant(RE_A::RE_1)
1240  }
1241  #[doc = r"Sets the field bit"]
1242  #[inline(always)]
1243  pub fn set_bit(self) -> &'a mut W {
1244    self.bit(true)
1245  }
1246  #[doc = r"Clears the field bit"]
1247  #[inline(always)]
1248  pub fn clear_bit(self) -> &'a mut W {
1249    self.bit(false)
1250  }
1251  #[doc = r"Writes raw bits to the field"]
1252  #[inline(always)]
1253  pub fn bit(self, value: bool) -> &'a mut W {
1254    self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
1255    self.w
1256  }
1257}
1258#[doc = "Transmitter Enable\n\nValue on reset: 0"]
1259#[derive(Clone, Copy, Debug, PartialEq)]
1260pub enum TE_A {
1261  #[doc = "0: Transmitter disabled."]
1262  TE_0,
1263  #[doc = "1: Transmitter enabled."]
1264  TE_1,
1265}
1266impl From<TE_A> for bool {
1267  #[inline(always)]
1268  fn from(variant: TE_A) -> Self {
1269    match variant {
1270      TE_A::TE_0 => false,
1271      TE_A::TE_1 => true,
1272    }
1273  }
1274}
1275#[doc = "Reader of field `TE`"]
1276pub type TE_R = crate::R<bool, TE_A>;
1277impl TE_R {
1278  #[doc = r"Get enumerated values variant"]
1279  #[inline(always)]
1280  pub fn variant(&self) -> TE_A {
1281    match self.bits {
1282      false => TE_A::TE_0,
1283      true => TE_A::TE_1,
1284    }
1285  }
1286  #[doc = "Checks if the value of the field is `TE_0`"]
1287  #[inline(always)]
1288  pub fn is_te_0(&self) -> bool {
1289    *self == TE_A::TE_0
1290  }
1291  #[doc = "Checks if the value of the field is `TE_1`"]
1292  #[inline(always)]
1293  pub fn is_te_1(&self) -> bool {
1294    *self == TE_A::TE_1
1295  }
1296}
1297#[doc = "Write proxy for field `TE`"]
1298pub struct TE_W<'a> {
1299  w: &'a mut W,
1300}
1301impl<'a> TE_W<'a> {
1302  #[doc = r"Writes `variant` to the field"]
1303  #[inline(always)]
1304  pub fn variant(self, variant: TE_A) -> &'a mut W {
1305    {
1306      self.bit(variant.into())
1307    }
1308  }
1309  #[doc = "Transmitter disabled."]
1310  #[inline(always)]
1311  pub fn te_0(self) -> &'a mut W {
1312    self.variant(TE_A::TE_0)
1313  }
1314  #[doc = "Transmitter enabled."]
1315  #[inline(always)]
1316  pub fn te_1(self) -> &'a mut W {
1317    self.variant(TE_A::TE_1)
1318  }
1319  #[doc = r"Sets the field bit"]
1320  #[inline(always)]
1321  pub fn set_bit(self) -> &'a mut W {
1322    self.bit(true)
1323  }
1324  #[doc = r"Clears the field bit"]
1325  #[inline(always)]
1326  pub fn clear_bit(self) -> &'a mut W {
1327    self.bit(false)
1328  }
1329  #[doc = r"Writes raw bits to the field"]
1330  #[inline(always)]
1331  pub fn bit(self, value: bool) -> &'a mut W {
1332    self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
1333    self.w
1334  }
1335}
1336#[doc = "Idle Line Interrupt Enable\n\nValue on reset: 0"]
1337#[derive(Clone, Copy, Debug, PartialEq)]
1338pub enum ILIE_A {
1339  #[doc = "0: Hardware interrupts from IDLE disabled; use polling."]
1340  ILIE_0,
1341  #[doc = "1: Hardware interrupt requested when IDLE flag is 1."]
1342  ILIE_1,
1343}
1344impl From<ILIE_A> for bool {
1345  #[inline(always)]
1346  fn from(variant: ILIE_A) -> Self {
1347    match variant {
1348      ILIE_A::ILIE_0 => false,
1349      ILIE_A::ILIE_1 => true,
1350    }
1351  }
1352}
1353#[doc = "Reader of field `ILIE`"]
1354pub type ILIE_R = crate::R<bool, ILIE_A>;
1355impl ILIE_R {
1356  #[doc = r"Get enumerated values variant"]
1357  #[inline(always)]
1358  pub fn variant(&self) -> ILIE_A {
1359    match self.bits {
1360      false => ILIE_A::ILIE_0,
1361      true => ILIE_A::ILIE_1,
1362    }
1363  }
1364  #[doc = "Checks if the value of the field is `ILIE_0`"]
1365  #[inline(always)]
1366  pub fn is_ilie_0(&self) -> bool {
1367    *self == ILIE_A::ILIE_0
1368  }
1369  #[doc = "Checks if the value of the field is `ILIE_1`"]
1370  #[inline(always)]
1371  pub fn is_ilie_1(&self) -> bool {
1372    *self == ILIE_A::ILIE_1
1373  }
1374}
1375#[doc = "Write proxy for field `ILIE`"]
1376pub struct ILIE_W<'a> {
1377  w: &'a mut W,
1378}
1379impl<'a> ILIE_W<'a> {
1380  #[doc = r"Writes `variant` to the field"]
1381  #[inline(always)]
1382  pub fn variant(self, variant: ILIE_A) -> &'a mut W {
1383    {
1384      self.bit(variant.into())
1385    }
1386  }
1387  #[doc = "Hardware interrupts from IDLE disabled; use polling."]
1388  #[inline(always)]
1389  pub fn ilie_0(self) -> &'a mut W {
1390    self.variant(ILIE_A::ILIE_0)
1391  }
1392  #[doc = "Hardware interrupt requested when IDLE flag is 1."]
1393  #[inline(always)]
1394  pub fn ilie_1(self) -> &'a mut W {
1395    self.variant(ILIE_A::ILIE_1)
1396  }
1397  #[doc = r"Sets the field bit"]
1398  #[inline(always)]
1399  pub fn set_bit(self) -> &'a mut W {
1400    self.bit(true)
1401  }
1402  #[doc = r"Clears the field bit"]
1403  #[inline(always)]
1404  pub fn clear_bit(self) -> &'a mut W {
1405    self.bit(false)
1406  }
1407  #[doc = r"Writes raw bits to the field"]
1408  #[inline(always)]
1409  pub fn bit(self, value: bool) -> &'a mut W {
1410    self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
1411    self.w
1412  }
1413}
1414#[doc = "Receiver Interrupt Enable\n\nValue on reset: 0"]
1415#[derive(Clone, Copy, Debug, PartialEq)]
1416pub enum RIE_A {
1417  #[doc = "0: Hardware interrupts from RDRF disabled; use polling."]
1418  RIE_0,
1419  #[doc = "1: Hardware interrupt requested when RDRF flag is 1."]
1420  RIE_1,
1421}
1422impl From<RIE_A> for bool {
1423  #[inline(always)]
1424  fn from(variant: RIE_A) -> Self {
1425    match variant {
1426      RIE_A::RIE_0 => false,
1427      RIE_A::RIE_1 => true,
1428    }
1429  }
1430}
1431#[doc = "Reader of field `RIE`"]
1432pub type RIE_R = crate::R<bool, RIE_A>;
1433impl RIE_R {
1434  #[doc = r"Get enumerated values variant"]
1435  #[inline(always)]
1436  pub fn variant(&self) -> RIE_A {
1437    match self.bits {
1438      false => RIE_A::RIE_0,
1439      true => RIE_A::RIE_1,
1440    }
1441  }
1442  #[doc = "Checks if the value of the field is `RIE_0`"]
1443  #[inline(always)]
1444  pub fn is_rie_0(&self) -> bool {
1445    *self == RIE_A::RIE_0
1446  }
1447  #[doc = "Checks if the value of the field is `RIE_1`"]
1448  #[inline(always)]
1449  pub fn is_rie_1(&self) -> bool {
1450    *self == RIE_A::RIE_1
1451  }
1452}
1453#[doc = "Write proxy for field `RIE`"]
1454pub struct RIE_W<'a> {
1455  w: &'a mut W,
1456}
1457impl<'a> RIE_W<'a> {
1458  #[doc = r"Writes `variant` to the field"]
1459  #[inline(always)]
1460  pub fn variant(self, variant: RIE_A) -> &'a mut W {
1461    {
1462      self.bit(variant.into())
1463    }
1464  }
1465  #[doc = "Hardware interrupts from RDRF disabled; use polling."]
1466  #[inline(always)]
1467  pub fn rie_0(self) -> &'a mut W {
1468    self.variant(RIE_A::RIE_0)
1469  }
1470  #[doc = "Hardware interrupt requested when RDRF flag is 1."]
1471  #[inline(always)]
1472  pub fn rie_1(self) -> &'a mut W {
1473    self.variant(RIE_A::RIE_1)
1474  }
1475  #[doc = r"Sets the field bit"]
1476  #[inline(always)]
1477  pub fn set_bit(self) -> &'a mut W {
1478    self.bit(true)
1479  }
1480  #[doc = r"Clears the field bit"]
1481  #[inline(always)]
1482  pub fn clear_bit(self) -> &'a mut W {
1483    self.bit(false)
1484  }
1485  #[doc = r"Writes raw bits to the field"]
1486  #[inline(always)]
1487  pub fn bit(self, value: bool) -> &'a mut W {
1488    self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
1489    self.w
1490  }
1491}
1492#[doc = "Transmission Complete Interrupt Enable for\n\nValue on reset: 0"]
1493#[derive(Clone, Copy, Debug, PartialEq)]
1494pub enum TCIE_A {
1495  #[doc = "0: Hardware interrupts from TC disabled; use polling."]
1496  TCIE_0,
1497  #[doc = "1: Hardware interrupt requested when TC flag is 1."]
1498  TCIE_1,
1499}
1500impl From<TCIE_A> for bool {
1501  #[inline(always)]
1502  fn from(variant: TCIE_A) -> Self {
1503    match variant {
1504      TCIE_A::TCIE_0 => false,
1505      TCIE_A::TCIE_1 => true,
1506    }
1507  }
1508}
1509#[doc = "Reader of field `TCIE`"]
1510pub type TCIE_R = crate::R<bool, TCIE_A>;
1511impl TCIE_R {
1512  #[doc = r"Get enumerated values variant"]
1513  #[inline(always)]
1514  pub fn variant(&self) -> TCIE_A {
1515    match self.bits {
1516      false => TCIE_A::TCIE_0,
1517      true => TCIE_A::TCIE_1,
1518    }
1519  }
1520  #[doc = "Checks if the value of the field is `TCIE_0`"]
1521  #[inline(always)]
1522  pub fn is_tcie_0(&self) -> bool {
1523    *self == TCIE_A::TCIE_0
1524  }
1525  #[doc = "Checks if the value of the field is `TCIE_1`"]
1526  #[inline(always)]
1527  pub fn is_tcie_1(&self) -> bool {
1528    *self == TCIE_A::TCIE_1
1529  }
1530}
1531#[doc = "Write proxy for field `TCIE`"]
1532pub struct TCIE_W<'a> {
1533  w: &'a mut W,
1534}
1535impl<'a> TCIE_W<'a> {
1536  #[doc = r"Writes `variant` to the field"]
1537  #[inline(always)]
1538  pub fn variant(self, variant: TCIE_A) -> &'a mut W {
1539    {
1540      self.bit(variant.into())
1541    }
1542  }
1543  #[doc = "Hardware interrupts from TC disabled; use polling."]
1544  #[inline(always)]
1545  pub fn tcie_0(self) -> &'a mut W {
1546    self.variant(TCIE_A::TCIE_0)
1547  }
1548  #[doc = "Hardware interrupt requested when TC flag is 1."]
1549  #[inline(always)]
1550  pub fn tcie_1(self) -> &'a mut W {
1551    self.variant(TCIE_A::TCIE_1)
1552  }
1553  #[doc = r"Sets the field bit"]
1554  #[inline(always)]
1555  pub fn set_bit(self) -> &'a mut W {
1556    self.bit(true)
1557  }
1558  #[doc = r"Clears the field bit"]
1559  #[inline(always)]
1560  pub fn clear_bit(self) -> &'a mut W {
1561    self.bit(false)
1562  }
1563  #[doc = r"Writes raw bits to the field"]
1564  #[inline(always)]
1565  pub fn bit(self, value: bool) -> &'a mut W {
1566    self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
1567    self.w
1568  }
1569}
1570#[doc = "Transmit Interrupt Enable\n\nValue on reset: 0"]
1571#[derive(Clone, Copy, Debug, PartialEq)]
1572pub enum TIE_A {
1573  #[doc = "0: Hardware interrupts from TDRE disabled; use polling."]
1574  TIE_0,
1575  #[doc = "1: Hardware interrupt requested when TDRE flag is 1."]
1576  TIE_1,
1577}
1578impl From<TIE_A> for bool {
1579  #[inline(always)]
1580  fn from(variant: TIE_A) -> Self {
1581    match variant {
1582      TIE_A::TIE_0 => false,
1583      TIE_A::TIE_1 => true,
1584    }
1585  }
1586}
1587#[doc = "Reader of field `TIE`"]
1588pub type TIE_R = crate::R<bool, TIE_A>;
1589impl TIE_R {
1590  #[doc = r"Get enumerated values variant"]
1591  #[inline(always)]
1592  pub fn variant(&self) -> TIE_A {
1593    match self.bits {
1594      false => TIE_A::TIE_0,
1595      true => TIE_A::TIE_1,
1596    }
1597  }
1598  #[doc = "Checks if the value of the field is `TIE_0`"]
1599  #[inline(always)]
1600  pub fn is_tie_0(&self) -> bool {
1601    *self == TIE_A::TIE_0
1602  }
1603  #[doc = "Checks if the value of the field is `TIE_1`"]
1604  #[inline(always)]
1605  pub fn is_tie_1(&self) -> bool {
1606    *self == TIE_A::TIE_1
1607  }
1608}
1609#[doc = "Write proxy for field `TIE`"]
1610pub struct TIE_W<'a> {
1611  w: &'a mut W,
1612}
1613impl<'a> TIE_W<'a> {
1614  #[doc = r"Writes `variant` to the field"]
1615  #[inline(always)]
1616  pub fn variant(self, variant: TIE_A) -> &'a mut W {
1617    {
1618      self.bit(variant.into())
1619    }
1620  }
1621  #[doc = "Hardware interrupts from TDRE disabled; use polling."]
1622  #[inline(always)]
1623  pub fn tie_0(self) -> &'a mut W {
1624    self.variant(TIE_A::TIE_0)
1625  }
1626  #[doc = "Hardware interrupt requested when TDRE flag is 1."]
1627  #[inline(always)]
1628  pub fn tie_1(self) -> &'a mut W {
1629    self.variant(TIE_A::TIE_1)
1630  }
1631  #[doc = r"Sets the field bit"]
1632  #[inline(always)]
1633  pub fn set_bit(self) -> &'a mut W {
1634    self.bit(true)
1635  }
1636  #[doc = r"Clears the field bit"]
1637  #[inline(always)]
1638  pub fn clear_bit(self) -> &'a mut W {
1639    self.bit(false)
1640  }
1641  #[doc = r"Writes raw bits to the field"]
1642  #[inline(always)]
1643  pub fn bit(self, value: bool) -> &'a mut W {
1644    self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
1645    self.w
1646  }
1647}
1648#[doc = "Parity Error Interrupt Enable\n\nValue on reset: 0"]
1649#[derive(Clone, Copy, Debug, PartialEq)]
1650pub enum PEIE_A {
1651  #[doc = "0: PF interrupts disabled; use polling)."]
1652  PEIE_0,
1653  #[doc = "1: Hardware interrupt requested when PF is set."]
1654  PEIE_1,
1655}
1656impl From<PEIE_A> for bool {
1657  #[inline(always)]
1658  fn from(variant: PEIE_A) -> Self {
1659    match variant {
1660      PEIE_A::PEIE_0 => false,
1661      PEIE_A::PEIE_1 => true,
1662    }
1663  }
1664}
1665#[doc = "Reader of field `PEIE`"]
1666pub type PEIE_R = crate::R<bool, PEIE_A>;
1667impl PEIE_R {
1668  #[doc = r"Get enumerated values variant"]
1669  #[inline(always)]
1670  pub fn variant(&self) -> PEIE_A {
1671    match self.bits {
1672      false => PEIE_A::PEIE_0,
1673      true => PEIE_A::PEIE_1,
1674    }
1675  }
1676  #[doc = "Checks if the value of the field is `PEIE_0`"]
1677  #[inline(always)]
1678  pub fn is_peie_0(&self) -> bool {
1679    *self == PEIE_A::PEIE_0
1680  }
1681  #[doc = "Checks if the value of the field is `PEIE_1`"]
1682  #[inline(always)]
1683  pub fn is_peie_1(&self) -> bool {
1684    *self == PEIE_A::PEIE_1
1685  }
1686}
1687#[doc = "Write proxy for field `PEIE`"]
1688pub struct PEIE_W<'a> {
1689  w: &'a mut W,
1690}
1691impl<'a> PEIE_W<'a> {
1692  #[doc = r"Writes `variant` to the field"]
1693  #[inline(always)]
1694  pub fn variant(self, variant: PEIE_A) -> &'a mut W {
1695    {
1696      self.bit(variant.into())
1697    }
1698  }
1699  #[doc = "PF interrupts disabled; use polling)."]
1700  #[inline(always)]
1701  pub fn peie_0(self) -> &'a mut W {
1702    self.variant(PEIE_A::PEIE_0)
1703  }
1704  #[doc = "Hardware interrupt requested when PF is set."]
1705  #[inline(always)]
1706  pub fn peie_1(self) -> &'a mut W {
1707    self.variant(PEIE_A::PEIE_1)
1708  }
1709  #[doc = r"Sets the field bit"]
1710  #[inline(always)]
1711  pub fn set_bit(self) -> &'a mut W {
1712    self.bit(true)
1713  }
1714  #[doc = r"Clears the field bit"]
1715  #[inline(always)]
1716  pub fn clear_bit(self) -> &'a mut W {
1717    self.bit(false)
1718  }
1719  #[doc = r"Writes raw bits to the field"]
1720  #[inline(always)]
1721  pub fn bit(self, value: bool) -> &'a mut W {
1722    self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
1723    self.w
1724  }
1725}
1726#[doc = "Framing Error Interrupt Enable\n\nValue on reset: 0"]
1727#[derive(Clone, Copy, Debug, PartialEq)]
1728pub enum FEIE_A {
1729  #[doc = "0: FE interrupts disabled; use polling."]
1730  FEIE_0,
1731  #[doc = "1: Hardware interrupt requested when FE is set."]
1732  FEIE_1,
1733}
1734impl From<FEIE_A> for bool {
1735  #[inline(always)]
1736  fn from(variant: FEIE_A) -> Self {
1737    match variant {
1738      FEIE_A::FEIE_0 => false,
1739      FEIE_A::FEIE_1 => true,
1740    }
1741  }
1742}
1743#[doc = "Reader of field `FEIE`"]
1744pub type FEIE_R = crate::R<bool, FEIE_A>;
1745impl FEIE_R {
1746  #[doc = r"Get enumerated values variant"]
1747  #[inline(always)]
1748  pub fn variant(&self) -> FEIE_A {
1749    match self.bits {
1750      false => FEIE_A::FEIE_0,
1751      true => FEIE_A::FEIE_1,
1752    }
1753  }
1754  #[doc = "Checks if the value of the field is `FEIE_0`"]
1755  #[inline(always)]
1756  pub fn is_feie_0(&self) -> bool {
1757    *self == FEIE_A::FEIE_0
1758  }
1759  #[doc = "Checks if the value of the field is `FEIE_1`"]
1760  #[inline(always)]
1761  pub fn is_feie_1(&self) -> bool {
1762    *self == FEIE_A::FEIE_1
1763  }
1764}
1765#[doc = "Write proxy for field `FEIE`"]
1766pub struct FEIE_W<'a> {
1767  w: &'a mut W,
1768}
1769impl<'a> FEIE_W<'a> {
1770  #[doc = r"Writes `variant` to the field"]
1771  #[inline(always)]
1772  pub fn variant(self, variant: FEIE_A) -> &'a mut W {
1773    {
1774      self.bit(variant.into())
1775    }
1776  }
1777  #[doc = "FE interrupts disabled; use polling."]
1778  #[inline(always)]
1779  pub fn feie_0(self) -> &'a mut W {
1780    self.variant(FEIE_A::FEIE_0)
1781  }
1782  #[doc = "Hardware interrupt requested when FE is set."]
1783  #[inline(always)]
1784  pub fn feie_1(self) -> &'a mut W {
1785    self.variant(FEIE_A::FEIE_1)
1786  }
1787  #[doc = r"Sets the field bit"]
1788  #[inline(always)]
1789  pub fn set_bit(self) -> &'a mut W {
1790    self.bit(true)
1791  }
1792  #[doc = r"Clears the field bit"]
1793  #[inline(always)]
1794  pub fn clear_bit(self) -> &'a mut W {
1795    self.bit(false)
1796  }
1797  #[doc = r"Writes raw bits to the field"]
1798  #[inline(always)]
1799  pub fn bit(self, value: bool) -> &'a mut W {
1800    self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
1801    self.w
1802  }
1803}
1804#[doc = "Noise Error Interrupt Enable\n\nValue on reset: 0"]
1805#[derive(Clone, Copy, Debug, PartialEq)]
1806pub enum NEIE_A {
1807  #[doc = "0: NF interrupts disabled; use polling."]
1808  NEIE_0,
1809  #[doc = "1: Hardware interrupt requested when NF is set."]
1810  NEIE_1,
1811}
1812impl From<NEIE_A> for bool {
1813  #[inline(always)]
1814  fn from(variant: NEIE_A) -> Self {
1815    match variant {
1816      NEIE_A::NEIE_0 => false,
1817      NEIE_A::NEIE_1 => true,
1818    }
1819  }
1820}
1821#[doc = "Reader of field `NEIE`"]
1822pub type NEIE_R = crate::R<bool, NEIE_A>;
1823impl NEIE_R {
1824  #[doc = r"Get enumerated values variant"]
1825  #[inline(always)]
1826  pub fn variant(&self) -> NEIE_A {
1827    match self.bits {
1828      false => NEIE_A::NEIE_0,
1829      true => NEIE_A::NEIE_1,
1830    }
1831  }
1832  #[doc = "Checks if the value of the field is `NEIE_0`"]
1833  #[inline(always)]
1834  pub fn is_neie_0(&self) -> bool {
1835    *self == NEIE_A::NEIE_0
1836  }
1837  #[doc = "Checks if the value of the field is `NEIE_1`"]
1838  #[inline(always)]
1839  pub fn is_neie_1(&self) -> bool {
1840    *self == NEIE_A::NEIE_1
1841  }
1842}
1843#[doc = "Write proxy for field `NEIE`"]
1844pub struct NEIE_W<'a> {
1845  w: &'a mut W,
1846}
1847impl<'a> NEIE_W<'a> {
1848  #[doc = r"Writes `variant` to the field"]
1849  #[inline(always)]
1850  pub fn variant(self, variant: NEIE_A) -> &'a mut W {
1851    {
1852      self.bit(variant.into())
1853    }
1854  }
1855  #[doc = "NF interrupts disabled; use polling."]
1856  #[inline(always)]
1857  pub fn neie_0(self) -> &'a mut W {
1858    self.variant(NEIE_A::NEIE_0)
1859  }
1860  #[doc = "Hardware interrupt requested when NF is set."]
1861  #[inline(always)]
1862  pub fn neie_1(self) -> &'a mut W {
1863    self.variant(NEIE_A::NEIE_1)
1864  }
1865  #[doc = r"Sets the field bit"]
1866  #[inline(always)]
1867  pub fn set_bit(self) -> &'a mut W {
1868    self.bit(true)
1869  }
1870  #[doc = r"Clears the field bit"]
1871  #[inline(always)]
1872  pub fn clear_bit(self) -> &'a mut W {
1873    self.bit(false)
1874  }
1875  #[doc = r"Writes raw bits to the field"]
1876  #[inline(always)]
1877  pub fn bit(self, value: bool) -> &'a mut W {
1878    self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
1879    self.w
1880  }
1881}
1882#[doc = "Overrun Interrupt Enable\n\nValue on reset: 0"]
1883#[derive(Clone, Copy, Debug, PartialEq)]
1884pub enum ORIE_A {
1885  #[doc = "0: OR interrupts disabled; use polling."]
1886  ORIE_0,
1887  #[doc = "1: Hardware interrupt requested when OR is set."]
1888  ORIE_1,
1889}
1890impl From<ORIE_A> for bool {
1891  #[inline(always)]
1892  fn from(variant: ORIE_A) -> Self {
1893    match variant {
1894      ORIE_A::ORIE_0 => false,
1895      ORIE_A::ORIE_1 => true,
1896    }
1897  }
1898}
1899#[doc = "Reader of field `ORIE`"]
1900pub type ORIE_R = crate::R<bool, ORIE_A>;
1901impl ORIE_R {
1902  #[doc = r"Get enumerated values variant"]
1903  #[inline(always)]
1904  pub fn variant(&self) -> ORIE_A {
1905    match self.bits {
1906      false => ORIE_A::ORIE_0,
1907      true => ORIE_A::ORIE_1,
1908    }
1909  }
1910  #[doc = "Checks if the value of the field is `ORIE_0`"]
1911  #[inline(always)]
1912  pub fn is_orie_0(&self) -> bool {
1913    *self == ORIE_A::ORIE_0
1914  }
1915  #[doc = "Checks if the value of the field is `ORIE_1`"]
1916  #[inline(always)]
1917  pub fn is_orie_1(&self) -> bool {
1918    *self == ORIE_A::ORIE_1
1919  }
1920}
1921#[doc = "Write proxy for field `ORIE`"]
1922pub struct ORIE_W<'a> {
1923  w: &'a mut W,
1924}
1925impl<'a> ORIE_W<'a> {
1926  #[doc = r"Writes `variant` to the field"]
1927  #[inline(always)]
1928  pub fn variant(self, variant: ORIE_A) -> &'a mut W {
1929    {
1930      self.bit(variant.into())
1931    }
1932  }
1933  #[doc = "OR interrupts disabled; use polling."]
1934  #[inline(always)]
1935  pub fn orie_0(self) -> &'a mut W {
1936    self.variant(ORIE_A::ORIE_0)
1937  }
1938  #[doc = "Hardware interrupt requested when OR is set."]
1939  #[inline(always)]
1940  pub fn orie_1(self) -> &'a mut W {
1941    self.variant(ORIE_A::ORIE_1)
1942  }
1943  #[doc = r"Sets the field bit"]
1944  #[inline(always)]
1945  pub fn set_bit(self) -> &'a mut W {
1946    self.bit(true)
1947  }
1948  #[doc = r"Clears the field bit"]
1949  #[inline(always)]
1950  pub fn clear_bit(self) -> &'a mut W {
1951    self.bit(false)
1952  }
1953  #[doc = r"Writes raw bits to the field"]
1954  #[inline(always)]
1955  pub fn bit(self, value: bool) -> &'a mut W {
1956    self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
1957    self.w
1958  }
1959}
1960#[doc = "Transmit Data Inversion\n\nValue on reset: 0"]
1961#[derive(Clone, Copy, Debug, PartialEq)]
1962pub enum TXINV_A {
1963  #[doc = "0: Transmit data not inverted."]
1964  TXINV_0,
1965  #[doc = "1: Transmit data inverted."]
1966  TXINV_1,
1967}
1968impl From<TXINV_A> for bool {
1969  #[inline(always)]
1970  fn from(variant: TXINV_A) -> Self {
1971    match variant {
1972      TXINV_A::TXINV_0 => false,
1973      TXINV_A::TXINV_1 => true,
1974    }
1975  }
1976}
1977#[doc = "Reader of field `TXINV`"]
1978pub type TXINV_R = crate::R<bool, TXINV_A>;
1979impl TXINV_R {
1980  #[doc = r"Get enumerated values variant"]
1981  #[inline(always)]
1982  pub fn variant(&self) -> TXINV_A {
1983    match self.bits {
1984      false => TXINV_A::TXINV_0,
1985      true => TXINV_A::TXINV_1,
1986    }
1987  }
1988  #[doc = "Checks if the value of the field is `TXINV_0`"]
1989  #[inline(always)]
1990  pub fn is_txinv_0(&self) -> bool {
1991    *self == TXINV_A::TXINV_0
1992  }
1993  #[doc = "Checks if the value of the field is `TXINV_1`"]
1994  #[inline(always)]
1995  pub fn is_txinv_1(&self) -> bool {
1996    *self == TXINV_A::TXINV_1
1997  }
1998}
1999#[doc = "Write proxy for field `TXINV`"]
2000pub struct TXINV_W<'a> {
2001  w: &'a mut W,
2002}
2003impl<'a> TXINV_W<'a> {
2004  #[doc = r"Writes `variant` to the field"]
2005  #[inline(always)]
2006  pub fn variant(self, variant: TXINV_A) -> &'a mut W {
2007    {
2008      self.bit(variant.into())
2009    }
2010  }
2011  #[doc = "Transmit data not inverted."]
2012  #[inline(always)]
2013  pub fn txinv_0(self) -> &'a mut W {
2014    self.variant(TXINV_A::TXINV_0)
2015  }
2016  #[doc = "Transmit data inverted."]
2017  #[inline(always)]
2018  pub fn txinv_1(self) -> &'a mut W {
2019    self.variant(TXINV_A::TXINV_1)
2020  }
2021  #[doc = r"Sets the field bit"]
2022  #[inline(always)]
2023  pub fn set_bit(self) -> &'a mut W {
2024    self.bit(true)
2025  }
2026  #[doc = r"Clears the field bit"]
2027  #[inline(always)]
2028  pub fn clear_bit(self) -> &'a mut W {
2029    self.bit(false)
2030  }
2031  #[doc = r"Writes raw bits to the field"]
2032  #[inline(always)]
2033  pub fn bit(self, value: bool) -> &'a mut W {
2034    self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
2035    self.w
2036  }
2037}
2038#[doc = "TXD Pin Direction in Single-Wire Mode\n\nValue on reset: 0"]
2039#[derive(Clone, Copy, Debug, PartialEq)]
2040pub enum TXDIR_A {
2041  #[doc = "0: TXD pin is an input in single-wire mode."]
2042  TXDIR_0,
2043  #[doc = "1: TXD pin is an output in single-wire mode."]
2044  TXDIR_1,
2045}
2046impl From<TXDIR_A> for bool {
2047  #[inline(always)]
2048  fn from(variant: TXDIR_A) -> Self {
2049    match variant {
2050      TXDIR_A::TXDIR_0 => false,
2051      TXDIR_A::TXDIR_1 => true,
2052    }
2053  }
2054}
2055#[doc = "Reader of field `TXDIR`"]
2056pub type TXDIR_R = crate::R<bool, TXDIR_A>;
2057impl TXDIR_R {
2058  #[doc = r"Get enumerated values variant"]
2059  #[inline(always)]
2060  pub fn variant(&self) -> TXDIR_A {
2061    match self.bits {
2062      false => TXDIR_A::TXDIR_0,
2063      true => TXDIR_A::TXDIR_1,
2064    }
2065  }
2066  #[doc = "Checks if the value of the field is `TXDIR_0`"]
2067  #[inline(always)]
2068  pub fn is_txdir_0(&self) -> bool {
2069    *self == TXDIR_A::TXDIR_0
2070  }
2071  #[doc = "Checks if the value of the field is `TXDIR_1`"]
2072  #[inline(always)]
2073  pub fn is_txdir_1(&self) -> bool {
2074    *self == TXDIR_A::TXDIR_1
2075  }
2076}
2077#[doc = "Write proxy for field `TXDIR`"]
2078pub struct TXDIR_W<'a> {
2079  w: &'a mut W,
2080}
2081impl<'a> TXDIR_W<'a> {
2082  #[doc = r"Writes `variant` to the field"]
2083  #[inline(always)]
2084  pub fn variant(self, variant: TXDIR_A) -> &'a mut W {
2085    {
2086      self.bit(variant.into())
2087    }
2088  }
2089  #[doc = "TXD pin is an input in single-wire mode."]
2090  #[inline(always)]
2091  pub fn txdir_0(self) -> &'a mut W {
2092    self.variant(TXDIR_A::TXDIR_0)
2093  }
2094  #[doc = "TXD pin is an output in single-wire mode."]
2095  #[inline(always)]
2096  pub fn txdir_1(self) -> &'a mut W {
2097    self.variant(TXDIR_A::TXDIR_1)
2098  }
2099  #[doc = r"Sets the field bit"]
2100  #[inline(always)]
2101  pub fn set_bit(self) -> &'a mut W {
2102    self.bit(true)
2103  }
2104  #[doc = r"Clears the field bit"]
2105  #[inline(always)]
2106  pub fn clear_bit(self) -> &'a mut W {
2107    self.bit(false)
2108  }
2109  #[doc = r"Writes raw bits to the field"]
2110  #[inline(always)]
2111  pub fn bit(self, value: bool) -> &'a mut W {
2112    self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
2113    self.w
2114  }
2115}
2116#[doc = "Reader of field `R9T8`"]
2117pub type R9T8_R = crate::R<bool, bool>;
2118#[doc = "Write proxy for field `R9T8`"]
2119pub struct R9T8_W<'a> {
2120  w: &'a mut W,
2121}
2122impl<'a> R9T8_W<'a> {
2123  #[doc = r"Sets the field bit"]
2124  #[inline(always)]
2125  pub fn set_bit(self) -> &'a mut W {
2126    self.bit(true)
2127  }
2128  #[doc = r"Clears the field bit"]
2129  #[inline(always)]
2130  pub fn clear_bit(self) -> &'a mut W {
2131    self.bit(false)
2132  }
2133  #[doc = r"Writes raw bits to the field"]
2134  #[inline(always)]
2135  pub fn bit(self, value: bool) -> &'a mut W {
2136    self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
2137    self.w
2138  }
2139}
2140#[doc = "Reader of field `R8T9`"]
2141pub type R8T9_R = crate::R<bool, bool>;
2142#[doc = "Write proxy for field `R8T9`"]
2143pub struct R8T9_W<'a> {
2144  w: &'a mut W,
2145}
2146impl<'a> R8T9_W<'a> {
2147  #[doc = r"Sets the field bit"]
2148  #[inline(always)]
2149  pub fn set_bit(self) -> &'a mut W {
2150    self.bit(true)
2151  }
2152  #[doc = r"Clears the field bit"]
2153  #[inline(always)]
2154  pub fn clear_bit(self) -> &'a mut W {
2155    self.bit(false)
2156  }
2157  #[doc = r"Writes raw bits to the field"]
2158  #[inline(always)]
2159  pub fn bit(self, value: bool) -> &'a mut W {
2160    self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
2161    self.w
2162  }
2163}
2164impl R {
2165  #[doc = "Bit 0 - Parity Type"]
2166  #[inline(always)]
2167  pub fn pt(&self) -> PT_R {
2168    PT_R::new((self.bits & 0x01) != 0)
2169  }
2170  #[doc = "Bit 1 - Parity Enable"]
2171  #[inline(always)]
2172  pub fn pe(&self) -> PE_R {
2173    PE_R::new(((self.bits >> 1) & 0x01) != 0)
2174  }
2175  #[doc = "Bit 2 - Idle Line Type Select"]
2176  #[inline(always)]
2177  pub fn ilt(&self) -> ILT_R {
2178    ILT_R::new(((self.bits >> 2) & 0x01) != 0)
2179  }
2180  #[doc = "Bit 3 - Receiver Wakeup Method Select"]
2181  #[inline(always)]
2182  pub fn wake(&self) -> WAKE_R {
2183    WAKE_R::new(((self.bits >> 3) & 0x01) != 0)
2184  }
2185  #[doc = "Bit 4 - 9-Bit or 8-Bit Mode Select"]
2186  #[inline(always)]
2187  pub fn m(&self) -> M_R {
2188    M_R::new(((self.bits >> 4) & 0x01) != 0)
2189  }
2190  #[doc = "Bit 5 - Receiver Source Select"]
2191  #[inline(always)]
2192  pub fn rsrc(&self) -> RSRC_R {
2193    RSRC_R::new(((self.bits >> 5) & 0x01) != 0)
2194  }
2195  #[doc = "Bit 6 - Doze Enable"]
2196  #[inline(always)]
2197  pub fn dozeen(&self) -> DOZEEN_R {
2198    DOZEEN_R::new(((self.bits >> 6) & 0x01) != 0)
2199  }
2200  #[doc = "Bit 7 - Loop Mode Select"]
2201  #[inline(always)]
2202  pub fn loops(&self) -> LOOPS_R {
2203    LOOPS_R::new(((self.bits >> 7) & 0x01) != 0)
2204  }
2205  #[doc = "Bits 8:10 - Idle Configuration"]
2206  #[inline(always)]
2207  pub fn idlecfg(&self) -> IDLECFG_R {
2208    IDLECFG_R::new(((self.bits >> 8) & 0x07) as u8)
2209  }
2210  #[doc = "Bit 11 - 7-Bit Mode Select"]
2211  #[inline(always)]
2212  pub fn m7(&self) -> M7_R {
2213    M7_R::new(((self.bits >> 11) & 0x01) != 0)
2214  }
2215  #[doc = "Bit 14 - Match 2 Interrupt Enable"]
2216  #[inline(always)]
2217  pub fn ma2ie(&self) -> MA2IE_R {
2218    MA2IE_R::new(((self.bits >> 14) & 0x01) != 0)
2219  }
2220  #[doc = "Bit 15 - Match 1 Interrupt Enable"]
2221  #[inline(always)]
2222  pub fn ma1ie(&self) -> MA1IE_R {
2223    MA1IE_R::new(((self.bits >> 15) & 0x01) != 0)
2224  }
2225  #[doc = "Bit 16 - Send Break"]
2226  #[inline(always)]
2227  pub fn sbk(&self) -> SBK_R {
2228    SBK_R::new(((self.bits >> 16) & 0x01) != 0)
2229  }
2230  #[doc = "Bit 17 - Receiver Wakeup Control"]
2231  #[inline(always)]
2232  pub fn rwu(&self) -> RWU_R {
2233    RWU_R::new(((self.bits >> 17) & 0x01) != 0)
2234  }
2235  #[doc = "Bit 18 - Receiver Enable"]
2236  #[inline(always)]
2237  pub fn re(&self) -> RE_R {
2238    RE_R::new(((self.bits >> 18) & 0x01) != 0)
2239  }
2240  #[doc = "Bit 19 - Transmitter Enable"]
2241  #[inline(always)]
2242  pub fn te(&self) -> TE_R {
2243    TE_R::new(((self.bits >> 19) & 0x01) != 0)
2244  }
2245  #[doc = "Bit 20 - Idle Line Interrupt Enable"]
2246  #[inline(always)]
2247  pub fn ilie(&self) -> ILIE_R {
2248    ILIE_R::new(((self.bits >> 20) & 0x01) != 0)
2249  }
2250  #[doc = "Bit 21 - Receiver Interrupt Enable"]
2251  #[inline(always)]
2252  pub fn rie(&self) -> RIE_R {
2253    RIE_R::new(((self.bits >> 21) & 0x01) != 0)
2254  }
2255  #[doc = "Bit 22 - Transmission Complete Interrupt Enable for"]
2256  #[inline(always)]
2257  pub fn tcie(&self) -> TCIE_R {
2258    TCIE_R::new(((self.bits >> 22) & 0x01) != 0)
2259  }
2260  #[doc = "Bit 23 - Transmit Interrupt Enable"]
2261  #[inline(always)]
2262  pub fn tie(&self) -> TIE_R {
2263    TIE_R::new(((self.bits >> 23) & 0x01) != 0)
2264  }
2265  #[doc = "Bit 24 - Parity Error Interrupt Enable"]
2266  #[inline(always)]
2267  pub fn peie(&self) -> PEIE_R {
2268    PEIE_R::new(((self.bits >> 24) & 0x01) != 0)
2269  }
2270  #[doc = "Bit 25 - Framing Error Interrupt Enable"]
2271  #[inline(always)]
2272  pub fn feie(&self) -> FEIE_R {
2273    FEIE_R::new(((self.bits >> 25) & 0x01) != 0)
2274  }
2275  #[doc = "Bit 26 - Noise Error Interrupt Enable"]
2276  #[inline(always)]
2277  pub fn neie(&self) -> NEIE_R {
2278    NEIE_R::new(((self.bits >> 26) & 0x01) != 0)
2279  }
2280  #[doc = "Bit 27 - Overrun Interrupt Enable"]
2281  #[inline(always)]
2282  pub fn orie(&self) -> ORIE_R {
2283    ORIE_R::new(((self.bits >> 27) & 0x01) != 0)
2284  }
2285  #[doc = "Bit 28 - Transmit Data Inversion"]
2286  #[inline(always)]
2287  pub fn txinv(&self) -> TXINV_R {
2288    TXINV_R::new(((self.bits >> 28) & 0x01) != 0)
2289  }
2290  #[doc = "Bit 29 - TXD Pin Direction in Single-Wire Mode"]
2291  #[inline(always)]
2292  pub fn txdir(&self) -> TXDIR_R {
2293    TXDIR_R::new(((self.bits >> 29) & 0x01) != 0)
2294  }
2295  #[doc = "Bit 30 - Receive Bit 9 / Transmit Bit 8"]
2296  #[inline(always)]
2297  pub fn r9t8(&self) -> R9T8_R {
2298    R9T8_R::new(((self.bits >> 30) & 0x01) != 0)
2299  }
2300  #[doc = "Bit 31 - Receive Bit 8 / Transmit Bit 9"]
2301  #[inline(always)]
2302  pub fn r8t9(&self) -> R8T9_R {
2303    R8T9_R::new(((self.bits >> 31) & 0x01) != 0)
2304  }
2305}
2306impl W {
2307  #[doc = "Bit 0 - Parity Type"]
2308  #[inline(always)]
2309  pub fn pt(&mut self) -> PT_W {
2310    PT_W { w: self }
2311  }
2312  #[doc = "Bit 1 - Parity Enable"]
2313  #[inline(always)]
2314  pub fn pe(&mut self) -> PE_W {
2315    PE_W { w: self }
2316  }
2317  #[doc = "Bit 2 - Idle Line Type Select"]
2318  #[inline(always)]
2319  pub fn ilt(&mut self) -> ILT_W {
2320    ILT_W { w: self }
2321  }
2322  #[doc = "Bit 3 - Receiver Wakeup Method Select"]
2323  #[inline(always)]
2324  pub fn wake(&mut self) -> WAKE_W {
2325    WAKE_W { w: self }
2326  }
2327  #[doc = "Bit 4 - 9-Bit or 8-Bit Mode Select"]
2328  #[inline(always)]
2329  pub fn m(&mut self) -> M_W {
2330    M_W { w: self }
2331  }
2332  #[doc = "Bit 5 - Receiver Source Select"]
2333  #[inline(always)]
2334  pub fn rsrc(&mut self) -> RSRC_W {
2335    RSRC_W { w: self }
2336  }
2337  #[doc = "Bit 6 - Doze Enable"]
2338  #[inline(always)]
2339  pub fn dozeen(&mut self) -> DOZEEN_W {
2340    DOZEEN_W { w: self }
2341  }
2342  #[doc = "Bit 7 - Loop Mode Select"]
2343  #[inline(always)]
2344  pub fn loops(&mut self) -> LOOPS_W {
2345    LOOPS_W { w: self }
2346  }
2347  #[doc = "Bits 8:10 - Idle Configuration"]
2348  #[inline(always)]
2349  pub fn idlecfg(&mut self) -> IDLECFG_W {
2350    IDLECFG_W { w: self }
2351  }
2352  #[doc = "Bit 11 - 7-Bit Mode Select"]
2353  #[inline(always)]
2354  pub fn m7(&mut self) -> M7_W {
2355    M7_W { w: self }
2356  }
2357  #[doc = "Bit 14 - Match 2 Interrupt Enable"]
2358  #[inline(always)]
2359  pub fn ma2ie(&mut self) -> MA2IE_W {
2360    MA2IE_W { w: self }
2361  }
2362  #[doc = "Bit 15 - Match 1 Interrupt Enable"]
2363  #[inline(always)]
2364  pub fn ma1ie(&mut self) -> MA1IE_W {
2365    MA1IE_W { w: self }
2366  }
2367  #[doc = "Bit 16 - Send Break"]
2368  #[inline(always)]
2369  pub fn sbk(&mut self) -> SBK_W {
2370    SBK_W { w: self }
2371  }
2372  #[doc = "Bit 17 - Receiver Wakeup Control"]
2373  #[inline(always)]
2374  pub fn rwu(&mut self) -> RWU_W {
2375    RWU_W { w: self }
2376  }
2377  #[doc = "Bit 18 - Receiver Enable"]
2378  #[inline(always)]
2379  pub fn re(&mut self) -> RE_W {
2380    RE_W { w: self }
2381  }
2382  #[doc = "Bit 19 - Transmitter Enable"]
2383  #[inline(always)]
2384  pub fn te(&mut self) -> TE_W {
2385    TE_W { w: self }
2386  }
2387  #[doc = "Bit 20 - Idle Line Interrupt Enable"]
2388  #[inline(always)]
2389  pub fn ilie(&mut self) -> ILIE_W {
2390    ILIE_W { w: self }
2391  }
2392  #[doc = "Bit 21 - Receiver Interrupt Enable"]
2393  #[inline(always)]
2394  pub fn rie(&mut self) -> RIE_W {
2395    RIE_W { w: self }
2396  }
2397  #[doc = "Bit 22 - Transmission Complete Interrupt Enable for"]
2398  #[inline(always)]
2399  pub fn tcie(&mut self) -> TCIE_W {
2400    TCIE_W { w: self }
2401  }
2402  #[doc = "Bit 23 - Transmit Interrupt Enable"]
2403  #[inline(always)]
2404  pub fn tie(&mut self) -> TIE_W {
2405    TIE_W { w: self }
2406  }
2407  #[doc = "Bit 24 - Parity Error Interrupt Enable"]
2408  #[inline(always)]
2409  pub fn peie(&mut self) -> PEIE_W {
2410    PEIE_W { w: self }
2411  }
2412  #[doc = "Bit 25 - Framing Error Interrupt Enable"]
2413  #[inline(always)]
2414  pub fn feie(&mut self) -> FEIE_W {
2415    FEIE_W { w: self }
2416  }
2417  #[doc = "Bit 26 - Noise Error Interrupt Enable"]
2418  #[inline(always)]
2419  pub fn neie(&mut self) -> NEIE_W {
2420    NEIE_W { w: self }
2421  }
2422  #[doc = "Bit 27 - Overrun Interrupt Enable"]
2423  #[inline(always)]
2424  pub fn orie(&mut self) -> ORIE_W {
2425    ORIE_W { w: self }
2426  }
2427  #[doc = "Bit 28 - Transmit Data Inversion"]
2428  #[inline(always)]
2429  pub fn txinv(&mut self) -> TXINV_W {
2430    TXINV_W { w: self }
2431  }
2432  #[doc = "Bit 29 - TXD Pin Direction in Single-Wire Mode"]
2433  #[inline(always)]
2434  pub fn txdir(&mut self) -> TXDIR_W {
2435    TXDIR_W { w: self }
2436  }
2437  #[doc = "Bit 30 - Receive Bit 9 / Transmit Bit 8"]
2438  #[inline(always)]
2439  pub fn r9t8(&mut self) -> R9T8_W {
2440    R9T8_W { w: self }
2441  }
2442  #[doc = "Bit 31 - Receive Bit 8 / Transmit Bit 9"]
2443  #[inline(always)]
2444  pub fn r8t9(&mut self) -> R8T9_W {
2445    R8T9_W { w: self }
2446  }
2447}
rv32m1_ri5cy_pac/lpuart0/ctrl.rs

rv32m1_ri5cy_pac/lpuart0/
ctrl.rs
