rv32m1_ri5cy_pac/sim/
chipctrl.rs

1#[doc = "Reader of register CHIPCTRL"]
2pub type R = crate::R<u32, super::CHIPCTRL>;
3#[doc = "Writer for register CHIPCTRL"]
4pub type W = crate::W<u32, super::CHIPCTRL>;
5#[doc = "Register CHIPCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CHIPCTRL {
7  type Type = u32;
8  #[inline(always)]
9  fn reset_value() -> Self::Type {
10    0
11  }
12}
13#[doc = "FLEXBUS security level\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15pub enum FBSL_A {
16  #[doc = "0: All off-chip access(instruction and data) via the Flexbus or sdram are disallowed"]
17  FBSL_0,
18  #[doc = "1: All off-chip access(instruction and data) via the Flexbus or sdram are disallowed"]
19  FBSL_1,
20  #[doc = "2: off-chip instruction access are disallowed, data access are allowed"]
21  FBSL_2,
22  #[doc = "3: off-chip instruction access and data access are allowed"]
23  FBSL_3,
24}
25impl From<FBSL_A> for u8 {
26  #[inline(always)]
27  fn from(variant: FBSL_A) -> Self {
28    match variant {
29      FBSL_A::FBSL_0 => 0,
30      FBSL_A::FBSL_1 => 1,
31      FBSL_A::FBSL_2 => 2,
32      FBSL_A::FBSL_3 => 3,
33    }
34  }
35}
36#[doc = "Reader of field `FBSL`"]
37pub type FBSL_R = crate::R<u8, FBSL_A>;
38impl FBSL_R {
39  #[doc = r"Get enumerated values variant"]
40  #[inline(always)]
41  pub fn variant(&self) -> FBSL_A {
42    match self.bits {
43      0 => FBSL_A::FBSL_0,
44      1 => FBSL_A::FBSL_1,
45      2 => FBSL_A::FBSL_2,
46      3 => FBSL_A::FBSL_3,
47      _ => unreachable!(),
48    }
49  }
50  #[doc = "Checks if the value of the field is `FBSL_0`"]
51  #[inline(always)]
52  pub fn is_fbsl_0(&self) -> bool {
53    *self == FBSL_A::FBSL_0
54  }
55  #[doc = "Checks if the value of the field is `FBSL_1`"]
56  #[inline(always)]
57  pub fn is_fbsl_1(&self) -> bool {
58    *self == FBSL_A::FBSL_1
59  }
60  #[doc = "Checks if the value of the field is `FBSL_2`"]
61  #[inline(always)]
62  pub fn is_fbsl_2(&self) -> bool {
63    *self == FBSL_A::FBSL_2
64  }
65  #[doc = "Checks if the value of the field is `FBSL_3`"]
66  #[inline(always)]
67  pub fn is_fbsl_3(&self) -> bool {
68    *self == FBSL_A::FBSL_3
69  }
70}
71#[doc = "Write proxy for field `FBSL`"]
72pub struct FBSL_W<'a> {
73  w: &'a mut W,
74}
75impl<'a> FBSL_W<'a> {
76  #[doc = r"Writes `variant` to the field"]
77  #[inline(always)]
78  pub fn variant(self, variant: FBSL_A) -> &'a mut W {
79    {
80      self.bits(variant.into())
81    }
82  }
83  #[doc = "All off-chip access(instruction and data) via the Flexbus or sdram are disallowed"]
84  #[inline(always)]
85  pub fn fbsl_0(self) -> &'a mut W {
86    self.variant(FBSL_A::FBSL_0)
87  }
88  #[doc = "All off-chip access(instruction and data) via the Flexbus or sdram are disallowed"]
89  #[inline(always)]
90  pub fn fbsl_1(self) -> &'a mut W {
91    self.variant(FBSL_A::FBSL_1)
92  }
93  #[doc = "off-chip instruction access are disallowed, data access are allowed"]
94  #[inline(always)]
95  pub fn fbsl_2(self) -> &'a mut W {
96    self.variant(FBSL_A::FBSL_2)
97  }
98  #[doc = "off-chip instruction access and data access are allowed"]
99  #[inline(always)]
100  pub fn fbsl_3(self) -> &'a mut W {
101    self.variant(FBSL_A::FBSL_3)
102  }
103  #[doc = r"Writes raw bits to the field"]
104  #[inline(always)]
105  pub fn bits(self, value: u8) -> &'a mut W {
106    self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
107    self.w
108  }
109}
110impl R {
111  #[doc = "Bits 8:9 - FLEXBUS security level"]
112  #[inline(always)]
113  pub fn fbsl(&self) -> FBSL_R {
114    FBSL_R::new(((self.bits >> 8) & 0x03) as u8)
115  }
116}
117impl W {
118  #[doc = "Bits 8:9 - FLEXBUS security level"]
119  #[inline(always)]
120  pub fn fbsl(&mut self) -> FBSL_W {
121    FBSL_W { w: self }
122  }
123}