rv32m1_ri5cy_pac/i2s0/
tcr3.rs

1#[doc = "Reader of register TCR3"]
2pub type R = crate::R<u32, super::TCR3>;
3#[doc = "Writer for register TCR3"]
4pub type W = crate::W<u32, super::TCR3>;
5#[doc = "Register TCR3 `reset()`'s with value 0"]
6impl crate::ResetValue for super::TCR3 {
7  type Type = u32;
8  #[inline(always)]
9  fn reset_value() -> Self::Type {
10    0
11  }
12}
13#[doc = "Reader of field `WDFL`"]
14pub type WDFL_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `WDFL`"]
16pub struct WDFL_W<'a> {
17  w: &'a mut W,
18}
19impl<'a> WDFL_W<'a> {
20  #[doc = r"Writes raw bits to the field"]
21  #[inline(always)]
22  pub unsafe fn bits(self, value: u8) -> &'a mut W {
23    self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
24    self.w
25  }
26}
27#[doc = "Reader of field `TCE`"]
28pub type TCE_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `TCE`"]
30pub struct TCE_W<'a> {
31  w: &'a mut W,
32}
33impl<'a> TCE_W<'a> {
34  #[doc = r"Writes raw bits to the field"]
35  #[inline(always)]
36  pub unsafe fn bits(self, value: u8) -> &'a mut W {
37    self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
38    self.w
39  }
40}
41#[doc = "Write proxy for field `CFR`"]
42pub struct CFR_W<'a> {
43  w: &'a mut W,
44}
45impl<'a> CFR_W<'a> {
46  #[doc = r"Writes raw bits to the field"]
47  #[inline(always)]
48  pub unsafe fn bits(self, value: u8) -> &'a mut W {
49    self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
50    self.w
51  }
52}
53impl R {
54  #[doc = "Bits 0:4 - Word Flag Configuration"]
55  #[inline(always)]
56  pub fn wdfl(&self) -> WDFL_R {
57    WDFL_R::new((self.bits & 0x1f) as u8)
58  }
59  #[doc = "Bits 16:17 - Transmit Channel Enable"]
60  #[inline(always)]
61  pub fn tce(&self) -> TCE_R {
62    TCE_R::new(((self.bits >> 16) & 0x03) as u8)
63  }
64}
65impl W {
66  #[doc = "Bits 0:4 - Word Flag Configuration"]
67  #[inline(always)]
68  pub fn wdfl(&mut self) -> WDFL_W {
69    WDFL_W { w: self }
70  }
71  #[doc = "Bits 16:17 - Transmit Channel Enable"]
72  #[inline(always)]
73  pub fn tce(&mut self) -> TCE_W {
74    TCE_W { w: self }
75  }
76  #[doc = "Bits 24:25 - Channel FIFO Reset"]
77  #[inline(always)]
78  pub fn cfr(&mut self) -> CFR_W {
79    CFR_W { w: self }
80  }
81}
rv32m1_ri5cy_pac/i2s0/tcr3.rs

rv32m1_ri5cy_pac/i2s0/
tcr3.rs
