rv32m1_ri5cy-pac 0.1.1

Peripheral access API for the RI5CY core of RV32M1 chips
Documentation 
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#[doc = "Reader of register SHIFTBUFHWS[%s]"]
pub type R = crate::R<u32, super::SHIFTBUFHWS>;
#[doc = "Writer for register SHIFTBUFHWS[%s]"]
pub type W = crate::W<u32, super::SHIFTBUFHWS>;
#[doc = "Register SHIFTBUFHWS[%s] `reset()`'s with value 0"]
impl crate::ResetValue for super::SHIFTBUFHWS {
  type Type = u32;
  #[inline(always)]
  fn reset_value() -> Self::Type {
    0
  }
}
#[doc = "Reader of field `SHIFTBUFHWS`"]
pub type SHIFTBUFHWS_R = crate::R<u32, u32>;
#[doc = "Write proxy for field `SHIFTBUFHWS`"]
pub struct SHIFTBUFHWS_W<'a> {
  w: &'a mut W,
}
impl<'a> SHIFTBUFHWS_W<'a> {
  #[doc = r"Writes raw bits to the field"]
  #[inline(always)]
  pub unsafe fn bits(self, value: u32) -> &'a mut W {
    self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
    self.w
  }
}
impl R {
  #[doc = "Bits 0:31 - Shift Buffer"]
  #[inline(always)]
  pub fn shiftbufhws(&self) -> SHIFTBUFHWS_R {
    SHIFTBUFHWS_R::new((self.bits & 0xffff_ffff) as u32)
  }
}
impl W {
  #[doc = "Bits 0:31 - Shift Buffer"]
  #[inline(always)]
  pub fn shiftbufhws(&mut self) -> SHIFTBUFHWS_W {
    SHIFTBUFHWS_W { w: self }
  }
}