ruvllm-esp32 0.3.2

Tiny LLM inference for ESP32 microcontrollers with INT8/INT4 quantization, multi-chip federation, RuVector semantic memory, and SNN-gated energy optimization
Documentation

ruvllm-esp32

There is very little structured metadata to build this page from currently. You should check the main library docs, readme, or Cargo.toml in case the author documented the features in them.

This version has 13 feature flags, 3 of them enabled by default.

default

federation (default)

This feature flag does not enable additional features.

host-test (default)

anyhow (default)

binary

This feature flag does not enable additional features.

esp-idf-hal

esp-idf-svc

esp-idf-sys

esp32-std

esp32s3-simd

This feature flag does not enable additional features.

no_std

This feature flag does not enable additional features.

q4

This feature flag does not enable additional features.

q8

This feature flag does not enable additional features.

self-learning

This feature flag does not enable additional features.