ruvix_aarch64/lib.rs
1//! AArch64 architecture support for RuVix Cognition Kernel
2//!
3//! This crate provides low-level AArch64 support including:
4//! - Boot sequence and early initialization
5//! - Memory Management Unit (MMU) configuration
6//! - Exception handling (sync, IRQ, FIQ, SError)
7//! - System register access
8//!
9//! # Memory Layout
10//!
11//! ```text
12//! 0x0000_0000_0000_0000 - 0x0000_FFFF_FFFF_FFFF: User space (TTBR0_EL1)
13//! 0xFFFF_0000_0000_0000 - 0xFFFF_FFFF_FFFF_FFFF: Kernel space (TTBR1_EL1)
14//! ```
15//!
16//! # Boot Sequence
17//!
18//! 1. Assembly entry point (`_start`) disables interrupts
19//! 2. Stack pointer initialized
20//! 3. BSS section cleared
21//! 4. `early_init()` called to set up MMU
22//! 5. Exception vectors configured
23//! 6. Jump to `kernel_main()`
24
25#![no_std]
26#![deny(unsafe_op_in_unsafe_fn)]
27
28pub mod boot;
29pub mod exception;
30pub mod mmu;
31pub mod registers;
32
33// Re-export key types
34pub use boot::{early_init, kernel_main};
35pub use mmu::Mmu;
36pub use registers::*;
37
38/// AArch64 page size (4KB)
39pub const PAGE_SIZE: usize = 0x1000;
40
41/// AArch64 page shift (log2 of page size)
42pub const PAGE_SHIFT: usize = 12;
43
44/// Kernel virtual base address (upper half)
45pub const KERNEL_VIRT_BASE: usize = 0xFFFF_0000_0000_0000;
46
47/// Physical RAM base (platform-specific, QEMU virt = 0x4000_0000)
48#[cfg(feature = "qemu-virt")]
49pub const PHYS_RAM_BASE: usize = 0x4000_0000;
50
51#[cfg(not(feature = "qemu-virt"))]
52pub const PHYS_RAM_BASE: usize = 0x0000_0000;
53
54/// Exception vector alignment requirement (2KB = 0x800)
55pub const VECTOR_ALIGNMENT: usize = 0x800;
56
57/// Convert virtual address to physical (simple offset for identity mapping)
58#[inline]
59pub const fn virt_to_phys(vaddr: usize) -> usize {
60 vaddr.wrapping_sub(KERNEL_VIRT_BASE)
61}
62
63/// Convert physical address to virtual (simple offset for identity mapping)
64#[inline]
65pub const fn phys_to_virt(paddr: usize) -> usize {
66 paddr.wrapping_add(KERNEL_VIRT_BASE)
67}