# Memory Hierarchy Design
* All memory controllers (cache and memory) implement same interface
* Cache takes care of deferring to next level, adds on its own latency
to the next level
* Simulator should keep track of how many cycles to stall
* Caches need to keep track of memory requests
* When enough cycles have passed, find a line to evict
* Caches/memory need to be clocked somehow
* Own clock or clocked to processor?
* Write-allocate? (probably easier to implement by default)
* Write-through? (probably easier to implement by default + avoids
need for snooping)