rustdv-methodology 0.3.0

//! # rustdv-methodology
//!
//! The verification methodology layer — rustdv's analog of the UVM's
//! component methodology (design-doc §5, as revised by review-memo R1–R6).
//!
//! **Read this first: R3, R4 and R5 are being reversed.** They are what
//! made rustdv a *closed-world* framework — one that cannot configure or
//! override anything you did not write yourself — and the branch this
//! crate is on exists to undo them. `output/.design-decisions.md` is
//! authoritative; the list below marks each item's real status so nobody
//! mistakes the current code for the intended design.
//!
//! - Transactions are plain structs with std derives (R1) — no base trait.
//!   **Stands.**
//! - The component tree is the ownership tree (R2): children are struct
//!   fields; [`ComponentNode`] provides traversal, hand-implementable or
//!   generated by `#[derive(Component)]`. **Stands** — the tree is still
//!   ownership; what returns is the phase structure over it.
//! - build/connect are constructor conventions (R3); the runtime lifecycle
//!   is the [`Component`] trait. **Reversed — `build`/`connect` are real
//!   phase methods again (D5/D6/D51), and the runner drives all nine phases
//!   over the tree (`run_component_test`).** The *first half* of ch24 (the
//!   phase-logging test) runs on this. Still pending: two-stage
//!   construction, where a parent creates children as `Option<T>`/`Vec<T>`
//!   in its own `build` — the second half of ch24.
//! - Configuration is typed config structs passed to constructors (R4).
//!   **Reversed by D11–D16, not yet implemented.** A path-addressed
//!   `ConfigDb` returns, with three-tier resolution and loud failure.
//! - Variation points are constructor injection (R5) — no factory.
//!   **Reversed, not yet implemented.** The factory returns in ch29
//!   (D26 keeps it out of ch23 only because the book does).
//! - Communication is channels + [`AnalysisBus`] + the sequencer
//!   handshake, preserved event-for-event from pyuvm (R6, §5.6).
//!   **Stands, and is being extended:** TLM ports, exports and FIFOs
//!   arrive per D17–D24, with ports in components and exports on FIFOs.
//!
//! What *has* landed on this branch is step 4: [`RustdvCtx`], the one
//! context (D47), and [`Component`]'s `async fn run` (D46, D48).

pub mod analysis;
pub mod channel;
#[cfg(test)]
use rustdv_vpi_stubs as _;

pub mod component;
pub mod config;
pub mod error;
pub mod factory;
pub mod fifo;
pub mod objection;
pub mod port;
pub mod sequence;
pub mod shared;

pub use analysis::{AnalysisBus, PublishExport, SubscribeExport};
pub use channel::{Receiver, Sender, TlmEmpty, TlmError, TlmFull, channel};
pub use component::{
    Active, CheckSink, Component, ComponentNode, DynPhases, RustdvCtx, build_all, check_all,
    check_connections, connect_all, end_of_elaboration_all, extract_all, final_all,
    print_hierarchy, report_all, run_all, run_component_test, run_extract_check_report, start_all,
    start_of_simulation_all, unconnected_ports,
};
pub use config::{ConfigDb, ConfigError};
pub use error::TestError;
pub use factory::{COMPONENT_REGISTRATIONS, ComponentReg, Factory, Maker, RustdvComp};
pub use fifo::{GetExport, PeekExport, PutExport, TapExport, TlmFifo};
pub use objection::{ObjectionGuard, ObjectionRegistry};
pub use port::{
    ConnectError, GetIf, GetPort, PeekIf, PeekPort, Port, PortField, PortInfo, PortName, PortOwner,
    PublishIf, PublishPort, PutIf, PutPort, SinkHandle, SubscribePort, Subscriber, bind,
};
pub use sequence::{
    DynSequence, ResponseQueue, RustdvSeq, SeqCtx, SeqError, SeqItem, SeqItemExport, SeqItemIf,
    SeqItemPort, Sequence, Sequencer, TxnId, clear_seq_overrides, create_seq, set_seq_override,
    set_sequence_seed,
};
pub use shared::RustdvShared;