rustdv-methodology 0.1.0

The verification methodology layer: component lifecycle and phases, ConfigDb, factory, objections, channels, analysis broadcast, TLM FIFOs, and the sequencer handshake (design-doc §5).
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  • Source code size: 197.77 kB This is the summed size of all the files inside the crates.io package for this release.
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  • this release: 6s Average build duration of successful builds.
  • all releases: 4s Average build duration of successful builds in releases after 2024-10-23.
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  • raysalemi

rustdv-methodology

The verification methodology layer — rustdv's analog of the UVM's component methodology (design-doc §5, as revised by review-memo R1–R6).

Read this first: R3, R4 and R5 are being reversed. They are what made rustdv a closed-world framework — one that cannot configure or override anything you did not write yourself — and the branch this crate is on exists to undo them. output/.design-decisions.md is authoritative; the list below marks each item's real status so nobody mistakes the current code for the intended design.

  • Transactions are plain structs with std derives (R1) — no base trait. Stands.
  • The component tree is the ownership tree (R2): children are struct fields; [ComponentNode] provides traversal, hand-implementable or generated by #[derive(Component)]. Stands — the tree is still ownership; what returns is the phase structure over it.
  • build/connect are constructor conventions (R3); the runtime lifecycle is the [Component] trait. Reversed — build/connect are real phase methods again (D5/D6/D51), and the runner drives all nine phases over the tree (run_component_test). The first half of ch24 (the phase-logging test) runs on this. Still pending: two-stage construction, where a parent creates children as Option<T>/Vec<T> in its own build — the second half of ch24.
  • Configuration is typed config structs passed to constructors (R4). Reversed by D11–D16, not yet implemented. A path-addressed ConfigDb returns, with three-tier resolution and loud failure.
  • Variation points are constructor injection (R5) — no factory. Reversed, not yet implemented. The factory returns in ch29 (D26 keeps it out of ch23 only because the book does).
  • Communication is channels + [AnalysisBus] + the sequencer handshake, preserved event-for-event from pyuvm (R6, §5.6). Stands, and is being extended: TLM ports, exports and FIFOs arrive per D17–D24, with ports in components and exports on FIFOs.

What has landed on this branch is step 4: [RustdvCtx], the one context (D47), and [Component]'s async fn run (D46, D48).