Struct rustduino::atmega328p::hal::port::Port

pub struct Port { /* fields omitted */ }

Contains registers to control the port.

• pin: Port input pins. Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

• ddr: Data direction register. The DDxn bit in the DDRx register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

• port: Data register. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running.

  If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

Section 13.2.1 and 13.2.2 of ATmega328P datasheet.

Implementations

impl Port

pub fn new(port_name: PortName) -> &'static mut Port

Returns mutable reference to the Port given PortName.

Section 13.4 of ATmega328P datasheet.

pub fn name(&self) -> PortName

Returns PortName of the port based on its address. Panics if Port has invalid address.

Section 13.4 of ATmega328P datasheet.

impl Port

pub fn pin(&mut self, pin: u8) -> Option<Pin>

Returns a Some<Pin> if pin number is valid.