Module ruspiro_register::system::aarch64::ttbr0_el2

This is supported on AArch64 only.

TTBR0_EL2 - Translation Table Base Register 0 EL2

Holds the base address of translation table 0, and information about the memory it occupies. This is one of the translation tables for the stage 1 translation of memory accesses from EL2 or HYP mode

Usage Constraints

EL0	EL1 (NS)	EL1(S)	EL2	EL3(NS)	EL3(S)
-	-	-	R/W	R/W	R/W

Modules

ASID	AArch64 An ASID for the translation table base address.
BADDR	AArch64 Translation table base address bits[47:x]. x is based on the value of TCR_EL2::T0SZ, the stage of translation and the memory translation granule size

Functions

get	AArch64 Read the raw register contents using the appropriate assembly
read	AArch64 Read the contents of a specific RegisterField. The returned value is already shifted to the right to start at bit 0. This means for a field value stored in the register at bit offset 3, the returned value is already shifted by 3 bits to the right. For example: If register raw value is 0b10110, the returned value for a register field specified as bits[4:3] would be 0b01. No further "masking" or "bit-shift" required
set	AArch64 Write the raw register contents using the appropriate contents
write	AArch64 Update the contents of a register from the RegisterFieldValue given. This will only change the bits the RegisterField definition specifies.