[−][src]Module ruspiro_register::system::aarch64::ccsidr_el1

This is supported on AArch64 only.

CCSIDR_EL1 - Cache Size ID Register

This is a read-only register

EL0	EL1 (NS)	EL1(S)	EL2	EL3(NS)	EL3(S)
-	R	R	R	R	R

ASSOC	AArch64 Indicates the associativity of the cache - 1. A value of 0 indicates an associativity of
LINESIZE	AArch64 Indicates the (log2(number of words in cache line)) - 2
NUMSETS	AArch64 Indeicates the number of sets in cache - 1. A value of 0 indeicates 1 set in the cache. It does not need to be a power of 2.
RA	AArch64 Indicates support for reas-allocation
WA	AArch64 Indicates support for write-allocation
WB	AArch64 Indicates support for write-back
WT	AArch64 Indicates support for write-through

get	AArch64 Read the raw register contents using the appropriate assembly
read	AArch64 Read the contents of a specific `RegisterField`. The returned value is already shifted to the right to start at bit 0. This means for a field value stored in the register at bit offset 3, the returned value is already shifted by 3 bits to the right. For example: If register raw value is 0b10110, the returned value for a register field specified as bits[4:3] would be 0b01. No further "masking" or "bit-shift" required
set	AArch64 Write the raw register contents using the appropriate contents
write	AArch64 Update the contents of a register from the `RegisterFieldValue` given. This will only change the bits the `RegisterField` definition specifies.