1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
use crate;
// Among all backends, the memory order guarantee of WebGPU is the weakest
// So Ruda's memory order cannot be stronger than that of WebGPU
/// # Coordinates the following among all invocations in the current ruda:
///
/// * Memory writes to variables in ruda address space(shared memory) complete,
/// e.g. writes that were initiated actually land in the ruda address space memory.
///
/// * Then all the invocations in the ruda wait for each other to arrive at the barrier, i.e. this step.
///
/// * Then all the invocations int the ruda begin executing after the barrier, and all writes to ruda address space made before the barrier are now visible to any invocation in this ruda.
/// Synchronizes units within their plane (e.g., warp or SIMD group).
///
/// Warning: not all targets support plane-level synchronization.
/// * `Sync_storage` is the same but change "ruda address space(shared memory)" to "storage address space(input args)". But the set of invocations that are collaborating is still only the invocations in the same ruda.
///
/// * There is no guarantee about using barriers alone to make the writes to storage buffer in one ruda become visible to invocations in a different ruda.
/// `sync_async_proxy_shared` is a synchronization fence for the experimental SM 9.0+ copy
/// functions, applying bidirectionally between the async proxy (i.e. TMA) and shared memory.
/// Should be used after initializing the barriers, and before the copy operation.
/// PTX: `fence.proxy.async.shared::cta`
/// Experimental and subject to change.