rucc-target 0.18.10

//! What each x86-64 machine instruction is in bytes.
//!
//! Design: `spec/11-asm-objects-debug.md` section 11.1.
//!
//! The other half of [`crate::x86_64::written`]. That says which instructions of the machine an
//! opcode is, what each of them is called and which operand each argument is drawn from, and this
//! says what the bytes of one of them are. Section 11.1 asks for one description behind both the
//! text and the object file, and this is how the two are one: a caller walks the same list of
//! [`Written`](crate::x86_64::Written) either way and only the last step differs, so an
//! instruction cannot be in the listing and missing from the object, or be written with one
//! operand and encoded with another.
//!
//! # How a row is found
//!
//! By the mnemonic and by what kind of thing each of its arguments is, which is what an assembler
//! does. `movl` is four different instructions depending on whether it is given an immediate, a
//! register, a load or a store, and they share a mnemonic because they do the same thing rather
//! than because they are the same instruction.
//!
//! The immediate is part of the question too. Two families here have a shorter form for a small
//! number: every arithmetic instruction can sign extend one byte instead of carrying four, and
//! the sixty four bit move is ten bytes with the whole number in it and seven with four sign
//! extended bytes. Writing those as their own rows, in front of the general one, is what keeps
//! the choice out of the encoder, where it would be a special case, and in the table, where it is
//! two more lines that a person can check against a manual.
//!
//! # What is not chosen here
//!
//! The short form of a jump. Every jump and call this writes carries a four byte distance,
//! because how far it goes is not known until every block has a place and this encodes one
//! instruction at a time. Picking the two byte form where it fits is relaxation, which
//! `spec/11-asm-objects-debug.md` section 11.1 describes as a pass over the whole function rather
//! than a decision an encoder makes, and it is not written yet. The bytes are correct without it
//! and longer than an assembler's would be.
//!
//! The other accumulator forms are not here either. `addl $1000, %eax` has a five byte encoding
//! that only `eax` can use and a six byte one that any register can, and only the second is
//! written, because the first is a size win of one byte on one register and a row that applies to
//! one register is the kind of row a reader stops checking. A shift by one is the same trade the
//! other way round: the machine has a form that means one and carries no count, and we write the
//! general form with a one in it, which is a byte longer and the same instruction.

use std::fmt;
use std::sync::LazyLock;

use crate::named;
use crate::regs::{PhysReg, Segment};
use crate::x86_64::text::{Arg, Width};

use Fits::{Signed8, Signed32};
use Size::{
    Byte, Double, DoubleQuad, Long, Quad, Single, SingleQuad, Untracked, Word, WordDouble, WordQuad,
};

/// What kind of thing one argument of an instruction is.
///
/// The coarse version of [`Arg`]: which operand a register is drawn from and how much of it is
/// read decide what is written, and neither decides which instruction it is. What decides that is
/// whether the argument is a register at all.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Kind {
    /// A register, whichever one and however much of it.
    Reg,
    /// A vector register, whichever one.
    ///
    /// Which file a register is in is part of which instruction it is, and this is the one place
    /// that could say so: an argument here is what picks a row, and `movq %rax, %rbx` and
    /// `movq %xmm0, %rax` are the same mnemonic with two register arguments. Nothing else about
    /// the two tells them apart, and a lookup that could not tell them apart would encode a
    /// conversion between the files as a copy inside one of them.
    Vec,
    /// An address.
    Mem,
    /// A number the instruction carries.
    Imm,
    /// Somewhere else in the program, which is what a jump and a call are given.
    Dest,
    /// One of the eight mask registers AVX-512 added, `k0` to `k7`.
    ///
    /// Its own kind because `kmovq` moves between one of these and a general purpose register,
    /// and a lookup that could not tell the two apart would have no way to pick the direction.
    Mask,
    /// A position on the x87 stack, which is a depth rather than a register.
    ///
    /// Its own kind for the reason [`Kind::Vec`] is: it is what picks a row, and a row it picked
    /// wrongly would be a different instruction. Nothing is written from it, since every row that
    /// takes one is a fixed opcode with the depth already in its second byte. What it is for is
    /// the same thing every kind here is for: the x87 mnemonics that take a stack position also
    /// have forms that take an address, and a lookup that could not tell the two apart would
    /// encode one as the other.
    Stack,
    /// A control register, which only a kernel names and only a move reads or writes.
    ///
    /// Its own kind because `movq %cr3, %rax` and `movq %rbx, %rax` are two register arguments
    /// to the same mnemonic and two different opcodes, the way a vector register and a general
    /// purpose one are.
    Control,
    /// A debug register, for the same reason.
    Debug,
    /// A segment register, which a move reads and writes and a push and a pop save and restore.
    Seg,
}

impl Kind {
    /// What kind of argument that is.
    #[must_use]
    pub fn of(arg: Arg) -> Self {
        match arg {
            Arg::Reg(_, _) | Arg::Low(_) | Arg::High(_) | Arg::Through => Kind::Reg,
            // A register named outright is `ah` but for the registers only AVX-512 has, which the
            // zeroing in front of a `ret` names since nothing is ever allocated to one of them.
            Arg::Named(name) if name.starts_with("zmm") || name.starts_with("xmm") => Kind::Vec,
            Arg::Named(name) if name.starts_with('k') => Kind::Mask,
            Arg::Named(_) => Kind::Reg,
            Arg::Xmm(_) => Kind::Vec,
            Arg::Stack(_) => Kind::Stack,
            Arg::Mem => Kind::Mem,
            Arg::Imm | Arg::Lit(_) => Kind::Imm,
            Arg::Symbol | Arg::Label => Kind::Dest,
        }
    }
}

/// What an instruction's prefixes say about the size of what it works on.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Size {
    /// Eight bits, which is no prefix. A REX byte may still be needed, because the four registers
    /// numbered four to seven are `ah`, `ch`, `dh` and `bh` as bytes without one and `spl`,
    /// `bpl`, `sil` and `dil` with one, but that is decided by the register rather than here.
    Byte,
    /// Sixteen bits, which is the `0x66` prefix.
    Word,
    /// Thirty two bits, which is this machine's default and is no prefix either. It is also what
    /// an instruction that is sixty four bits without being told is written as, which is a push,
    /// a pop, a jump, a call and leaving, since telling those would be a byte that says nothing.
    Long,
    /// Sixty four bits, which is `REX.W`.
    Quad,
    /// One `float`, which is the `0xF3` prefix.
    ///
    /// The manual calls this a mandatory prefix rather than a size, because `0xF3` in front of an
    /// SSE opcode is part of which instruction it is rather than a claim about how wide the
    /// operands are: `0F 58` is `addps` and `F3 0F 58` is `addss`. It is here anyway, because
    /// where the byte goes is what this field decides and it goes exactly where `0x66` goes, in
    /// front of the REX byte and behind nothing.
    Single,
    /// One `double`, which is the `0xF2` prefix and is the same kind of thing.
    Double,
    /// The `0x66` prefix with `REX.W` set, which is `movq` between the two register files.
    ///
    /// The three below are each one of the prefixes above and the bit that means sixty four bits,
    /// which is a combination the machine really has and nothing here could say before. They are
    /// where the conversions between an integer and a float at sixty four bits are: `cvtsi2sdq`
    /// is the `0xF2` prefix, because that is what makes the opcode the `double` one, and `REX.W`,
    /// because that is what makes the integer it reads sixty four bits wide, and the two answer
    /// different questions about the same instruction.
    WordQuad,
    /// The `0xF3` prefix with `REX.W` set, which is the `float` conversions at sixty four bits.
    SingleQuad,
    /// The `0xF2` prefix with `REX.W` set, which is the `double` ones.
    DoubleQuad,
    /// The `0x66` prefix and then the `0xF2` one, which is `crc32w`.
    ///
    /// The only size here that is two prefix bytes. `0xF2` is what makes `0F 38 F1` a checksum
    /// step rather than `movbe`, and `0x66` is what makes the operand it reads sixteen bits, so the
    /// two answer different questions the way the pairs above do, except that the second answer is
    /// a byte of its own rather than a bit in the REX byte. gas writes `0x66` first and the manual
    /// lists it that way, and the bytes have to match what gas writes.
    WordDouble,
    /// The `0x3E` prefix, which is `notrack` in front of an indirect jump or call.
    ///
    /// Not a size either. With indirect branch tracking on, a jump through a register has to land
    /// on an `endbr64`, and this byte says the place it lands is one that need not, which is what
    /// a switch lowered to a table of offsets wants. It goes where the other prefixes go, in front
    /// of the REX byte, since behind it the REX byte would no longer be the last thing before the
    /// opcode and `jmp *%r8` would read as a jump through `rax`.
    Untracked,
}

impl Size {
    /// The byte this size puts in front of the instruction, if it puts one there at all.
    ///
    /// `REX.W` is not here. It is a bit in a byte the registers also write into, so it is set
    /// where that byte is built rather than returned as a prefix of its own.
    const fn prefix(self) -> Option<u8> {
        match self {
            Word | WordQuad => Some(0x66),
            Single | SingleQuad => Some(0xF3),
            Double | DoubleQuad | WordDouble => Some(0xF2),
            Untracked => Some(0x3E),
            Byte | Long | Quad => None,
        }
    }

    /// Whether the REX byte's wide bit is set, which is the other half of what a size says.
    ///
    /// Separate from [`Size::prefix`] because the two go in different bytes and because they are
    /// not the same question. A prefix in front of an SSE opcode says which instruction it is and
    /// this says how wide the general purpose register in it is, which is why four of the sizes
    /// here answer both.
    pub(crate) const fn wide(self) -> bool {
        matches!(self, Quad | WordQuad | SingleQuad | DoubleQuad)
    }
}

/// Which of the two machines the bytes are for, the sixty four bit one or the i386 one.
///
/// One table serves both, because almost every instruction is the same bytes in either: an i386
/// instruction is an x86-64 one that names none of the registers the second half of the machine
/// added and none of its sixty four bit operand sizes. What differs is small and all of it is in
/// how an instruction is put together rather than in which instructions there are:
///
/// - There is no REX byte. `0x40` to `0x4F` are instructions of their own, `inc` and `dec` of a
///   thirty two bit register, so a register numbered eight or above, a sixty four bit operand and
///   a byte register that needs a REX byte to be named (`spl`, `bpl`, `sil`, `dil`) cannot be
///   written, and asking for one is an error rather than a byte the processor reads as `inc`.
/// - `mod=00 rm=101` is a four byte absolute address rather than one counted from the end of the
///   instruction, so an address with neither base nor index is that and needs no SIB byte, and an
///   address counted from the instruction cannot be written at all.
/// - `inc` and `dec` of a sixteen or thirty two bit register take the one byte form gas writes.
/// - A push and a pop move four bytes and are spelled `pushl` and `popl`.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default, Hash)]
pub enum Mode {
    /// Sixty four bit mode, which is what [`encode`] writes for.
    #[default]
    Bits64,
    /// Thirty two bit protected mode, which is what an i386 program runs in.
    Bits32,
}

impl Mode {
    /// The low four bits of `byte` when it is a REX byte in this mode, which it never is in thirty
    /// two bit mode.
    ///
    /// For something reading an instruction back from its bytes, which has to know whether the
    /// byte in front of an opcode is a prefix of it or an instruction of its own.
    #[must_use]
    pub const fn rex(self, byte: u8) -> Option<u8> {
        match self {
            Mode::Bits64 if byte & 0xF0 == 0x40 => Some(byte & 0x0F),
            _ => None,
        }
    }

    /// The instruction `byte` is on its own in this mode, when it is `0x40` to `0x4F` and this is
    /// thirty two bit mode: `incl` of the register in its low three bits for the first eight and
    /// `decl` for the second. In sixty four bit mode those bytes are REX prefixes and this is
    /// [`None`], as it is for every other byte.
    #[must_use]
    pub const fn counted(self, byte: u8) -> Option<(&'static str, PhysReg)> {
        match self {
            Mode::Bits32 if byte & 0xF0 == 0x40 => {
                let reg = PhysReg::new(byte & 7);
                Some((if byte & 8 == 0 { "incl" } else { "decl" }, reg))
            }
            _ => None,
        }
    }
}

/// Where the arguments of an instruction go in the byte that addresses them.
///
/// An index rather than the argument, for the reason [`Arg`] gives: the order an instruction is
/// written in is not the order its operands are in, and an argument the machine needs may be one
/// the assembler does not write.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Fields {
    /// No addressing byte at all, which is an instruction whose arguments are all in the opcode
    /// or are the distance to somewhere else.
    None,
    /// The argument at that index is addressed, and the three bits beside it in the byte are more
    /// of the opcode rather than a second register. Eight instructions share `0xF7` this way.
    Ext {
        /// The argument the byte addresses, which is a register or an address.
        rm: u8,
        /// The three bits that finish the opcode.
        ext: u8,
    },
    /// The argument at `rm` is addressed and the one at `reg` is the register beside it.
    Pair {
        /// The argument the byte addresses, which is a register or an address.
        rm: u8,
        /// The argument in the register field, which is always a register.
        reg: u8,
    },
    /// The low three bits of that argument's register are added to the last byte of the opcode,
    /// which is how a push, a pop and the ten byte move name theirs.
    Plus {
        /// The argument whose register is in the opcode.
        reg: u8,
    },
}

/// The immediate an instruction carries, behind everything else it is made of.
///
/// Named the way the manual names them, because this is a table a person checks against one.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum ImmSize {
    /// None at all.
    None,
    /// One byte.
    Ib,
    /// Two bytes.
    Iw,
    /// Four bytes.
    Id,
    /// Eight bytes, which only the ten byte move has.
    Io,
    /// Four bytes of signed distance from the end of the instruction, which is what a jump and a
    /// call carry and is filled in once the place it goes to is known.
    Cd,
    /// One byte of the same thing, which reaches a hundred and twenty seven bytes either way and
    /// is the only distance the one instruction that carries it has. Nothing this compiler emits
    /// uses it, because choosing the short form of a jump that also has a long one is a pass over
    /// a whole section rather than an encoding question, and a whole section is not what an
    /// encoder is given.
    Cb,
    /// One byte whose top four bits are the number of the register written first, which is how
    /// `vpblendvb` names its fourth operand.
    Is4,
}

/// Which immediates a row is for.
///
/// Two jobs. It is how one instruction has more than one encoding, since the arithmetic
/// instructions have a short form for a small number and the sixty four bit move has a long one
/// for a big one. And it is how a number too big for any form of an instruction is refused rather
/// than quietly cut down, which would be a compiler that writes a different program from the one
/// it was given.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Fits {
    /// Any at all, which is what a row with no immediate takes and what the one instruction with
    /// an eight byte immediate takes.
    Any,
    /// One that fits in a signed byte, which is the short form every arithmetic instruction here
    /// has and is why the general row is written behind it.
    Signed8,
    /// One that fits in four signed bytes, which is as far as an instruction that sign extends
    /// what it carries reaches. That is the seven byte form of the sixty four bit move, and it is
    /// also every sixty four bit arithmetic instruction with an immediate, because four bytes is
    /// the widest immediate the machine has outside that one move.
    Signed32,
    /// One that fits in a byte, counted either way, since a number over a hundred and twenty
    /// seven and the negative one it would be read as are the same eight bits. A negative number
    /// down to -255 is taken too, which is gas's rule and which it keeps quiet about: gcc prints
    /// `(u8)~0x80` passed as an `int` to an `"iq"` operand under `%b` as `andb $-129`, and the
    /// kernel's `clear_bit` is that, so it is the low eight bits that are meant.
    Byte,
    /// One that fits in two bytes, counted either way, with the same rule for a negative one.
    Word,
    /// One that fits in four bytes, counted either way, with the same rule for a negative one.
    Long,
}

/// Whether gas writes that number in that many bits without a word, which is `offset_in_range` in
/// its tc-i386.c: either the number or its negation has nothing above those bits. So a byte takes
/// everything from -255 to 255, and -256, which gas shortens to zero with a warning, is refused.
fn quietly(imm: i64, bits: u32) -> bool {
    let above = !((1i64 << bits) - 1);
    imm & above == 0 || imm.wrapping_neg() & above == 0
}

impl Fits {
    /// Whether this row is one that number may be written with.
    fn holds(self, imm: i64) -> bool {
        match self {
            Fits::Any => true,
            Signed8 => i8::try_from(imm).is_ok(),
            Signed32 => i32::try_from(imm).is_ok(),
            Fits::Byte => quietly(imm, 8),
            Fits::Word => quietly(imm, 16),
            Fits::Long => quietly(imm, 32),
        }
    }
}

/// Which of the escape sequences a VEX encoded instruction's opcode would have been written behind.
///
/// A legacy opcode says which of three tables it is in by how many bytes it puts in front of itself:
/// nothing, `0F`, `0F 38` or `0F 3A`. VEX carries the same answer as a number in its own bytes, so
/// the row's opcode is the last byte alone and this says which table to look it up in. That is not
/// a saving of two bytes dressed up as a field, it is why the two byte form of the prefix exists at
/// all: that form can only say `0F`, so a row in either of the other two tables is three bytes of
/// prefix whatever else is true of it.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Map {
    /// What `0F` in front of a legacy opcode means.
    Escape,
    /// What `0F 38` means, which is where the bit manipulation instructions are.
    Escape38,
    /// What `0F 3A` means, which is where the ones carrying an immediate that selects something
    /// are.
    Escape3A,
}

impl Map {
    /// The number the prefix carries for it, which is the five bit `mmmmm` field.
    const fn bits(self) -> u8 {
        match self {
            Map::Escape => 1,
            Map::Escape38 => 2,
            Map::Escape3A => 3,
        }
    }
}

/// What a row needs to say to be VEX encoded rather than written the legacy way.
///
/// VEX replaces the prefix bytes and the REX byte with two or three bytes of its own, carrying the
/// same register extension bits, the same wide bit, which of the mandatory prefixes applies and
/// which opcode table the opcode is in, and one thing no legacy encoding has anywhere to put: a
/// third register operand. So a row that has one of these writes none of the legacy prefixes and no
/// REX byte, and everything those said is said here instead.
///
/// The prefix and the wide bit are not in this struct, because [`Size`] already carries both and
/// says exactly the same thing: a row whose size is [`Size::Word`] is one the legacy encoding would
/// have put `0x66` in front of and VEX gives `pp` of one, and a row whose size is
/// [`Size::WordQuad`] is that with the wide bit as well. Repeating them here would be two places to
/// write the same fact and one of them eventually wrong.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct Vex {
    /// Which opcode table the row's opcode is in.
    pub map: Map,
    /// The argument that goes in the `vvvv` field, which is the third register operand.
    ///
    /// Always a register. The field is four bits and is written inverted, so the number that means
    /// no operand at all is fifteen, which is what a row with nothing to put here says by leaving
    /// this [`None`].
    pub vvvv: Option<u8>,
    /// Whether the instruction works on the wide half of a vector register, which is the `L` bit,
    /// whatever registers it names.
    ///
    /// Only `vzeroall` sets it. An instruction over general purpose registers has no wide half and
    /// the manual writes `LZ` for exactly that, and a vector row is set by the registers it names,
    /// a `ymm` anywhere making it the wide instruction.
    pub long: bool,
}

/// How much of a vector register an instruction works on, which is what its name says.
///
/// `xmm3`, `ymm3` and `zmm3` are one register named three ways: the low sixteen bytes, the low
/// thirty two and all sixty four. An EVEX encoded instruction has no opcode per length, the
/// length is two bits of the prefix, so the name an operand is written with is what those two
/// bits are read from.
#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
pub enum Length {
    /// Sixteen bytes, `xmm`.
    Xmm,
    /// Thirty two bytes, `ymm`.
    Ymm,
    /// Sixty four bytes, `zmm`.
    Zmm,
}

impl Length {
    /// The two bits an EVEX prefix says it with, `L'L`.
    const fn bits(self) -> u8 {
        match self {
            Length::Xmm => 0,
            Length::Ymm => 1,
            Length::Zmm => 2,
        }
    }

    /// How many bytes that is.
    #[must_use]
    pub const fn bytes(self) -> u8 {
        match self {
            Length::Xmm => 16,
            Length::Ymm => 32,
            Length::Zmm => 64,
        }
    }

    /// The letter a register of this length starts with.
    #[must_use]
    pub const fn letter(self) -> char {
        match self {
            Length::Xmm => 'x',
            Length::Ymm => 'y',
            Length::Zmm => 'z',
        }
    }
}

/// How much memory an EVEX encoded instruction reaches, which is what its one byte displacement
/// is counted in.
///
/// EVEX scales a one byte displacement by the size of the access, so `64(%rax)` under a load of
/// a whole `zmm` register is the byte `01` rather than `40`. A displacement that is not a whole
/// number of accesses, or is too many of them for a byte, takes the four byte form, which is not
/// scaled. The manual calls this the tuple type and has a dozen of them, and these two are the
/// ones the rows here need.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Tuple {
    /// The whole vector, as long as the instruction's registers say it is.
    Full,
    /// That many bytes whatever the length, which is a sixteen byte lane pulled out of a vector or
    /// broadcast across one.
    Fixed(u8),
}

/// What a row needs to say to be EVEX encoded, which is how AVX-512 is written.
///
/// EVEX is VEX grown to four bytes. The extra room holds a fifth bit for every register number,
/// which is what reaches `zmm16` to `zmm31`, two bits of length where VEX had one, and the mask
/// register and zeroing bit that `{%k1}{z}` writes. The mandatory prefix is the row's [`Size`], the
/// same as for a VEX row, and the wide bit is here instead, because an AVX-512 instruction over
/// vectors has no general purpose register for the size to describe.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct Evex {
    /// Which opcode table the row's opcode is in.
    pub map: Map,
    /// The wide bit, which here says whether the elements are four bytes or eight.
    pub w: bool,
    /// The argument that goes in the `vvvv` field, as for `Vex`.
    pub vvvv: Option<u8>,
    /// What a one byte displacement is counted in.
    pub tuple: Tuple,
    /// Whether the instruction also has a VEX form, and the wide bit that form is written with.
    ///
    /// gas writes the VEX form of an instruction that has one whenever nothing about the operands
    /// needs EVEX, which is a register numbered sixteen or above, a whole `zmm` or a mask. The
    /// bytes have to match, and the VEX form is also the one a processor without AVX-512 can run.
    pub vex: Option<bool>,
}

impl Evex {
    /// A row in that table with that wide bit, reaching a whole vector, with no third register and
    /// no VEX form.
    const fn new(map: Map, w: bool) -> Evex {
        Evex { map, w, vvvv: None, tuple: Tuple::Full, vex: None }
    }

    /// The same with the argument at that index in `vvvv`.
    const fn third(self, at: u8) -> Evex {
        Evex { vvvv: Some(at), ..self }
    }

    /// The same reaching that many bytes whatever the length.
    const fn fixed(self, bytes: u8) -> Evex {
        Evex { tuple: Tuple::Fixed(bytes), ..self }
    }

    /// The same with a VEX form written with that wide bit.
    const fn or_vex(self, w: bool) -> Evex {
        Evex { vex: Some(w), ..self }
    }
}

/// One instruction of the machine, as a processor reads it.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct Encoding {
    /// The mnemonic, which is the one [`Written`](crate::x86_64::Written) carries.
    pub mnemonic: &'static str,
    /// What each of its arguments is, in the order they are written.
    pub args: &'static [Kind],
    /// Which immediates this row is for.
    pub fits: Fits,
    /// What the prefixes say the operands are.
    pub size: Size,
    /// The bytes of the opcode itself, in front of everything the arguments decide.
    pub opcode: &'static [u8],
    /// Where the arguments go in the byte that addresses them.
    pub fields: Fields,
    /// The immediate behind the rest of it.
    pub imm: ImmSize,
    /// Whether the instruction is written with `fwait` in front of it.
    ///
    /// Only the x87 instructions that have two names, where the one with the `n` in it is the
    /// instruction and the one without is that instruction with `fwait` written first. `fwait` is
    /// an instruction of its own rather than a prefix, so it goes in front of everything including
    /// the REX byte, which is where a REX byte would be wrong: a prefix reaches the instruction
    /// after it, and the instruction after `fwait` is the one the REX byte is about.
    pub wait: bool,
    /// Whether the instruction is VEX encoded, and what the prefix has to say if it is.
    ///
    /// [`None`] for every row written the legacy way, which is all of them but the three shifts.
    pub vex: Option<Vex>,
    /// Whether the instruction is EVEX encoded, and what the prefix has to say if it is.
    ///
    /// [`None`] for everything but the AVX-512 rows at the end of the table.
    pub evex: Option<Evex>,
}

/// One row of the table below, for an instruction that carries no immediate or that carries one
/// of any size at all.
///
/// A row whose immediate is one byte only takes a number that byte can hold, by gas's rule in
/// [`Fits::Byte`], the same as [`avx`] and [`evex`] rows. Without that `pshufd $1000` was written
/// as `pshufd $0xe8`, which is not what was asked for and which every other assembler refuses.
const fn bytes(
    mnemonic: &'static str,
    args: &'static [Kind],
    size: Size,
    opcode: &'static [u8],
    fields: Fields,
    imm: ImmSize,
) -> Encoding {
    Encoding {
        mnemonic,
        args,
        fits: if matches!(imm, ImmSize::Ib) { Fits::Byte } else { Fits::Any },
        size,
        opcode,
        fields,
        imm,
        wait: false,
        vex: None,
        evex: None,
    }
}

/// One row for a VEX encoded instruction, which is where the third register operand goes.
///
/// The opcode is the last byte alone rather than the escape bytes and then the opcode, because the
/// escape is the `map` and is in the prefix. The size says both which of the mandatory prefixes
/// applies and whether the wide bit is set, the same as it does for a legacy row.
const fn third(
    mnemonic: &'static str,
    args: &'static [Kind],
    size: Size,
    map: Map,
    opcode: &'static [u8],
    vvvv: u8,
    fields: Fields,
) -> Encoding {
    Encoding {
        mnemonic,
        args,
        fits: Fits::Any,
        size,
        opcode,
        fields,
        imm: NO_IMM,
        wait: false,
        vex: Some(Vex { map, vvvv: Some(vvvv), long: false }),
        evex: None,
    }
}

/// One row for an instruction whose immediate has to be of a certain size, which is every row
/// here that carries one but the ten byte move.
const fn takes(
    mnemonic: &'static str,
    args: &'static [Kind],
    fits: Fits,
    size: Size,
    opcode: &'static [u8],
    fields: Fields,
    imm: ImmSize,
) -> Encoding {
    Encoding { mnemonic, args, fits, size, opcode, fields, imm, wait: false, vex: None, evex: None }
}

/// One row for an x87 instruction written with `fwait` in front of it.
///
/// Three of them have the same operands as the row beside them and differ in that one byte, which
/// is `fwait` and is an instruction rather than a prefix: it waits for whatever the coprocessor is
/// doing and then the next instruction runs. So each of the three is here twice, under the name
/// with the `n` in it and under the name without, rather than once with something reading the
/// mnemonic, since what a row is looked up by is the name a file wrote.
const fn waits(
    mnemonic: &'static str,
    args: &'static [Kind],
    size: Size,
    opcode: &'static [u8],
    fields: Fields,
) -> Encoding {
    Encoding {
        mnemonic,
        args,
        fits: Fits::Any,
        size,
        opcode,
        fields,
        imm: NO_IMM,
        wait: true,
        vex: None,
        evex: None,
    }
}

/// One row for a VEX encoded instruction with no third register, which is a move to or from a
/// mask register.
const fn vexed(
    mnemonic: &'static str,
    args: &'static [Kind],
    size: Size,
    opcode: &'static [u8],
    fields: Fields,
) -> Encoding {
    Encoding {
        mnemonic,
        args,
        fits: Fits::Any,
        size,
        opcode,
        fields,
        imm: NO_IMM,
        wait: false,
        vex: Some(Vex { map: Map::Escape, vvvv: None, long: false }),
        evex: None,
    }
}

/// One row for an AVX or AVX2 instruction, which is VEX encoded and has no EVEX form.
///
/// The length is not on the row, because the same row is an `xmm` and a `ymm` instruction and
/// which is the one bit of the prefix the registers named decide. An instruction whose first
/// argument is an immediate carries it as one byte, as for [`evex`].
const fn avx(
    mnemonic: &'static str,
    args: &'static [Kind],
    size: Size,
    map: Map,
    opcode: &'static [u8],
    vvvv: Option<u8>,
    fields: Fields,
) -> Encoding {
    let imm = matches!(args.first(), Some(Kind::Imm));
    Encoding {
        mnemonic,
        args,
        fits: if imm { Fits::Byte } else { Fits::Any },
        size,
        opcode,
        fields,
        imm: if imm { ImmSize::Ib } else { NO_IMM },
        wait: false,
        vex: Some(Vex { map, vvvv, long: false }),
        evex: None,
    }
}

/// One row for an EVEX encoded instruction.
///
/// The size is only the mandatory prefix, since the wide bit is on the [`Evex`]. An instruction
/// whose first argument is an immediate carries it as one byte, which every AVX-512 instruction
/// with an immediate does.
const fn evex(
    mnemonic: &'static str,
    args: &'static [Kind],
    size: Size,
    opcode: &'static [u8],
    fields: Fields,
    evex: Evex,
) -> Encoding {
    let imm = matches!(args.first(), Some(Kind::Imm));
    Encoding {
        mnemonic,
        args,
        fits: if imm { Fits::Byte } else { Fits::Any },
        size,
        opcode,
        fields,
        imm: if imm { ImmSize::Ib } else { NO_IMM },
        wait: false,
        vex: None,
        evex: Some(evex),
    }
}

/// An addressing byte whose spare three bits finish the opcode.
const fn ext(rm: u8, ext: u8) -> Fields {
    Fields::Ext { rm, ext }
}

/// An addressing byte that names two registers, or one register and an address.
const fn pair(rm: u8, reg: u8) -> Fields {
    Fields::Pair { rm, reg }
}

/// A register in the last byte of the opcode.
const fn plus(reg: u8) -> Fields {
    Fields::Plus { reg }
}

/// No addressing byte.
const NO_MODRM: Fields = Fields::None;
/// No immediate.
const NO_IMM: ImmSize = ImmSize::None;

// The argument lists, which are short and repeat, so they are written once and named. AT&T order
// throughout, so the source is in front of the destination.
static NO_ARGS: [Kind; 0] = [];
static R: [Kind; 1] = [Kind::Reg];
static RR: [Kind; 2] = [Kind::Reg, Kind::Reg];
static IR: [Kind; 2] = [Kind::Imm, Kind::Reg];
static IRR: [Kind; 3] = [Kind::Imm, Kind::Reg, Kind::Reg];
static IMR: [Kind; 3] = [Kind::Imm, Kind::Mem, Kind::Reg];
static RRR: [Kind; 3] = [Kind::Reg, Kind::Reg, Kind::Reg];
static MRR: [Kind; 3] = [Kind::Mem, Kind::Reg, Kind::Reg];
static RMR: [Kind; 3] = [Kind::Reg, Kind::Mem, Kind::Reg];
static MR: [Kind; 2] = [Kind::Mem, Kind::Reg];
static IM: [Kind; 2] = [Kind::Imm, Kind::Mem];
static RM: [Kind; 2] = [Kind::Reg, Kind::Mem];
static D: [Kind; 1] = [Kind::Dest];
static I: [Kind; 1] = [Kind::Imm];
static M: [Kind; 1] = [Kind::Mem];
// The same shapes with a vector register in them, which is a different row rather than a different
// spelling of the same one for the reason `Kind::Vec` gives.
static VV: [Kind; 2] = [Kind::Vec, Kind::Vec];
static MV: [Kind; 2] = [Kind::Mem, Kind::Vec];
static VM: [Kind; 2] = [Kind::Vec, Kind::Mem];
static RV: [Kind; 2] = [Kind::Reg, Kind::Vec];
static VR: [Kind; 2] = [Kind::Vec, Kind::Reg];
static IV: [Kind; 2] = [Kind::Imm, Kind::Vec];
// The three with an immediate naming which part of a vector register is meant, which is how the
// sixteen bit lane a `_Float16` lives in is reached.
static IMV: [Kind; 3] = [Kind::Imm, Kind::Mem, Kind::Vec];
static IRV: [Kind; 3] = [Kind::Imm, Kind::Reg, Kind::Vec];
static IVR: [Kind; 3] = [Kind::Imm, Kind::Vec, Kind::Reg];
// A shuffle, whose immediate says which lane of the source goes where in the destination.
static IVV: [Kind; 3] = [Kind::Imm, Kind::Vec, Kind::Vec];
// A lane of a vector register stored to memory, which is where `pextrd` may write.
static IVM: [Kind; 3] = [Kind::Imm, Kind::Vec, Kind::Mem];
/// The three and four argument shapes of the AVX-512 rows, which read two vectors, or a vector
/// and an address, and write a third vector.
static VVV: [Kind; 3] = [Kind::Vec, Kind::Vec, Kind::Vec];
static MVV: [Kind; 3] = [Kind::Mem, Kind::Vec, Kind::Vec];
static IVVV: [Kind; 4] = [Kind::Imm, Kind::Vec, Kind::Vec, Kind::Vec];
static IMVV: [Kind; 4] = [Kind::Imm, Kind::Mem, Kind::Vec, Kind::Vec];
static IRVV: [Kind; 4] = [Kind::Imm, Kind::Reg, Kind::Vec, Kind::Vec];
/// A general purpose register and a mask register, in the two directions `kmovq` goes.
static RK: [Kind; 2] = [Kind::Reg, Kind::Mask];
static KR: [Kind; 2] = [Kind::Mask, Kind::Reg];
/// Two masks read and a third written, as `kaddb` does.
static KKK: [Kind; 3] = [Kind::Mask, Kind::Mask, Kind::Mask];
/// A compare of two vectors, or of a vector and an address, into a mask.
static IVVK: [Kind; 4] = [Kind::Imm, Kind::Vec, Kind::Vec, Kind::Mask];
static IMVK: [Kind; 4] = [Kind::Imm, Kind::Mem, Kind::Vec, Kind::Mask];
/// The same with no immediate, as `vpcmpgtb` writes it.
static VVK: [Kind; 3] = [Kind::Vec, Kind::Vec, Kind::Mask];
static MVK: [Kind; 3] = [Kind::Mem, Kind::Vec, Kind::Mask];
/// A mask spread out into a vector, as `vpmovm2b` does.
static KV: [Kind; 2] = [Kind::Mask, Kind::Vec];
/// A blend of two vectors under a third, which is `vpblendvb`.
static VVVV: [Kind; 4] = [Kind::Vec, Kind::Vec, Kind::Vec, Kind::Vec];
static VMVV: [Kind; 4] = [Kind::Vec, Kind::Mem, Kind::Vec, Kind::Vec];
// The x87 stack positions, which are one argument or two and are never anything else. There is no
// row here mixing one with a register or with an address, because no instruction on this machine
// names a stack position and a register in the same breath.
static S: [Kind; 1] = [Kind::Stack];
static SS: [Kind; 2] = [Kind::Stack, Kind::Stack];
// A register and a number, in the order `outb %al, $0x80` writes them, which is the one
// instruction here whose immediate comes second.
static RI: [Kind; 2] = [Kind::Reg, Kind::Imm];
// The registers only a kernel names, each moved to and from a general purpose register, and a
// segment register to and from memory as well.
static CONTROL_R: [Kind; 2] = [Kind::Control, Kind::Reg];
static R_CONTROL: [Kind; 2] = [Kind::Reg, Kind::Control];
static DEBUG_R: [Kind; 2] = [Kind::Debug, Kind::Reg];
static R_DEBUG: [Kind; 2] = [Kind::Reg, Kind::Debug];
static SEG_R: [Kind; 2] = [Kind::Seg, Kind::Reg];
static R_SEG: [Kind; 2] = [Kind::Reg, Kind::Seg];
static SEG_M: [Kind; 2] = [Kind::Seg, Kind::Mem];
static M_SEG: [Kind; 2] = [Kind::Mem, Kind::Seg];

/// Every instruction [`crate::x86_64::written`] can name, and the bytes it comes out as.
///
/// In the order the opcodes that reach them are described in, and grouped the same way, so that
/// a reader with the manual open can go down all three tables together. An instruction reached
/// from more than one opcode is written once, where it is first reached, which is why the
/// conversions hold the widening a division needs and the arithmetic holds the clearing.
///
/// There are rows here the listing never names, and they are not a mistake. The assembler reads
/// files this compiler did not write, and what those files contain is what the person who wrote
/// them meant rather than what a C expression compiles to: a carry carried from one instruction to
/// the next, a rotate, a bit test, a count of a loop that leaves the flags alone. A row with no
/// opcode behind it in the listing costs a lookup nothing, and the alternative is refusing a file
/// gas assembles, so the claim the tests hold is one way round: everything the listing names is
/// here, and not everything here is named by the listing.
///
/// A row for a small immediate comes in front of the general row for the same instruction,
/// because a lookup takes the first row that fits and the narrower one is the one wanted.
static ENCODINGS: &[Encoding] = &[
    // Constants. The three narrow ones put the destination in the opcode rather than in an
    // addressing byte, which is one byte shorter and is why `B0` and `B8` are here instead of
    // `C6 /0` and `C7 /0`. The addressed forms reach memory as well and these do not, so where a
    // register is the destination the shorter row is the only row each of them needs.
    // The sixty four bit move is the one that keeps the addressing byte: its short form carries
    // the whole eight bytes and the addressed one sign extends four, so seven beats ten whenever
    // the number fits, which is nearly always.
    takes("movb", &IR, Fits::Byte, Byte, &[0xB0], plus(1), ImmSize::Ib),
    takes("movw", &IR, Fits::Word, Word, &[0xB8], plus(1), ImmSize::Iw),
    takes("movl", &IR, Fits::Long, Long, &[0xB8], plus(1), ImmSize::Id),
    takes("movq", &IR, Signed32, Quad, &[0xC7], ext(1, 0), ImmSize::Id),
    bytes("movq", &IR, Quad, &[0xB8], plus(1), ImmSize::Io),
    // The same constants into memory, which is the addressed form and the only form there is when
    // the destination is an address. This compiler does not write one, since a store it made has
    // the value in a register by the time it gets here, and a file written by hand writes the
    // number straight into the slot: `movq $0, -8(%rsp)` in libgmp's `tests/amd64call.asm` clears
    // the word it is about to read the control register into. There is no row for eight bytes of
    // immediate, because the instruction has no such form: a number wider than four bytes has to
    // go through a register whoever is writing it.
    takes("movb", &IM, Fits::Byte, Byte, &[0xC6], ext(1, 0), ImmSize::Ib),
    takes("movw", &IM, Fits::Word, Word, &[0xC7], ext(1, 0), ImmSize::Iw),
    takes("movl", &IM, Fits::Long, Long, &[0xC7], ext(1, 0), ImmSize::Id),
    takes("movq", &IM, Signed32, Quad, &[0xC7], ext(1, 0), ImmSize::Id),
    // The name a file gives the long form when it wants that form whatever the number is. It is the
    // row above and nothing else, and it is a row of its own rather than a spelling because a
    // lookup here is by mnemonic and a program that writes this has asked for ten bytes.
    bytes("movabsq", &IR, Quad, &[0xB8], plus(1), ImmSize::Io),
    // Arithmetic, register with register. The source is written first and is the register beside
    // the addressing byte, and the destination is the one the byte addresses.
    bytes("addb", &RR, Byte, &[0x00], pair(1, 0), NO_IMM),
    bytes("addw", &RR, Word, &[0x01], pair(1, 0), NO_IMM),
    bytes("addl", &RR, Long, &[0x01], pair(1, 0), NO_IMM),
    bytes("addq", &RR, Quad, &[0x01], pair(1, 0), NO_IMM),
    bytes("subb", &RR, Byte, &[0x28], pair(1, 0), NO_IMM),
    bytes("subw", &RR, Word, &[0x29], pair(1, 0), NO_IMM),
    bytes("subl", &RR, Long, &[0x29], pair(1, 0), NO_IMM),
    bytes("subq", &RR, Quad, &[0x29], pair(1, 0), NO_IMM),
    bytes("andb", &RR, Byte, &[0x20], pair(1, 0), NO_IMM),
    bytes("andw", &RR, Word, &[0x21], pair(1, 0), NO_IMM),
    bytes("andl", &RR, Long, &[0x21], pair(1, 0), NO_IMM),
    bytes("andq", &RR, Quad, &[0x21], pair(1, 0), NO_IMM),
    bytes("orb", &RR, Byte, &[0x08], pair(1, 0), NO_IMM),
    bytes("orw", &RR, Word, &[0x09], pair(1, 0), NO_IMM),
    bytes("orl", &RR, Long, &[0x09], pair(1, 0), NO_IMM),
    bytes("orq", &RR, Quad, &[0x09], pair(1, 0), NO_IMM),
    bytes("xorb", &RR, Byte, &[0x30], pair(1, 0), NO_IMM),
    bytes("xorw", &RR, Word, &[0x31], pair(1, 0), NO_IMM),
    bytes("xorl", &RR, Long, &[0x31], pair(1, 0), NO_IMM),
    bytes("xorq", &RR, Quad, &[0x31], pair(1, 0), NO_IMM),
    // The two of the eight that carry the flag from the instruction before them, which nothing this
    // compiler generates uses and every hand written addition of a number wider than a register is
    // made of. They sit in the same column as the rest, two opcodes above the addition and two
    // above the subtraction, and read exactly the same way round.
    bytes("adcb", &RR, Byte, &[0x10], pair(1, 0), NO_IMM),
    bytes("adcw", &RR, Word, &[0x11], pair(1, 0), NO_IMM),
    bytes("adcl", &RR, Long, &[0x11], pair(1, 0), NO_IMM),
    bytes("adcq", &RR, Quad, &[0x11], pair(1, 0), NO_IMM),
    bytes("sbbb", &RR, Byte, &[0x18], pair(1, 0), NO_IMM),
    bytes("sbbw", &RR, Word, &[0x19], pair(1, 0), NO_IMM),
    bytes("sbbl", &RR, Long, &[0x19], pair(1, 0), NO_IMM),
    bytes("sbbq", &RR, Quad, &[0x19], pair(1, 0), NO_IMM),
    // The multiply is the other way round from the rest of them: it is not one of the eight that
    // share an opcode column, and the register beside the addressing byte is its destination.
    bytes("imulw", &RR, Word, &[0x0F, 0xAF], pair(0, 1), NO_IMM),
    bytes("imull", &RR, Long, &[0x0F, 0xAF], pair(0, 1), NO_IMM),
    bytes("imulq", &RR, Quad, &[0x0F, 0xAF], pair(0, 1), NO_IMM),
    // The same arithmetic with the source in memory, which for the eight that share a column is
    // the opcode two above the register form: the column holds the direction, so `01` writes the
    // register into what the addressing byte names and `03` reads it out. The addressing byte
    // therefore names the memory and the register beside it is the destination, which is the
    // multiply's arrangement rather than the addition's and is why every row here reads the same
    // way round.
    bytes("addb", &MR, Byte, &[0x02], pair(0, 1), NO_IMM),
    bytes("addw", &MR, Word, &[0x03], pair(0, 1), NO_IMM),
    bytes("addl", &MR, Long, &[0x03], pair(0, 1), NO_IMM),
    bytes("addq", &MR, Quad, &[0x03], pair(0, 1), NO_IMM),
    bytes("subb", &MR, Byte, &[0x2A], pair(0, 1), NO_IMM),
    bytes("subw", &MR, Word, &[0x2B], pair(0, 1), NO_IMM),
    bytes("subl", &MR, Long, &[0x2B], pair(0, 1), NO_IMM),
    bytes("subq", &MR, Quad, &[0x2B], pair(0, 1), NO_IMM),
    bytes("andb", &MR, Byte, &[0x22], pair(0, 1), NO_IMM),
    bytes("andw", &MR, Word, &[0x23], pair(0, 1), NO_IMM),
    bytes("andl", &MR, Long, &[0x23], pair(0, 1), NO_IMM),
    bytes("andq", &MR, Quad, &[0x23], pair(0, 1), NO_IMM),
    bytes("orb", &MR, Byte, &[0x0A], pair(0, 1), NO_IMM),
    bytes("orw", &MR, Word, &[0x0B], pair(0, 1), NO_IMM),
    bytes("orl", &MR, Long, &[0x0B], pair(0, 1), NO_IMM),
    bytes("orq", &MR, Quad, &[0x0B], pair(0, 1), NO_IMM),
    bytes("xorb", &MR, Byte, &[0x32], pair(0, 1), NO_IMM),
    bytes("xorw", &MR, Word, &[0x33], pair(0, 1), NO_IMM),
    bytes("xorl", &MR, Long, &[0x33], pair(0, 1), NO_IMM),
    bytes("xorq", &MR, Quad, &[0x33], pair(0, 1), NO_IMM),
    bytes("adcb", &MR, Byte, &[0x12], pair(0, 1), NO_IMM),
    bytes("adcw", &MR, Word, &[0x13], pair(0, 1), NO_IMM),
    bytes("adcl", &MR, Long, &[0x13], pair(0, 1), NO_IMM),
    bytes("adcq", &MR, Quad, &[0x13], pair(0, 1), NO_IMM),
    bytes("sbbb", &MR, Byte, &[0x1A], pair(0, 1), NO_IMM),
    bytes("sbbw", &MR, Word, &[0x1B], pair(0, 1), NO_IMM),
    bytes("sbbl", &MR, Long, &[0x1B], pair(0, 1), NO_IMM),
    bytes("sbbq", &MR, Quad, &[0x1B], pair(0, 1), NO_IMM),
    bytes("imulw", &MR, Word, &[0x0F, 0xAF], pair(0, 1), NO_IMM),
    bytes("imull", &MR, Long, &[0x0F, 0xAF], pair(0, 1), NO_IMM),
    bytes("imulq", &MR, Quad, &[0x0F, 0xAF], pair(0, 1), NO_IMM),
    bytes("cmpb", &MR, Byte, &[0x3A], pair(0, 1), NO_IMM),
    bytes("cmpw", &MR, Word, &[0x3B], pair(0, 1), NO_IMM),
    bytes("cmpl", &MR, Long, &[0x3B], pair(0, 1), NO_IMM),
    bytes("cmpq", &MR, Quad, &[0x3B], pair(0, 1), NO_IMM),
    // The same arithmetic the other way about, a register read and an address written. This is the
    // opcode the register form already uses, since the register form is one register addressing
    // another and the only thing that changes is what the addressing byte names. So `01` is `addl`
    // between two registers above and `addl` into memory here, and the difference is entirely in
    // the byte behind it.
    //
    // Nothing this compiler emits is shaped this way. A read and modify and write of a variable in
    // memory goes through a register in the middle, because the value is wanted afterwards as often
    // as not and because a register is where the selector puts everything. A file written by hand
    // has no such habit and adds straight into the array it is walking, which is what GMP does in
    // every one of its loops.
    bytes("addb", &RM, Byte, &[0x00], pair(1, 0), NO_IMM),
    bytes("addw", &RM, Word, &[0x01], pair(1, 0), NO_IMM),
    bytes("addl", &RM, Long, &[0x01], pair(1, 0), NO_IMM),
    bytes("addq", &RM, Quad, &[0x01], pair(1, 0), NO_IMM),
    bytes("orb", &RM, Byte, &[0x08], pair(1, 0), NO_IMM),
    bytes("orw", &RM, Word, &[0x09], pair(1, 0), NO_IMM),
    bytes("orl", &RM, Long, &[0x09], pair(1, 0), NO_IMM),
    bytes("orq", &RM, Quad, &[0x09], pair(1, 0), NO_IMM),
    bytes("adcb", &RM, Byte, &[0x10], pair(1, 0), NO_IMM),
    bytes("adcw", &RM, Word, &[0x11], pair(1, 0), NO_IMM),
    bytes("adcl", &RM, Long, &[0x11], pair(1, 0), NO_IMM),
    bytes("adcq", &RM, Quad, &[0x11], pair(1, 0), NO_IMM),
    bytes("sbbb", &RM, Byte, &[0x18], pair(1, 0), NO_IMM),
    bytes("sbbw", &RM, Word, &[0x19], pair(1, 0), NO_IMM),
    bytes("sbbl", &RM, Long, &[0x19], pair(1, 0), NO_IMM),
    bytes("sbbq", &RM, Quad, &[0x19], pair(1, 0), NO_IMM),
    bytes("andb", &RM, Byte, &[0x20], pair(1, 0), NO_IMM),
    bytes("andw", &RM, Word, &[0x21], pair(1, 0), NO_IMM),
    bytes("andl", &RM, Long, &[0x21], pair(1, 0), NO_IMM),
    bytes("andq", &RM, Quad, &[0x21], pair(1, 0), NO_IMM),
    bytes("subb", &RM, Byte, &[0x28], pair(1, 0), NO_IMM),
    bytes("subw", &RM, Word, &[0x29], pair(1, 0), NO_IMM),
    bytes("subl", &RM, Long, &[0x29], pair(1, 0), NO_IMM),
    bytes("subq", &RM, Quad, &[0x29], pair(1, 0), NO_IMM),
    bytes("xorb", &RM, Byte, &[0x30], pair(1, 0), NO_IMM),
    bytes("xorw", &RM, Word, &[0x31], pair(1, 0), NO_IMM),
    bytes("xorl", &RM, Long, &[0x31], pair(1, 0), NO_IMM),
    bytes("xorq", &RM, Quad, &[0x31], pair(1, 0), NO_IMM),
    bytes("cmpb", &RM, Byte, &[0x38], pair(1, 0), NO_IMM),
    bytes("cmpw", &RM, Word, &[0x39], pair(1, 0), NO_IMM),
    bytes("cmpl", &RM, Long, &[0x39], pair(1, 0), NO_IMM),
    bytes("cmpq", &RM, Quad, &[0x39], pair(1, 0), NO_IMM),
    // Arithmetic, register with immediate. The eight of these share three opcodes and are told
    // apart by the three bits beside the register, which is the column the manual calls `/digit`.
    // Nothing narrower than a word can sign extend a byte, since a byte is already one.
    takes("addb", &IR, Fits::Byte, Byte, &[0x80], ext(1, 0), ImmSize::Ib),
    takes("addw", &IR, Signed8, Word, &[0x83], ext(1, 0), ImmSize::Ib),
    takes("addw", &IR, Fits::Word, Word, &[0x81], ext(1, 0), ImmSize::Iw),
    takes("addl", &IR, Signed8, Long, &[0x83], ext(1, 0), ImmSize::Ib),
    takes("addl", &IR, Fits::Long, Long, &[0x81], ext(1, 0), ImmSize::Id),
    takes("addq", &IR, Signed8, Quad, &[0x83], ext(1, 0), ImmSize::Ib),
    takes("addq", &IR, Signed32, Quad, &[0x81], ext(1, 0), ImmSize::Id),
    takes("subb", &IR, Fits::Byte, Byte, &[0x80], ext(1, 5), ImmSize::Ib),
    takes("subw", &IR, Signed8, Word, &[0x83], ext(1, 5), ImmSize::Ib),
    takes("subw", &IR, Fits::Word, Word, &[0x81], ext(1, 5), ImmSize::Iw),
    takes("subl", &IR, Signed8, Long, &[0x83], ext(1, 5), ImmSize::Ib),
    takes("subl", &IR, Fits::Long, Long, &[0x81], ext(1, 5), ImmSize::Id),
    takes("subq", &IR, Signed8, Quad, &[0x83], ext(1, 5), ImmSize::Ib),
    takes("subq", &IR, Signed32, Quad, &[0x81], ext(1, 5), ImmSize::Id),
    takes("andb", &IR, Fits::Byte, Byte, &[0x80], ext(1, 4), ImmSize::Ib),
    takes("andw", &IR, Signed8, Word, &[0x83], ext(1, 4), ImmSize::Ib),
    takes("andw", &IR, Fits::Word, Word, &[0x81], ext(1, 4), ImmSize::Iw),
    takes("andl", &IR, Signed8, Long, &[0x83], ext(1, 4), ImmSize::Ib),
    takes("andl", &IR, Fits::Long, Long, &[0x81], ext(1, 4), ImmSize::Id),
    takes("andq", &IR, Signed8, Quad, &[0x83], ext(1, 4), ImmSize::Ib),
    takes("andq", &IR, Signed32, Quad, &[0x81], ext(1, 4), ImmSize::Id),
    takes("orb", &IR, Fits::Byte, Byte, &[0x80], ext(1, 1), ImmSize::Ib),
    takes("orw", &IR, Signed8, Word, &[0x83], ext(1, 1), ImmSize::Ib),
    takes("orw", &IR, Fits::Word, Word, &[0x81], ext(1, 1), ImmSize::Iw),
    takes("orl", &IR, Signed8, Long, &[0x83], ext(1, 1), ImmSize::Ib),
    takes("orl", &IR, Fits::Long, Long, &[0x81], ext(1, 1), ImmSize::Id),
    takes("orq", &IR, Signed8, Quad, &[0x83], ext(1, 1), ImmSize::Ib),
    takes("orq", &IR, Signed32, Quad, &[0x81], ext(1, 1), ImmSize::Id),
    takes("xorb", &IR, Fits::Byte, Byte, &[0x80], ext(1, 6), ImmSize::Ib),
    takes("xorw", &IR, Signed8, Word, &[0x83], ext(1, 6), ImmSize::Ib),
    takes("xorw", &IR, Fits::Word, Word, &[0x81], ext(1, 6), ImmSize::Iw),
    takes("xorl", &IR, Signed8, Long, &[0x83], ext(1, 6), ImmSize::Ib),
    takes("xorl", &IR, Fits::Long, Long, &[0x81], ext(1, 6), ImmSize::Id),
    takes("xorq", &IR, Signed8, Quad, &[0x83], ext(1, 6), ImmSize::Ib),
    takes("xorq", &IR, Signed32, Quad, &[0x81], ext(1, 6), ImmSize::Id),
    takes("adcb", &IR, Fits::Byte, Byte, &[0x80], ext(1, 2), ImmSize::Ib),
    takes("adcw", &IR, Signed8, Word, &[0x83], ext(1, 2), ImmSize::Ib),
    takes("adcw", &IR, Fits::Word, Word, &[0x81], ext(1, 2), ImmSize::Iw),
    takes("adcl", &IR, Signed8, Long, &[0x83], ext(1, 2), ImmSize::Ib),
    takes("adcl", &IR, Fits::Long, Long, &[0x81], ext(1, 2), ImmSize::Id),
    takes("adcq", &IR, Signed8, Quad, &[0x83], ext(1, 2), ImmSize::Ib),
    takes("adcq", &IR, Signed32, Quad, &[0x81], ext(1, 2), ImmSize::Id),
    takes("sbbb", &IR, Fits::Byte, Byte, &[0x80], ext(1, 3), ImmSize::Ib),
    takes("sbbw", &IR, Signed8, Word, &[0x83], ext(1, 3), ImmSize::Ib),
    takes("sbbw", &IR, Fits::Word, Word, &[0x81], ext(1, 3), ImmSize::Iw),
    takes("sbbl", &IR, Signed8, Long, &[0x83], ext(1, 3), ImmSize::Ib),
    takes("sbbl", &IR, Fits::Long, Long, &[0x81], ext(1, 3), ImmSize::Id),
    takes("sbbq", &IR, Signed8, Quad, &[0x83], ext(1, 3), ImmSize::Ib),
    takes("sbbq", &IR, Signed32, Quad, &[0x81], ext(1, 3), ImmSize::Id),
    takes("cmpb", &IR, Fits::Byte, Byte, &[0x80], ext(1, 7), ImmSize::Ib),
    takes("cmpw", &IR, Signed8, Word, &[0x83], ext(1, 7), ImmSize::Ib),
    takes("cmpw", &IR, Fits::Word, Word, &[0x81], ext(1, 7), ImmSize::Iw),
    takes("cmpl", &IR, Signed8, Long, &[0x83], ext(1, 7), ImmSize::Ib),
    takes("cmpl", &IR, Fits::Long, Long, &[0x81], ext(1, 7), ImmSize::Id),
    takes("cmpq", &IR, Signed8, Quad, &[0x83], ext(1, 7), ImmSize::Ib),
    takes("cmpq", &IR, Signed32, Quad, &[0x81], ext(1, 7), ImmSize::Id),
    // The same eight writing an immediate to an address, which is the rows above with an address
    // where the register was and is why they are grouped by which digit names them rather than by
    // which instruction they are. The one thing this compiler writes here is the inclusive or of
    // zero with a byte that a probing prologue touches a page with, see `crate::frame::Probe`, and
    // the rest are for a file that adds a constant to a counter in memory without loading it first.
    takes("addb", &IM, Fits::Byte, Byte, &[0x80], ext(1, 0), ImmSize::Ib),
    takes("addw", &IM, Signed8, Word, &[0x83], ext(1, 0), ImmSize::Ib),
    takes("addw", &IM, Fits::Word, Word, &[0x81], ext(1, 0), ImmSize::Iw),
    takes("addl", &IM, Signed8, Long, &[0x83], ext(1, 0), ImmSize::Ib),
    takes("addl", &IM, Fits::Long, Long, &[0x81], ext(1, 0), ImmSize::Id),
    takes("addq", &IM, Signed8, Quad, &[0x83], ext(1, 0), ImmSize::Ib),
    takes("addq", &IM, Signed32, Quad, &[0x81], ext(1, 0), ImmSize::Id),
    takes("orb", &IM, Fits::Byte, Byte, &[0x80], ext(1, 1), ImmSize::Ib),
    takes("orw", &IM, Signed8, Word, &[0x83], ext(1, 1), ImmSize::Ib),
    takes("orw", &IM, Fits::Word, Word, &[0x81], ext(1, 1), ImmSize::Iw),
    takes("orl", &IM, Signed8, Long, &[0x83], ext(1, 1), ImmSize::Ib),
    takes("orl", &IM, Fits::Long, Long, &[0x81], ext(1, 1), ImmSize::Id),
    takes("orq", &IM, Signed8, Quad, &[0x83], ext(1, 1), ImmSize::Ib),
    takes("orq", &IM, Signed32, Quad, &[0x81], ext(1, 1), ImmSize::Id),
    takes("adcb", &IM, Fits::Byte, Byte, &[0x80], ext(1, 2), ImmSize::Ib),
    takes("adcw", &IM, Signed8, Word, &[0x83], ext(1, 2), ImmSize::Ib),
    takes("adcw", &IM, Fits::Word, Word, &[0x81], ext(1, 2), ImmSize::Iw),
    takes("adcl", &IM, Signed8, Long, &[0x83], ext(1, 2), ImmSize::Ib),
    takes("adcl", &IM, Fits::Long, Long, &[0x81], ext(1, 2), ImmSize::Id),
    takes("adcq", &IM, Signed8, Quad, &[0x83], ext(1, 2), ImmSize::Ib),
    takes("adcq", &IM, Signed32, Quad, &[0x81], ext(1, 2), ImmSize::Id),
    takes("sbbb", &IM, Fits::Byte, Byte, &[0x80], ext(1, 3), ImmSize::Ib),
    takes("sbbw", &IM, Signed8, Word, &[0x83], ext(1, 3), ImmSize::Ib),
    takes("sbbw", &IM, Fits::Word, Word, &[0x81], ext(1, 3), ImmSize::Iw),
    takes("sbbl", &IM, Signed8, Long, &[0x83], ext(1, 3), ImmSize::Ib),
    takes("sbbl", &IM, Fits::Long, Long, &[0x81], ext(1, 3), ImmSize::Id),
    takes("sbbq", &IM, Signed8, Quad, &[0x83], ext(1, 3), ImmSize::Ib),
    takes("sbbq", &IM, Signed32, Quad, &[0x81], ext(1, 3), ImmSize::Id),
    takes("andb", &IM, Fits::Byte, Byte, &[0x80], ext(1, 4), ImmSize::Ib),
    takes("andw", &IM, Signed8, Word, &[0x83], ext(1, 4), ImmSize::Ib),
    takes("andw", &IM, Fits::Word, Word, &[0x81], ext(1, 4), ImmSize::Iw),
    takes("andl", &IM, Signed8, Long, &[0x83], ext(1, 4), ImmSize::Ib),
    takes("andl", &IM, Fits::Long, Long, &[0x81], ext(1, 4), ImmSize::Id),
    takes("andq", &IM, Signed8, Quad, &[0x83], ext(1, 4), ImmSize::Ib),
    takes("andq", &IM, Signed32, Quad, &[0x81], ext(1, 4), ImmSize::Id),
    takes("subb", &IM, Fits::Byte, Byte, &[0x80], ext(1, 5), ImmSize::Ib),
    takes("subw", &IM, Signed8, Word, &[0x83], ext(1, 5), ImmSize::Ib),
    takes("subw", &IM, Fits::Word, Word, &[0x81], ext(1, 5), ImmSize::Iw),
    takes("subl", &IM, Signed8, Long, &[0x83], ext(1, 5), ImmSize::Ib),
    takes("subl", &IM, Fits::Long, Long, &[0x81], ext(1, 5), ImmSize::Id),
    takes("subq", &IM, Signed8, Quad, &[0x83], ext(1, 5), ImmSize::Ib),
    takes("subq", &IM, Signed32, Quad, &[0x81], ext(1, 5), ImmSize::Id),
    takes("xorb", &IM, Fits::Byte, Byte, &[0x80], ext(1, 6), ImmSize::Ib),
    takes("xorw", &IM, Signed8, Word, &[0x83], ext(1, 6), ImmSize::Ib),
    takes("xorw", &IM, Fits::Word, Word, &[0x81], ext(1, 6), ImmSize::Iw),
    takes("xorl", &IM, Signed8, Long, &[0x83], ext(1, 6), ImmSize::Ib),
    takes("xorl", &IM, Fits::Long, Long, &[0x81], ext(1, 6), ImmSize::Id),
    takes("xorq", &IM, Signed8, Quad, &[0x83], ext(1, 6), ImmSize::Ib),
    takes("xorq", &IM, Signed32, Quad, &[0x81], ext(1, 6), ImmSize::Id),
    takes("cmpb", &IM, Fits::Byte, Byte, &[0x80], ext(1, 7), ImmSize::Ib),
    takes("cmpw", &IM, Signed8, Word, &[0x83], ext(1, 7), ImmSize::Ib),
    takes("cmpw", &IM, Fits::Word, Word, &[0x81], ext(1, 7), ImmSize::Iw),
    takes("cmpl", &IM, Signed8, Long, &[0x83], ext(1, 7), ImmSize::Ib),
    takes("cmpl", &IM, Fits::Long, Long, &[0x81], ext(1, 7), ImmSize::Id),
    takes("cmpq", &IM, Signed8, Quad, &[0x83], ext(1, 7), ImmSize::Ib),
    takes("cmpq", &IM, Signed32, Quad, &[0x81], ext(1, 7), ImmSize::Id),
    // The three-operand multiply, whose source and destination are both written because they are
    // not the same register and whose immediate narrows the same way the eight above do.
    takes("imulw", &IRR, Signed8, Word, &[0x6B], pair(1, 2), ImmSize::Ib),
    takes("imulw", &IRR, Fits::Word, Word, &[0x69], pair(1, 2), ImmSize::Iw),
    takes("imull", &IRR, Signed8, Long, &[0x6B], pair(1, 2), ImmSize::Ib),
    takes("imull", &IRR, Fits::Long, Long, &[0x69], pair(1, 2), ImmSize::Id),
    takes("imulq", &IRR, Signed8, Quad, &[0x6B], pair(1, 2), ImmSize::Ib),
    takes("imulq", &IRR, Signed32, Quad, &[0x69], pair(1, 2), ImmSize::Id),
    // The same with the number multiplied read from memory, which is how a hash written in C
    // multiplies each word it reads by a constant.
    takes("imulw", &IMR, Signed8, Word, &[0x6B], pair(1, 2), ImmSize::Ib),
    takes("imulw", &IMR, Fits::Word, Word, &[0x69], pair(1, 2), ImmSize::Iw),
    takes("imull", &IMR, Signed8, Long, &[0x6B], pair(1, 2), ImmSize::Ib),
    takes("imull", &IMR, Fits::Long, Long, &[0x69], pair(1, 2), ImmSize::Id),
    takes("imulq", &IMR, Signed8, Quad, &[0x6B], pair(1, 2), ImmSize::Ib),
    takes("imulq", &IMR, Signed32, Quad, &[0x69], pair(1, 2), ImmSize::Id),
    // Negation and complement, which are two more of the eight that share `0xF7`.
    bytes("negb", &R, Byte, &[0xF6], ext(0, 3), NO_IMM),
    bytes("negw", &R, Word, &[0xF7], ext(0, 3), NO_IMM),
    bytes("negl", &R, Long, &[0xF7], ext(0, 3), NO_IMM),
    bytes("negq", &R, Quad, &[0xF7], ext(0, 3), NO_IMM),
    bytes("notb", &R, Byte, &[0xF6], ext(0, 2), NO_IMM),
    bytes("notw", &R, Word, &[0xF7], ext(0, 2), NO_IMM),
    bytes("notl", &R, Long, &[0xF7], ext(0, 2), NO_IMM),
    bytes("notq", &R, Quad, &[0xF7], ext(0, 2), NO_IMM),
    // Adding one and taking one away, which are two of the eight that share `0xFF` and are not what
    // a rule writes for `++`: an addition of one sets the carry flag and these leave it alone, so
    // the two are different instructions and the addition is the one a C program means. Hand
    // written assembly counts loops with these precisely because they leave the flag alone, which
    // is the whole reason a carry can be carried across an iteration at all.
    //
    // What does write one is `rucc_codegen::shorten`, at a level that asked for small code and at
    // an instruction where it has looked behind and found nothing reading the carry. That is the
    // same trade gcc makes, and it is a trade rather than a free win because the flag these leave
    // alone is a flag the next instruction to write the condition state has to merge with.
    bytes("incb", &R, Byte, &[0xFE], ext(0, 0), NO_IMM),
    bytes("incw", &R, Word, &[0xFF], ext(0, 0), NO_IMM),
    bytes("incl", &R, Long, &[0xFF], ext(0, 0), NO_IMM),
    bytes("incq", &R, Quad, &[0xFF], ext(0, 0), NO_IMM),
    bytes("decb", &R, Byte, &[0xFE], ext(0, 1), NO_IMM),
    bytes("decw", &R, Word, &[0xFF], ext(0, 1), NO_IMM),
    bytes("decl", &R, Long, &[0xFF], ext(0, 1), NO_IMM),
    bytes("decq", &R, Quad, &[0xFF], ext(0, 1), NO_IMM),
    // The four widenings a division needs, each of which is one byte and a prefix. They read one
    // fixed register and write another and name neither, which is why they have no arguments.
    bytes("cbtw", &NO_ARGS, Word, &[0x98], NO_MODRM, NO_IMM),
    bytes("cwtd", &NO_ARGS, Word, &[0x99], NO_MODRM, NO_IMM),
    bytes("cltd", &NO_ARGS, Long, &[0x99], NO_MODRM, NO_IMM),
    bytes("cqto", &NO_ARGS, Quad, &[0x99], NO_MODRM, NO_IMM),
    // The same two opcodes at the other size each can have, which widen the low half of `rax` into
    // the whole of it instead of into `rdx`. `cltq` is what a compiler writes to make an `int`
    // index into a pointer's width, which is why it is one of the commonest words in its output.
    bytes("cwtl", &NO_ARGS, Long, &[0x98], NO_MODRM, NO_IMM),
    bytes("cltq", &NO_ARGS, Quad, &[0x98], NO_MODRM, NO_IMM),
    // The divisions themselves, which are the last two of the eight.
    bytes("idivb", &R, Byte, &[0xF6], ext(0, 7), NO_IMM),
    bytes("idivw", &R, Word, &[0xF7], ext(0, 7), NO_IMM),
    bytes("idivl", &R, Long, &[0xF7], ext(0, 7), NO_IMM),
    bytes("idivq", &R, Quad, &[0xF7], ext(0, 7), NO_IMM),
    bytes("divb", &R, Byte, &[0xF6], ext(0, 6), NO_IMM),
    bytes("divw", &R, Word, &[0xF7], ext(0, 6), NO_IMM),
    bytes("divl", &R, Long, &[0xF7], ext(0, 6), NO_IMM),
    bytes("divq", &R, Quad, &[0xF7], ext(0, 6), NO_IMM),
    // The multiply that writes both halves of its answer, which is the fifth of the eight and is
    // not `imul` above: this one is unsigned and puts the top half in a second register the
    // instruction does not name, which is what a program doing arithmetic wider than a register
    // wants and what nothing a C expression compiles to ever needs.
    bytes("mulb", &R, Byte, &[0xF6], ext(0, 4), NO_IMM),
    bytes("mulw", &R, Word, &[0xF7], ext(0, 4), NO_IMM),
    bytes("mull", &R, Long, &[0xF7], ext(0, 4), NO_IMM),
    bytes("mulq", &R, Quad, &[0xF7], ext(0, 4), NO_IMM),
    // The signed one beside it, which is the same instruction in the same column and is a different
    // row from the two operand `imul` above because it takes one operand and writes two registers.
    bytes("imulb", &R, Byte, &[0xF6], ext(0, 5), NO_IMM),
    bytes("imulw", &R, Word, &[0xF7], ext(0, 5), NO_IMM),
    bytes("imull", &R, Long, &[0xF7], ext(0, 5), NO_IMM),
    bytes("imulq", &R, Quad, &[0xF7], ext(0, 5), NO_IMM),
    // All eight of the group naming an address instead of a register, which is the same opcode and
    // the same digit with the addressing byte pointing somewhere else. The compiler loads into a
    // register first every time, so none of these had a row. A file written by hand multiplies
    // straight out of the array it is walking, which is what `mulq 16(%r8)` in GMP's division is.
    bytes("negb", &M, Byte, &[0xF6], ext(0, 3), NO_IMM),
    bytes("negw", &M, Word, &[0xF7], ext(0, 3), NO_IMM),
    bytes("negl", &M, Long, &[0xF7], ext(0, 3), NO_IMM),
    bytes("negq", &M, Quad, &[0xF7], ext(0, 3), NO_IMM),
    bytes("notb", &M, Byte, &[0xF6], ext(0, 2), NO_IMM),
    bytes("notw", &M, Word, &[0xF7], ext(0, 2), NO_IMM),
    bytes("notl", &M, Long, &[0xF7], ext(0, 2), NO_IMM),
    bytes("notq", &M, Quad, &[0xF7], ext(0, 2), NO_IMM),
    bytes("mulb", &M, Byte, &[0xF6], ext(0, 4), NO_IMM),
    bytes("mulw", &M, Word, &[0xF7], ext(0, 4), NO_IMM),
    bytes("mull", &M, Long, &[0xF7], ext(0, 4), NO_IMM),
    bytes("mulq", &M, Quad, &[0xF7], ext(0, 4), NO_IMM),
    bytes("imulb", &M, Byte, &[0xF6], ext(0, 5), NO_IMM),
    bytes("imulw", &M, Word, &[0xF7], ext(0, 5), NO_IMM),
    bytes("imull", &M, Long, &[0xF7], ext(0, 5), NO_IMM),
    bytes("imulq", &M, Quad, &[0xF7], ext(0, 5), NO_IMM),
    bytes("divb", &M, Byte, &[0xF6], ext(0, 6), NO_IMM),
    bytes("divw", &M, Word, &[0xF7], ext(0, 6), NO_IMM),
    bytes("divl", &M, Long, &[0xF7], ext(0, 6), NO_IMM),
    bytes("divq", &M, Quad, &[0xF7], ext(0, 6), NO_IMM),
    bytes("idivb", &M, Byte, &[0xF6], ext(0, 7), NO_IMM),
    bytes("idivw", &M, Word, &[0xF7], ext(0, 7), NO_IMM),
    bytes("idivl", &M, Long, &[0xF7], ext(0, 7), NO_IMM),
    bytes("idivq", &M, Quad, &[0xF7], ext(0, 7), NO_IMM),
    // The two that share the other opcode of the pair, counted up and counted down.
    bytes("incb", &M, Byte, &[0xFE], ext(0, 0), NO_IMM),
    bytes("incw", &M, Word, &[0xFF], ext(0, 0), NO_IMM),
    bytes("incl", &M, Long, &[0xFF], ext(0, 0), NO_IMM),
    bytes("incq", &M, Quad, &[0xFF], ext(0, 0), NO_IMM),
    bytes("decb", &M, Byte, &[0xFE], ext(0, 1), NO_IMM),
    bytes("decw", &M, Word, &[0xFF], ext(0, 1), NO_IMM),
    bytes("decl", &M, Long, &[0xFF], ext(0, 1), NO_IMM),
    bytes("decq", &M, Quad, &[0xFF], ext(0, 1), NO_IMM),
    // Shifts by a constant, which carry one byte of count however wide the thing shifted is,
    // because nothing shifts a register by more than sixty three places.
    takes("shlb", &IR, Fits::Byte, Byte, &[0xC0], ext(1, 4), ImmSize::Ib),
    takes("shlw", &IR, Fits::Byte, Word, &[0xC1], ext(1, 4), ImmSize::Ib),
    takes("shll", &IR, Fits::Byte, Long, &[0xC1], ext(1, 4), ImmSize::Ib),
    takes("shlq", &IR, Fits::Byte, Quad, &[0xC1], ext(1, 4), ImmSize::Ib),
    takes("shrb", &IR, Fits::Byte, Byte, &[0xC0], ext(1, 5), ImmSize::Ib),
    takes("shrw", &IR, Fits::Byte, Word, &[0xC1], ext(1, 5), ImmSize::Ib),
    takes("shrl", &IR, Fits::Byte, Long, &[0xC1], ext(1, 5), ImmSize::Ib),
    takes("shrq", &IR, Fits::Byte, Quad, &[0xC1], ext(1, 5), ImmSize::Ib),
    takes("sarb", &IR, Fits::Byte, Byte, &[0xC0], ext(1, 7), ImmSize::Ib),
    takes("sarw", &IR, Fits::Byte, Word, &[0xC1], ext(1, 7), ImmSize::Ib),
    takes("sarl", &IR, Fits::Byte, Long, &[0xC1], ext(1, 7), ImmSize::Ib),
    takes("sarq", &IR, Fits::Byte, Quad, &[0xC1], ext(1, 7), ImmSize::Ib),
    // The rotates, which are the first two of the eight the shifts are the last four of. A C
    // program has no way to write one, which is why this compiler never emits one and why every
    // library that wants one writes it in assembly or in a builtin, but they are the same opcode
    // and the same two shapes as the shifts beside them.
    takes("rolb", &IR, Fits::Byte, Byte, &[0xC0], ext(1, 0), ImmSize::Ib),
    takes("rolw", &IR, Fits::Byte, Word, &[0xC1], ext(1, 0), ImmSize::Ib),
    takes("roll", &IR, Fits::Byte, Long, &[0xC1], ext(1, 0), ImmSize::Ib),
    takes("rolq", &IR, Fits::Byte, Quad, &[0xC1], ext(1, 0), ImmSize::Ib),
    takes("rorb", &IR, Fits::Byte, Byte, &[0xC0], ext(1, 1), ImmSize::Ib),
    takes("rorw", &IR, Fits::Byte, Word, &[0xC1], ext(1, 1), ImmSize::Ib),
    takes("rorl", &IR, Fits::Byte, Long, &[0xC1], ext(1, 1), ImmSize::Ib),
    takes("rorq", &IR, Fits::Byte, Quad, &[0xC1], ext(1, 1), ImmSize::Ib),
    // Shifts by a count, which is written and not encoded: the machine reads it from `cl` and
    // there is nowhere in the instruction to say so. The count is the argument at zero, and every
    // row here addresses the argument at one.
    bytes("shlb", &RR, Byte, &[0xD2], ext(1, 4), NO_IMM),
    bytes("shlw", &RR, Word, &[0xD3], ext(1, 4), NO_IMM),
    bytes("shll", &RR, Long, &[0xD3], ext(1, 4), NO_IMM),
    bytes("shlq", &RR, Quad, &[0xD3], ext(1, 4), NO_IMM),
    bytes("shrb", &RR, Byte, &[0xD2], ext(1, 5), NO_IMM),
    bytes("shrw", &RR, Word, &[0xD3], ext(1, 5), NO_IMM),
    bytes("shrl", &RR, Long, &[0xD3], ext(1, 5), NO_IMM),
    bytes("shrq", &RR, Quad, &[0xD3], ext(1, 5), NO_IMM),
    bytes("sarb", &RR, Byte, &[0xD2], ext(1, 7), NO_IMM),
    bytes("sarw", &RR, Word, &[0xD3], ext(1, 7), NO_IMM),
    bytes("sarl", &RR, Long, &[0xD3], ext(1, 7), NO_IMM),
    bytes("sarq", &RR, Quad, &[0xD3], ext(1, 7), NO_IMM),
    bytes("rolb", &RR, Byte, &[0xD2], ext(1, 0), NO_IMM),
    bytes("rolw", &RR, Word, &[0xD3], ext(1, 0), NO_IMM),
    bytes("roll", &RR, Long, &[0xD3], ext(1, 0), NO_IMM),
    bytes("rolq", &RR, Quad, &[0xD3], ext(1, 0), NO_IMM),
    bytes("rorb", &RR, Byte, &[0xD2], ext(1, 1), NO_IMM),
    bytes("rorw", &RR, Word, &[0xD3], ext(1, 1), NO_IMM),
    bytes("rorl", &RR, Long, &[0xD3], ext(1, 1), NO_IMM),
    bytes("rorq", &RR, Quad, &[0xD3], ext(1, 1), NO_IMM),
    // The two rotates that go through the carry, which are the middle pair of the eight and are the
    // reason the group is eight and not six. They shift a bit out into the carry and the old carry
    // in at the other end, so a chain of them moves a number wider than a register one place, which
    // is what a halving of a multiple precision sum is and is the only thing anybody uses them for.
    // No C expression names one, the way no C expression names a plain rotate.
    takes("rclb", &IR, Fits::Byte, Byte, &[0xC0], ext(1, 2), ImmSize::Ib),
    takes("rclw", &IR, Fits::Byte, Word, &[0xC1], ext(1, 2), ImmSize::Ib),
    takes("rcll", &IR, Fits::Byte, Long, &[0xC1], ext(1, 2), ImmSize::Ib),
    takes("rclq", &IR, Fits::Byte, Quad, &[0xC1], ext(1, 2), ImmSize::Ib),
    takes("rcrb", &IR, Fits::Byte, Byte, &[0xC0], ext(1, 3), ImmSize::Ib),
    takes("rcrw", &IR, Fits::Byte, Word, &[0xC1], ext(1, 3), ImmSize::Ib),
    takes("rcrl", &IR, Fits::Byte, Long, &[0xC1], ext(1, 3), ImmSize::Ib),
    takes("rcrq", &IR, Fits::Byte, Quad, &[0xC1], ext(1, 3), ImmSize::Ib),
    bytes("rclb", &RR, Byte, &[0xD2], ext(1, 2), NO_IMM),
    bytes("rclw", &RR, Word, &[0xD3], ext(1, 2), NO_IMM),
    bytes("rcll", &RR, Long, &[0xD3], ext(1, 2), NO_IMM),
    bytes("rclq", &RR, Quad, &[0xD3], ext(1, 2), NO_IMM),
    bytes("rcrb", &RR, Byte, &[0xD2], ext(1, 3), NO_IMM),
    bytes("rcrw", &RR, Word, &[0xD3], ext(1, 3), NO_IMM),
    bytes("rcrl", &RR, Long, &[0xD3], ext(1, 3), NO_IMM),
    bytes("rcrq", &RR, Quad, &[0xD3], ext(1, 3), NO_IMM),
    // All eight of them shifting by one place with nothing written down, which is a third opcode
    // beside the constant and the count. It is one byte shorter than writing the one out, and it is
    // not the same instruction as writing the one out: the overflow flag it leaves is defined here
    // and undefined there, which matters to the `rcr` a halving is built from.
    //
    // This is a row and not a choice. Nothing here decides to write `D1` where a file wrote `C1`
    // with a one behind it, because that is picking a shorter encoding for the same instruction and
    // is the relaxation pass's business rather than a lookup's. What this does is take the file
    // that wrote the one operand form, which is what every hand written file writes.
    bytes("rolb", &R, Byte, &[0xD0], ext(0, 0), NO_IMM),
    bytes("rolw", &R, Word, &[0xD1], ext(0, 0), NO_IMM),
    bytes("roll", &R, Long, &[0xD1], ext(0, 0), NO_IMM),
    bytes("rolq", &R, Quad, &[0xD1], ext(0, 0), NO_IMM),
    bytes("rorb", &R, Byte, &[0xD0], ext(0, 1), NO_IMM),
    bytes("rorw", &R, Word, &[0xD1], ext(0, 1), NO_IMM),
    bytes("rorl", &R, Long, &[0xD1], ext(0, 1), NO_IMM),
    bytes("rorq", &R, Quad, &[0xD1], ext(0, 1), NO_IMM),
    bytes("rclb", &R, Byte, &[0xD0], ext(0, 2), NO_IMM),
    bytes("rclw", &R, Word, &[0xD1], ext(0, 2), NO_IMM),
    bytes("rcll", &R, Long, &[0xD1], ext(0, 2), NO_IMM),
    bytes("rclq", &R, Quad, &[0xD1], ext(0, 2), NO_IMM),
    bytes("rcrb", &R, Byte, &[0xD0], ext(0, 3), NO_IMM),
    bytes("rcrw", &R, Word, &[0xD1], ext(0, 3), NO_IMM),
    bytes("rcrl", &R, Long, &[0xD1], ext(0, 3), NO_IMM),
    bytes("rcrq", &R, Quad, &[0xD1], ext(0, 3), NO_IMM),
    bytes("shlb", &R, Byte, &[0xD0], ext(0, 4), NO_IMM),
    bytes("shlw", &R, Word, &[0xD1], ext(0, 4), NO_IMM),
    bytes("shll", &R, Long, &[0xD1], ext(0, 4), NO_IMM),
    bytes("shlq", &R, Quad, &[0xD1], ext(0, 4), NO_IMM),
    bytes("shrb", &R, Byte, &[0xD0], ext(0, 5), NO_IMM),
    bytes("shrw", &R, Word, &[0xD1], ext(0, 5), NO_IMM),
    bytes("shrl", &R, Long, &[0xD1], ext(0, 5), NO_IMM),
    bytes("shrq", &R, Quad, &[0xD1], ext(0, 5), NO_IMM),
    bytes("sarb", &R, Byte, &[0xD0], ext(0, 7), NO_IMM),
    bytes("sarw", &R, Word, &[0xD1], ext(0, 7), NO_IMM),
    bytes("sarl", &R, Long, &[0xD1], ext(0, 7), NO_IMM),
    bytes("sarq", &R, Quad, &[0xD1], ext(0, 7), NO_IMM),
    // All three shapes again with the thing shifted in memory, which a compiler writes for a shift
    // of a variable it keeps in its frame and gas takes like any other address.
    takes("rolb", &IM, Fits::Byte, Byte, &[0xC0], ext(1, 0), ImmSize::Ib),
    takes("rolw", &IM, Fits::Byte, Word, &[0xC1], ext(1, 0), ImmSize::Ib),
    takes("roll", &IM, Fits::Byte, Long, &[0xC1], ext(1, 0), ImmSize::Ib),
    takes("rolq", &IM, Fits::Byte, Quad, &[0xC1], ext(1, 0), ImmSize::Ib),
    takes("rorb", &IM, Fits::Byte, Byte, &[0xC0], ext(1, 1), ImmSize::Ib),
    takes("rorw", &IM, Fits::Byte, Word, &[0xC1], ext(1, 1), ImmSize::Ib),
    takes("rorl", &IM, Fits::Byte, Long, &[0xC1], ext(1, 1), ImmSize::Ib),
    takes("rorq", &IM, Fits::Byte, Quad, &[0xC1], ext(1, 1), ImmSize::Ib),
    takes("rclb", &IM, Fits::Byte, Byte, &[0xC0], ext(1, 2), ImmSize::Ib),
    takes("rclw", &IM, Fits::Byte, Word, &[0xC1], ext(1, 2), ImmSize::Ib),
    takes("rcll", &IM, Fits::Byte, Long, &[0xC1], ext(1, 2), ImmSize::Ib),
    takes("rclq", &IM, Fits::Byte, Quad, &[0xC1], ext(1, 2), ImmSize::Ib),
    takes("rcrb", &IM, Fits::Byte, Byte, &[0xC0], ext(1, 3), ImmSize::Ib),
    takes("rcrw", &IM, Fits::Byte, Word, &[0xC1], ext(1, 3), ImmSize::Ib),
    takes("rcrl", &IM, Fits::Byte, Long, &[0xC1], ext(1, 3), ImmSize::Ib),
    takes("rcrq", &IM, Fits::Byte, Quad, &[0xC1], ext(1, 3), ImmSize::Ib),
    takes("shlb", &IM, Fits::Byte, Byte, &[0xC0], ext(1, 4), ImmSize::Ib),
    takes("shlw", &IM, Fits::Byte, Word, &[0xC1], ext(1, 4), ImmSize::Ib),
    takes("shll", &IM, Fits::Byte, Long, &[0xC1], ext(1, 4), ImmSize::Ib),
    takes("shlq", &IM, Fits::Byte, Quad, &[0xC1], ext(1, 4), ImmSize::Ib),
    takes("shrb", &IM, Fits::Byte, Byte, &[0xC0], ext(1, 5), ImmSize::Ib),
    takes("shrw", &IM, Fits::Byte, Word, &[0xC1], ext(1, 5), ImmSize::Ib),
    takes("shrl", &IM, Fits::Byte, Long, &[0xC1], ext(1, 5), ImmSize::Ib),
    takes("shrq", &IM, Fits::Byte, Quad, &[0xC1], ext(1, 5), ImmSize::Ib),
    takes("sarb", &IM, Fits::Byte, Byte, &[0xC0], ext(1, 7), ImmSize::Ib),
    takes("sarw", &IM, Fits::Byte, Word, &[0xC1], ext(1, 7), ImmSize::Ib),
    takes("sarl", &IM, Fits::Byte, Long, &[0xC1], ext(1, 7), ImmSize::Ib),
    takes("sarq", &IM, Fits::Byte, Quad, &[0xC1], ext(1, 7), ImmSize::Ib),
    bytes("rolb", &RM, Byte, &[0xD2], ext(1, 0), NO_IMM),
    bytes("rolw", &RM, Word, &[0xD3], ext(1, 0), NO_IMM),
    bytes("roll", &RM, Long, &[0xD3], ext(1, 0), NO_IMM),
    bytes("rolq", &RM, Quad, &[0xD3], ext(1, 0), NO_IMM),
    bytes("rorb", &RM, Byte, &[0xD2], ext(1, 1), NO_IMM),
    bytes("rorw", &RM, Word, &[0xD3], ext(1, 1), NO_IMM),
    bytes("rorl", &RM, Long, &[0xD3], ext(1, 1), NO_IMM),
    bytes("rorq", &RM, Quad, &[0xD3], ext(1, 1), NO_IMM),
    bytes("rclb", &RM, Byte, &[0xD2], ext(1, 2), NO_IMM),
    bytes("rclw", &RM, Word, &[0xD3], ext(1, 2), NO_IMM),
    bytes("rcll", &RM, Long, &[0xD3], ext(1, 2), NO_IMM),
    bytes("rclq", &RM, Quad, &[0xD3], ext(1, 2), NO_IMM),
    bytes("rcrb", &RM, Byte, &[0xD2], ext(1, 3), NO_IMM),
    bytes("rcrw", &RM, Word, &[0xD3], ext(1, 3), NO_IMM),
    bytes("rcrl", &RM, Long, &[0xD3], ext(1, 3), NO_IMM),
    bytes("rcrq", &RM, Quad, &[0xD3], ext(1, 3), NO_IMM),
    bytes("shlb", &RM, Byte, &[0xD2], ext(1, 4), NO_IMM),
    bytes("shlw", &RM, Word, &[0xD3], ext(1, 4), NO_IMM),
    bytes("shll", &RM, Long, &[0xD3], ext(1, 4), NO_IMM),
    bytes("shlq", &RM, Quad, &[0xD3], ext(1, 4), NO_IMM),
    bytes("shrb", &RM, Byte, &[0xD2], ext(1, 5), NO_IMM),
    bytes("shrw", &RM, Word, &[0xD3], ext(1, 5), NO_IMM),
    bytes("shrl", &RM, Long, &[0xD3], ext(1, 5), NO_IMM),
    bytes("shrq", &RM, Quad, &[0xD3], ext(1, 5), NO_IMM),
    bytes("sarb", &RM, Byte, &[0xD2], ext(1, 7), NO_IMM),
    bytes("sarw", &RM, Word, &[0xD3], ext(1, 7), NO_IMM),
    bytes("sarl", &RM, Long, &[0xD3], ext(1, 7), NO_IMM),
    bytes("sarq", &RM, Quad, &[0xD3], ext(1, 7), NO_IMM),
    bytes("rolb", &M, Byte, &[0xD0], ext(0, 0), NO_IMM),
    bytes("rolw", &M, Word, &[0xD1], ext(0, 0), NO_IMM),
    bytes("roll", &M, Long, &[0xD1], ext(0, 0), NO_IMM),
    bytes("rolq", &M, Quad, &[0xD1], ext(0, 0), NO_IMM),
    bytes("rorb", &M, Byte, &[0xD0], ext(0, 1), NO_IMM),
    bytes("rorw", &M, Word, &[0xD1], ext(0, 1), NO_IMM),
    bytes("rorl", &M, Long, &[0xD1], ext(0, 1), NO_IMM),
    bytes("rorq", &M, Quad, &[0xD1], ext(0, 1), NO_IMM),
    bytes("rclb", &M, Byte, &[0xD0], ext(0, 2), NO_IMM),
    bytes("rclw", &M, Word, &[0xD1], ext(0, 2), NO_IMM),
    bytes("rcll", &M, Long, &[0xD1], ext(0, 2), NO_IMM),
    bytes("rclq", &M, Quad, &[0xD1], ext(0, 2), NO_IMM),
    bytes("rcrb", &M, Byte, &[0xD0], ext(0, 3), NO_IMM),
    bytes("rcrw", &M, Word, &[0xD1], ext(0, 3), NO_IMM),
    bytes("rcrl", &M, Long, &[0xD1], ext(0, 3), NO_IMM),
    bytes("rcrq", &M, Quad, &[0xD1], ext(0, 3), NO_IMM),
    bytes("shlb", &M, Byte, &[0xD0], ext(0, 4), NO_IMM),
    bytes("shlw", &M, Word, &[0xD1], ext(0, 4), NO_IMM),
    bytes("shll", &M, Long, &[0xD1], ext(0, 4), NO_IMM),
    bytes("shlq", &M, Quad, &[0xD1], ext(0, 4), NO_IMM),
    bytes("shrb", &M, Byte, &[0xD0], ext(0, 5), NO_IMM),
    bytes("shrw", &M, Word, &[0xD1], ext(0, 5), NO_IMM),
    bytes("shrl", &M, Long, &[0xD1], ext(0, 5), NO_IMM),
    bytes("shrq", &M, Quad, &[0xD1], ext(0, 5), NO_IMM),
    bytes("sarb", &M, Byte, &[0xD0], ext(0, 7), NO_IMM),
    bytes("sarw", &M, Word, &[0xD1], ext(0, 7), NO_IMM),
    bytes("sarl", &M, Long, &[0xD1], ext(0, 7), NO_IMM),
    bytes("sarq", &M, Quad, &[0xD1], ext(0, 7), NO_IMM),
    // The two shifts that name a second register to shift in from, which are the only instructions
    // on this machine with three operands that are not a multiply. They move a window across a pair
    // of registers, which is what shifting a number wider than a register is, and they are how GMP
    // writes every one of its shifting loops.
    //
    // The count comes first in both shapes, either as a number or in `cl`, and the register shifted
    // in is second and the one shifted is last. That is the same order the manual writes them in
    // backwards, and the addressing byte therefore names the last argument and holds the middle one
    // beside it, which is the opposite way round from the three operand multiply above.
    takes("shldw", &IRR, Fits::Byte, Word, &[0x0F, 0xA4], pair(2, 1), ImmSize::Ib),
    takes("shldl", &IRR, Fits::Byte, Long, &[0x0F, 0xA4], pair(2, 1), ImmSize::Ib),
    takes("shldq", &IRR, Fits::Byte, Quad, &[0x0F, 0xA4], pair(2, 1), ImmSize::Ib),
    takes("shrdw", &IRR, Fits::Byte, Word, &[0x0F, 0xAC], pair(2, 1), ImmSize::Ib),
    takes("shrdl", &IRR, Fits::Byte, Long, &[0x0F, 0xAC], pair(2, 1), ImmSize::Ib),
    takes("shrdq", &IRR, Fits::Byte, Quad, &[0x0F, 0xAC], pair(2, 1), ImmSize::Ib),
    bytes("shldw", &RRR, Word, &[0x0F, 0xA5], pair(2, 1), NO_IMM),
    bytes("shldl", &RRR, Long, &[0x0F, 0xA5], pair(2, 1), NO_IMM),
    bytes("shldq", &RRR, Quad, &[0x0F, 0xA5], pair(2, 1), NO_IMM),
    bytes("shrdw", &RRR, Word, &[0x0F, 0xAD], pair(2, 1), NO_IMM),
    bytes("shrdl", &RRR, Long, &[0x0F, 0xAD], pair(2, 1), NO_IMM),
    bytes("shrdq", &RRR, Quad, &[0x0F, 0xAD], pair(2, 1), NO_IMM),
    // The three shifts that take their count in any register, which are BMI2 and are the only rows
    // here that are VEX encoded. They exist because the ordinary shift takes its count in `cl` and
    // nowhere else and writes the flags, so a loop shifting by several different amounts spends
    // instructions moving things through one register and cannot keep a comparison across the
    // shift. These take the count from wherever it already is and leave the flags alone, which is
    // why a file written by hand uses them and why a C expression never compiles to one.
    //
    // All three share the opcode `F7` in the `0F 38` table and are told apart by which mandatory
    // prefix they carry, which is the same way the legacy tables tell instructions apart and is
    // what lets [`Size`] carry it here: `0x66` is the left shift, `0xF3` the arithmetic right and
    // `0xF2` the logical right. The `q` rows are those with the wide bit, which is the other half
    // of what a size says.
    //
    // The operand order is the surprising part and it is the manual's, read backwards into AT&T.
    // Intel writes the destination, then the value being shifted, then the count, so AT&T writes
    // the count first, then the value, then the destination. The addressing byte therefore names
    // the middle argument and holds the last one beside it, and the count, which is the operand no
    // legacy encoding has anywhere to put, goes in the prefix.
    third("shlxl", &RRR, Word, Map::Escape38, &[0xF7], 0, pair(1, 2)),
    third("shlxq", &RRR, WordQuad, Map::Escape38, &[0xF7], 0, pair(1, 2)),
    third("sarxl", &RRR, Single, Map::Escape38, &[0xF7], 0, pair(1, 2)),
    third("sarxq", &RRR, SingleQuad, Map::Escape38, &[0xF7], 0, pair(1, 2)),
    third("shrxl", &RRR, Double, Map::Escape38, &[0xF7], 0, pair(1, 2)),
    third("shrxq", &RRR, DoubleQuad, Map::Escape38, &[0xF7], 0, pair(1, 2)),
    // The comparison, which is the eighth of the ones that share an opcode column and is written
    // the same way round as the subtraction it is.
    bytes("cmpb", &RR, Byte, &[0x38], pair(1, 0), NO_IMM),
    bytes("cmpw", &RR, Word, &[0x39], pair(1, 0), NO_IMM),
    bytes("cmpl", &RR, Long, &[0x39], pair(1, 0), NO_IMM),
    bytes("cmpq", &RR, Quad, &[0x39], pair(1, 0), NO_IMM),
    // The byte each condition sets, which is one opcode with the condition in its low four bits.
    // The conditional move, one opcode with the condition in its low four bits, the same way the
    // sets above are. Only the three widths the machine has: there is no eight bit conditional
    // move and the eight bit form of `select` is written with the thirty two bit one.
    //
    // The operands are the other way round from every move above it. `0F 45` reads a register or
    // memory and writes a register, so the register field is the destination, where in `88` and
    // `89` it is the source. The mnemonic order is the same in both and only the byte after the
    // opcode differs, which is exactly the kind of thing a table gets wrong silently.
    bytes("cmovew", &RR, Word, &[0x0F, 0x44], pair(0, 1), NO_IMM),
    bytes("cmovel", &RR, Long, &[0x0F, 0x44], pair(0, 1), NO_IMM),
    bytes("cmoveq", &RR, Quad, &[0x0F, 0x44], pair(0, 1), NO_IMM),
    bytes("cmovnew", &RR, Word, &[0x0F, 0x45], pair(0, 1), NO_IMM),
    bytes("cmovnel", &RR, Long, &[0x0F, 0x45], pair(0, 1), NO_IMM),
    bytes("cmovneq", &RR, Quad, &[0x0F, 0x45], pair(0, 1), NO_IMM),
    bytes("cmovlw", &RR, Word, &[0x0F, 0x4C], pair(0, 1), NO_IMM),
    bytes("cmovll", &RR, Long, &[0x0F, 0x4C], pair(0, 1), NO_IMM),
    bytes("cmovlq", &RR, Quad, &[0x0F, 0x4C], pair(0, 1), NO_IMM),
    bytes("cmovlew", &RR, Word, &[0x0F, 0x4E], pair(0, 1), NO_IMM),
    bytes("cmovlel", &RR, Long, &[0x0F, 0x4E], pair(0, 1), NO_IMM),
    bytes("cmovleq", &RR, Quad, &[0x0F, 0x4E], pair(0, 1), NO_IMM),
    bytes("cmovgw", &RR, Word, &[0x0F, 0x4F], pair(0, 1), NO_IMM),
    bytes("cmovgl", &RR, Long, &[0x0F, 0x4F], pair(0, 1), NO_IMM),
    bytes("cmovgq", &RR, Quad, &[0x0F, 0x4F], pair(0, 1), NO_IMM),
    bytes("cmovgew", &RR, Word, &[0x0F, 0x4D], pair(0, 1), NO_IMM),
    bytes("cmovgel", &RR, Long, &[0x0F, 0x4D], pair(0, 1), NO_IMM),
    bytes("cmovgeq", &RR, Quad, &[0x0F, 0x4D], pair(0, 1), NO_IMM),
    bytes("cmovbw", &RR, Word, &[0x0F, 0x42], pair(0, 1), NO_IMM),
    bytes("cmovbl", &RR, Long, &[0x0F, 0x42], pair(0, 1), NO_IMM),
    bytes("cmovbq", &RR, Quad, &[0x0F, 0x42], pair(0, 1), NO_IMM),
    bytes("cmovbew", &RR, Word, &[0x0F, 0x46], pair(0, 1), NO_IMM),
    bytes("cmovbel", &RR, Long, &[0x0F, 0x46], pair(0, 1), NO_IMM),
    bytes("cmovbeq", &RR, Quad, &[0x0F, 0x46], pair(0, 1), NO_IMM),
    bytes("cmovaw", &RR, Word, &[0x0F, 0x47], pair(0, 1), NO_IMM),
    bytes("cmoval", &RR, Long, &[0x0F, 0x47], pair(0, 1), NO_IMM),
    bytes("cmovaq", &RR, Quad, &[0x0F, 0x47], pair(0, 1), NO_IMM),
    bytes("cmovaew", &RR, Word, &[0x0F, 0x43], pair(0, 1), NO_IMM),
    bytes("cmovael", &RR, Long, &[0x0F, 0x43], pair(0, 1), NO_IMM),
    bytes("cmovaeq", &RR, Quad, &[0x0F, 0x43], pair(0, 1), NO_IMM),
    // The six conditions above that this compiler has no way to reach. A C comparison comes out as
    // one of the ten, because the sign and the overflow and the parity are not things an expression
    // asks about on their own: what `a < b` wants to know is the two of them together, which is `l`,
    // and the sign by itself is only the answer when one side is a zero the selector folded away.
    // A file written by hand asks about them directly and GMP does it in every other loop.
    bytes("cmovow", &RR, Word, &[0x0F, 0x40], pair(0, 1), NO_IMM),
    bytes("cmovol", &RR, Long, &[0x0F, 0x40], pair(0, 1), NO_IMM),
    bytes("cmovoq", &RR, Quad, &[0x0F, 0x40], pair(0, 1), NO_IMM),
    bytes("cmovnow", &RR, Word, &[0x0F, 0x41], pair(0, 1), NO_IMM),
    bytes("cmovnol", &RR, Long, &[0x0F, 0x41], pair(0, 1), NO_IMM),
    bytes("cmovnoq", &RR, Quad, &[0x0F, 0x41], pair(0, 1), NO_IMM),
    bytes("cmovsw", &RR, Word, &[0x0F, 0x48], pair(0, 1), NO_IMM),
    bytes("cmovsl", &RR, Long, &[0x0F, 0x48], pair(0, 1), NO_IMM),
    bytes("cmovsq", &RR, Quad, &[0x0F, 0x48], pair(0, 1), NO_IMM),
    bytes("cmovnsw", &RR, Word, &[0x0F, 0x49], pair(0, 1), NO_IMM),
    bytes("cmovnsl", &RR, Long, &[0x0F, 0x49], pair(0, 1), NO_IMM),
    bytes("cmovnsq", &RR, Quad, &[0x0F, 0x49], pair(0, 1), NO_IMM),
    bytes("cmovpw", &RR, Word, &[0x0F, 0x4A], pair(0, 1), NO_IMM),
    bytes("cmovpl", &RR, Long, &[0x0F, 0x4A], pair(0, 1), NO_IMM),
    bytes("cmovpq", &RR, Quad, &[0x0F, 0x4A], pair(0, 1), NO_IMM),
    bytes("cmovnpw", &RR, Word, &[0x0F, 0x4B], pair(0, 1), NO_IMM),
    bytes("cmovnpl", &RR, Long, &[0x0F, 0x4B], pair(0, 1), NO_IMM),
    bytes("cmovnpq", &RR, Quad, &[0x0F, 0x4B], pair(0, 1), NO_IMM),
    // All sixteen of them reading memory, which is the same opcode with an address where the source
    // register was and is the shape the instruction was put on the machine for. Loading a value and
    // then deciding whether to keep it is two instructions, one of which might fault on an address
    // the condition says not to read, and a conditional move from memory reads either way, so it is
    // no help with the fault and every help with the branch. This compiler loads first and moves
    // second, which is why it has never needed these. GMP writes `cmovc 16(%r8), %rbx` instead.
    bytes("cmovow", &MR, Word, &[0x0F, 0x40], pair(0, 1), NO_IMM),
    bytes("cmovol", &MR, Long, &[0x0F, 0x40], pair(0, 1), NO_IMM),
    bytes("cmovoq", &MR, Quad, &[0x0F, 0x40], pair(0, 1), NO_IMM),
    bytes("cmovnow", &MR, Word, &[0x0F, 0x41], pair(0, 1), NO_IMM),
    bytes("cmovnol", &MR, Long, &[0x0F, 0x41], pair(0, 1), NO_IMM),
    bytes("cmovnoq", &MR, Quad, &[0x0F, 0x41], pair(0, 1), NO_IMM),
    bytes("cmovbw", &MR, Word, &[0x0F, 0x42], pair(0, 1), NO_IMM),
    bytes("cmovbl", &MR, Long, &[0x0F, 0x42], pair(0, 1), NO_IMM),
    bytes("cmovbq", &MR, Quad, &[0x0F, 0x42], pair(0, 1), NO_IMM),
    bytes("cmovaew", &MR, Word, &[0x0F, 0x43], pair(0, 1), NO_IMM),
    bytes("cmovael", &MR, Long, &[0x0F, 0x43], pair(0, 1), NO_IMM),
    bytes("cmovaeq", &MR, Quad, &[0x0F, 0x43], pair(0, 1), NO_IMM),
    bytes("cmovew", &MR, Word, &[0x0F, 0x44], pair(0, 1), NO_IMM),
    bytes("cmovel", &MR, Long, &[0x0F, 0x44], pair(0, 1), NO_IMM),
    bytes("cmoveq", &MR, Quad, &[0x0F, 0x44], pair(0, 1), NO_IMM),
    bytes("cmovnew", &MR, Word, &[0x0F, 0x45], pair(0, 1), NO_IMM),
    bytes("cmovnel", &MR, Long, &[0x0F, 0x45], pair(0, 1), NO_IMM),
    bytes("cmovneq", &MR, Quad, &[0x0F, 0x45], pair(0, 1), NO_IMM),
    bytes("cmovbew", &MR, Word, &[0x0F, 0x46], pair(0, 1), NO_IMM),
    bytes("cmovbel", &MR, Long, &[0x0F, 0x46], pair(0, 1), NO_IMM),
    bytes("cmovbeq", &MR, Quad, &[0x0F, 0x46], pair(0, 1), NO_IMM),
    bytes("cmovaw", &MR, Word, &[0x0F, 0x47], pair(0, 1), NO_IMM),
    bytes("cmoval", &MR, Long, &[0x0F, 0x47], pair(0, 1), NO_IMM),
    bytes("cmovaq", &MR, Quad, &[0x0F, 0x47], pair(0, 1), NO_IMM),
    bytes("cmovsw", &MR, Word, &[0x0F, 0x48], pair(0, 1), NO_IMM),
    bytes("cmovsl", &MR, Long, &[0x0F, 0x48], pair(0, 1), NO_IMM),
    bytes("cmovsq", &MR, Quad, &[0x0F, 0x48], pair(0, 1), NO_IMM),
    bytes("cmovnsw", &MR, Word, &[0x0F, 0x49], pair(0, 1), NO_IMM),
    bytes("cmovnsl", &MR, Long, &[0x0F, 0x49], pair(0, 1), NO_IMM),
    bytes("cmovnsq", &MR, Quad, &[0x0F, 0x49], pair(0, 1), NO_IMM),
    bytes("cmovpw", &MR, Word, &[0x0F, 0x4A], pair(0, 1), NO_IMM),
    bytes("cmovpl", &MR, Long, &[0x0F, 0x4A], pair(0, 1), NO_IMM),
    bytes("cmovpq", &MR, Quad, &[0x0F, 0x4A], pair(0, 1), NO_IMM),
    bytes("cmovnpw", &MR, Word, &[0x0F, 0x4B], pair(0, 1), NO_IMM),
    bytes("cmovnpl", &MR, Long, &[0x0F, 0x4B], pair(0, 1), NO_IMM),
    bytes("cmovnpq", &MR, Quad, &[0x0F, 0x4B], pair(0, 1), NO_IMM),
    bytes("cmovlw", &MR, Word, &[0x0F, 0x4C], pair(0, 1), NO_IMM),
    bytes("cmovll", &MR, Long, &[0x0F, 0x4C], pair(0, 1), NO_IMM),
    bytes("cmovlq", &MR, Quad, &[0x0F, 0x4C], pair(0, 1), NO_IMM),
    bytes("cmovgew", &MR, Word, &[0x0F, 0x4D], pair(0, 1), NO_IMM),
    bytes("cmovgel", &MR, Long, &[0x0F, 0x4D], pair(0, 1), NO_IMM),
    bytes("cmovgeq", &MR, Quad, &[0x0F, 0x4D], pair(0, 1), NO_IMM),
    bytes("cmovlew", &MR, Word, &[0x0F, 0x4E], pair(0, 1), NO_IMM),
    bytes("cmovlel", &MR, Long, &[0x0F, 0x4E], pair(0, 1), NO_IMM),
    bytes("cmovleq", &MR, Quad, &[0x0F, 0x4E], pair(0, 1), NO_IMM),
    bytes("cmovgw", &MR, Word, &[0x0F, 0x4F], pair(0, 1), NO_IMM),
    bytes("cmovgl", &MR, Long, &[0x0F, 0x4F], pair(0, 1), NO_IMM),
    bytes("cmovgq", &MR, Quad, &[0x0F, 0x4F], pair(0, 1), NO_IMM),
    bytes("sete", &R, Byte, &[0x0F, 0x94], ext(0, 0), NO_IMM),
    bytes("setne", &R, Byte, &[0x0F, 0x95], ext(0, 0), NO_IMM),
    bytes("setl", &R, Byte, &[0x0F, 0x9C], ext(0, 0), NO_IMM),
    bytes("setle", &R, Byte, &[0x0F, 0x9E], ext(0, 0), NO_IMM),
    bytes("setg", &R, Byte, &[0x0F, 0x9F], ext(0, 0), NO_IMM),
    bytes("setge", &R, Byte, &[0x0F, 0x9D], ext(0, 0), NO_IMM),
    bytes("setb", &R, Byte, &[0x0F, 0x92], ext(0, 0), NO_IMM),
    bytes("setbe", &R, Byte, &[0x0F, 0x96], ext(0, 0), NO_IMM),
    bytes("seta", &R, Byte, &[0x0F, 0x97], ext(0, 0), NO_IMM),
    bytes("setae", &R, Byte, &[0x0F, 0x93], ext(0, 0), NO_IMM),
    // The two conditions on the parity flag, which are here because a float comparison is the one
    // thing on this machine that sets it for a reason anybody wants. It says the two operands were
    // not ordered, which is to say one of them was a NaN.
    bytes("setp", &R, Byte, &[0x0F, 0x9A], ext(0, 0), NO_IMM),
    bytes("setnp", &R, Byte, &[0x0F, 0x9B], ext(0, 0), NO_IMM),
    // The four conditions left, which complete the sixteen. The sign and the overflow are asked
    // about directly only by a file that knows what the flags hold, which a C expression never does.
    bytes("seto", &R, Byte, &[0x0F, 0x90], ext(0, 0), NO_IMM),
    bytes("setno", &R, Byte, &[0x0F, 0x91], ext(0, 0), NO_IMM),
    bytes("sets", &R, Byte, &[0x0F, 0x98], ext(0, 0), NO_IMM),
    bytes("setns", &R, Byte, &[0x0F, 0x99], ext(0, 0), NO_IMM),
    // The sixteen again with the byte they write in memory, which is where gcc puts a flag it
    // keeps in a `bool` on the stack.
    bytes("seto", &M, Byte, &[0x0F, 0x90], ext(0, 0), NO_IMM),
    bytes("setno", &M, Byte, &[0x0F, 0x91], ext(0, 0), NO_IMM),
    bytes("setb", &M, Byte, &[0x0F, 0x92], ext(0, 0), NO_IMM),
    bytes("setae", &M, Byte, &[0x0F, 0x93], ext(0, 0), NO_IMM),
    bytes("sete", &M, Byte, &[0x0F, 0x94], ext(0, 0), NO_IMM),
    bytes("setne", &M, Byte, &[0x0F, 0x95], ext(0, 0), NO_IMM),
    bytes("setbe", &M, Byte, &[0x0F, 0x96], ext(0, 0), NO_IMM),
    bytes("seta", &M, Byte, &[0x0F, 0x97], ext(0, 0), NO_IMM),
    bytes("sets", &M, Byte, &[0x0F, 0x98], ext(0, 0), NO_IMM),
    bytes("setns", &M, Byte, &[0x0F, 0x99], ext(0, 0), NO_IMM),
    bytes("setp", &M, Byte, &[0x0F, 0x9A], ext(0, 0), NO_IMM),
    bytes("setnp", &M, Byte, &[0x0F, 0x9B], ext(0, 0), NO_IMM),
    bytes("setl", &M, Byte, &[0x0F, 0x9C], ext(0, 0), NO_IMM),
    bytes("setge", &M, Byte, &[0x0F, 0x9D], ext(0, 0), NO_IMM),
    bytes("setle", &M, Byte, &[0x0F, 0x9E], ext(0, 0), NO_IMM),
    bytes("setg", &M, Byte, &[0x0F, 0x9F], ext(0, 0), NO_IMM),
    // The conversions between widths, which read a register and write a wider one, so the
    // destination is the register beside the addressing byte rather than the one it addresses.
    // How wide the source is decides the opcode and how wide the destination is decides the
    // prefix, which is why five opcodes make eleven instructions.
    bytes("movzbw", &RR, Word, &[0x0F, 0xB6], pair(0, 1), NO_IMM),
    bytes("movzbl", &RR, Long, &[0x0F, 0xB6], pair(0, 1), NO_IMM),
    bytes("movzbq", &RR, Quad, &[0x0F, 0xB6], pair(0, 1), NO_IMM),
    bytes("movzwl", &RR, Long, &[0x0F, 0xB7], pair(0, 1), NO_IMM),
    bytes("movzwq", &RR, Quad, &[0x0F, 0xB7], pair(0, 1), NO_IMM),
    bytes("movsbw", &RR, Word, &[0x0F, 0xBE], pair(0, 1), NO_IMM),
    bytes("movsbl", &RR, Long, &[0x0F, 0xBE], pair(0, 1), NO_IMM),
    bytes("movsbq", &RR, Quad, &[0x0F, 0xBE], pair(0, 1), NO_IMM),
    bytes("movswl", &RR, Long, &[0x0F, 0xBF], pair(0, 1), NO_IMM),
    bytes("movswq", &RR, Quad, &[0x0F, 0xBF], pair(0, 1), NO_IMM),
    bytes("movslq", &RR, Quad, &[0x63], pair(0, 1), NO_IMM),
    // The same widenings reading memory instead of a register, which is the same opcode with an
    // address where the source register was. `movzbl` has had its row since `_Bool` was read this
    // way and the other ten are here because a file somebody else wrote reaches memory as readily
    // as it reaches a register, where what this compiler emits has always loaded first.
    bytes("movzbw", &MR, Word, &[0x0F, 0xB6], pair(0, 1), NO_IMM),
    bytes("movzbq", &MR, Quad, &[0x0F, 0xB6], pair(0, 1), NO_IMM),
    bytes("movzwl", &MR, Long, &[0x0F, 0xB7], pair(0, 1), NO_IMM),
    bytes("movzwq", &MR, Quad, &[0x0F, 0xB7], pair(0, 1), NO_IMM),
    bytes("movsbw", &MR, Word, &[0x0F, 0xBE], pair(0, 1), NO_IMM),
    bytes("movsbl", &MR, Long, &[0x0F, 0xBE], pair(0, 1), NO_IMM),
    bytes("movsbq", &MR, Quad, &[0x0F, 0xBE], pair(0, 1), NO_IMM),
    bytes("movswl", &MR, Long, &[0x0F, 0xBF], pair(0, 1), NO_IMM),
    bytes("movswq", &MR, Quad, &[0x0F, 0xBF], pair(0, 1), NO_IMM),
    bytes("movslq", &MR, Quad, &[0x63], pair(0, 1), NO_IMM),
    // Asking about one bit and, for the three behind the first, changing it. The immediate form is
    // one opcode told apart by the three spare bits the way the eight above are, and the register
    // form is four opcodes of its own. There is no byte form of either, because the bit is counted
    // off a whole operand and the narrowest operand the instruction has is a word.
    //
    // The register form is written the way the arithmetic is and not the way the conversions are:
    // the bit number is the register beside the addressing byte and the thing it is counted in is
    // what the byte addresses, so the source is first in both the text and the encoding.
    takes("btw", &IR, Fits::Byte, Word, &[0x0F, 0xBA], ext(1, 4), ImmSize::Ib),
    takes("btl", &IR, Fits::Byte, Long, &[0x0F, 0xBA], ext(1, 4), ImmSize::Ib),
    takes("btq", &IR, Fits::Byte, Quad, &[0x0F, 0xBA], ext(1, 4), ImmSize::Ib),
    takes("btsw", &IR, Fits::Byte, Word, &[0x0F, 0xBA], ext(1, 5), ImmSize::Ib),
    takes("btsl", &IR, Fits::Byte, Long, &[0x0F, 0xBA], ext(1, 5), ImmSize::Ib),
    takes("btsq", &IR, Fits::Byte, Quad, &[0x0F, 0xBA], ext(1, 5), ImmSize::Ib),
    takes("btrw", &IR, Fits::Byte, Word, &[0x0F, 0xBA], ext(1, 6), ImmSize::Ib),
    takes("btrl", &IR, Fits::Byte, Long, &[0x0F, 0xBA], ext(1, 6), ImmSize::Ib),
    takes("btrq", &IR, Fits::Byte, Quad, &[0x0F, 0xBA], ext(1, 6), ImmSize::Ib),
    takes("btcw", &IR, Fits::Byte, Word, &[0x0F, 0xBA], ext(1, 7), ImmSize::Ib),
    takes("btcl", &IR, Fits::Byte, Long, &[0x0F, 0xBA], ext(1, 7), ImmSize::Ib),
    takes("btcq", &IR, Fits::Byte, Quad, &[0x0F, 0xBA], ext(1, 7), ImmSize::Ib),
    bytes("btw", &RR, Word, &[0x0F, 0xA3], pair(1, 0), NO_IMM),
    bytes("btl", &RR, Long, &[0x0F, 0xA3], pair(1, 0), NO_IMM),
    bytes("btq", &RR, Quad, &[0x0F, 0xA3], pair(1, 0), NO_IMM),
    bytes("btsw", &RR, Word, &[0x0F, 0xAB], pair(1, 0), NO_IMM),
    bytes("btsl", &RR, Long, &[0x0F, 0xAB], pair(1, 0), NO_IMM),
    bytes("btsq", &RR, Quad, &[0x0F, 0xAB], pair(1, 0), NO_IMM),
    bytes("btrw", &RR, Word, &[0x0F, 0xB3], pair(1, 0), NO_IMM),
    bytes("btrl", &RR, Long, &[0x0F, 0xB3], pair(1, 0), NO_IMM),
    bytes("btrq", &RR, Quad, &[0x0F, 0xB3], pair(1, 0), NO_IMM),
    bytes("btcw", &RR, Word, &[0x0F, 0xBB], pair(1, 0), NO_IMM),
    bytes("btcl", &RR, Long, &[0x0F, 0xBB], pair(1, 0), NO_IMM),
    bytes("btcq", &RR, Quad, &[0x0F, 0xBB], pair(1, 0), NO_IMM),
    // The same four on something in memory, which is the same opcode with the addressing byte
    // pointing at an address rather than at a register, the way the arithmetic's memory rows are.
    // The kernel's `test_bit` on a bit number it cannot see is `bt` on memory.
    takes("btw", &IM, Fits::Byte, Word, &[0x0F, 0xBA], ext(1, 4), ImmSize::Ib),
    takes("btl", &IM, Fits::Byte, Long, &[0x0F, 0xBA], ext(1, 4), ImmSize::Ib),
    takes("btq", &IM, Fits::Byte, Quad, &[0x0F, 0xBA], ext(1, 4), ImmSize::Ib),
    takes("btsw", &IM, Fits::Byte, Word, &[0x0F, 0xBA], ext(1, 5), ImmSize::Ib),
    takes("btsl", &IM, Fits::Byte, Long, &[0x0F, 0xBA], ext(1, 5), ImmSize::Ib),
    takes("btsq", &IM, Fits::Byte, Quad, &[0x0F, 0xBA], ext(1, 5), ImmSize::Ib),
    takes("btrw", &IM, Fits::Byte, Word, &[0x0F, 0xBA], ext(1, 6), ImmSize::Ib),
    takes("btrl", &IM, Fits::Byte, Long, &[0x0F, 0xBA], ext(1, 6), ImmSize::Ib),
    takes("btrq", &IM, Fits::Byte, Quad, &[0x0F, 0xBA], ext(1, 6), ImmSize::Ib),
    takes("btcw", &IM, Fits::Byte, Word, &[0x0F, 0xBA], ext(1, 7), ImmSize::Ib),
    takes("btcl", &IM, Fits::Byte, Long, &[0x0F, 0xBA], ext(1, 7), ImmSize::Ib),
    takes("btcq", &IM, Fits::Byte, Quad, &[0x0F, 0xBA], ext(1, 7), ImmSize::Ib),
    bytes("btw", &RM, Word, &[0x0F, 0xA3], pair(1, 0), NO_IMM),
    bytes("btl", &RM, Long, &[0x0F, 0xA3], pair(1, 0), NO_IMM),
    bytes("btq", &RM, Quad, &[0x0F, 0xA3], pair(1, 0), NO_IMM),
    bytes("btsw", &RM, Word, &[0x0F, 0xAB], pair(1, 0), NO_IMM),
    bytes("btsl", &RM, Long, &[0x0F, 0xAB], pair(1, 0), NO_IMM),
    bytes("btsq", &RM, Quad, &[0x0F, 0xAB], pair(1, 0), NO_IMM),
    bytes("btrw", &RM, Word, &[0x0F, 0xB3], pair(1, 0), NO_IMM),
    bytes("btrl", &RM, Long, &[0x0F, 0xB3], pair(1, 0), NO_IMM),
    bytes("btrq", &RM, Quad, &[0x0F, 0xB3], pair(1, 0), NO_IMM),
    bytes("btcw", &RM, Word, &[0x0F, 0xBB], pair(1, 0), NO_IMM),
    bytes("btcl", &RM, Long, &[0x0F, 0xBB], pair(1, 0), NO_IMM),
    bytes("btcq", &RM, Quad, &[0x0F, 0xBB], pair(1, 0), NO_IMM),
    // Finding the lowest or the highest bit that is set, which read one operand and write another,
    // so they go the way the conversions above do and not the way the bit tests beside them do.
    bytes("bsfw", &RR, Word, &[0x0F, 0xBC], pair(0, 1), NO_IMM),
    bytes("bsfl", &RR, Long, &[0x0F, 0xBC], pair(0, 1), NO_IMM),
    bytes("bsfq", &RR, Quad, &[0x0F, 0xBC], pair(0, 1), NO_IMM),
    bytes("bsrw", &RR, Word, &[0x0F, 0xBD], pair(0, 1), NO_IMM),
    bytes("bsrl", &RR, Long, &[0x0F, 0xBD], pair(0, 1), NO_IMM),
    bytes("bsrq", &RR, Quad, &[0x0F, 0xBD], pair(0, 1), NO_IMM),
    bytes("bsfw", &MR, Word, &[0x0F, 0xBC], pair(0, 1), NO_IMM),
    bytes("bsfl", &MR, Long, &[0x0F, 0xBC], pair(0, 1), NO_IMM),
    bytes("bsfq", &MR, Quad, &[0x0F, 0xBC], pair(0, 1), NO_IMM),
    bytes("bsrw", &MR, Word, &[0x0F, 0xBD], pair(0, 1), NO_IMM),
    bytes("bsrl", &MR, Long, &[0x0F, 0xBD], pair(0, 1), NO_IMM),
    bytes("bsrq", &MR, Quad, &[0x0F, 0xBD], pair(0, 1), NO_IMM),
    // The counts, which are the same two opcodes with `0xF3` in front of them and are not the same
    // instructions. A search answers where the bit it found is and a count answers how many places
    // there were before it, so the two agree only on an argument with one bit in it, and a search
    // leaves its destination alone for an argument with none where a count writes the width. The
    // prefix was ignored on a processor without the feature, which is how a program comes to write
    // the search when it means the count: assemblers older than the mnemonic had no way to spell
    // it, and libgmp still writes `rep;bsr` with a comment saying it is `lzcnt`.
    //
    // No sixteen bit form. That one is `66 f3 0f bd`, which is two prefixes at once, and no `Size`
    // here says both. Nothing asks for it, since what a program counts the bits of is a word or a
    // limb and neither of those is sixteen bits on this machine.
    bytes("lzcntl", &RR, Single, &[0x0F, 0xBD], pair(0, 1), NO_IMM),
    bytes("lzcntq", &RR, SingleQuad, &[0x0F, 0xBD], pair(0, 1), NO_IMM),
    bytes("tzcntl", &RR, Single, &[0x0F, 0xBC], pair(0, 1), NO_IMM),
    bytes("tzcntq", &RR, SingleQuad, &[0x0F, 0xBC], pair(0, 1), NO_IMM),
    bytes("lzcntl", &MR, Single, &[0x0F, 0xBD], pair(0, 1), NO_IMM),
    bytes("lzcntq", &MR, SingleQuad, &[0x0F, 0xBD], pair(0, 1), NO_IMM),
    bytes("tzcntl", &MR, Single, &[0x0F, 0xBC], pair(0, 1), NO_IMM),
    bytes("tzcntq", &MR, SingleQuad, &[0x0F, 0xBC], pair(0, 1), NO_IMM),
    // Counting the bits that are set, which is the third opcode of the same family and the one
    // `__builtin_popcount` is short for. Its own feature bit rather than part of any SSE level, so
    // a processor has it or not whatever else it has, and `-mpopcnt` is what says it does. No
    // sixteen bit form, for the reason the two counts above have none.
    bytes("popcntl", &RR, Single, &[0x0F, 0xB8], pair(0, 1), NO_IMM),
    bytes("popcntq", &RR, SingleQuad, &[0x0F, 0xB8], pair(0, 1), NO_IMM),
    bytes("popcntl", &MR, Single, &[0x0F, 0xB8], pair(0, 1), NO_IMM),
    bytes("popcntq", &MR, SingleQuad, &[0x0F, 0xB8], pair(0, 1), NO_IMM),
    // One step of the CRC-32C checksum, which is SSE4.2 and is what `_mm_crc32_u8` and its three
    // wider siblings are. The destination is the running checksum and the source is the next one,
    // two, four or eight bytes of data, so the letter is the width of the source and not of the
    // destination: every form but the last accumulates into a thirty two bit register, and the
    // last is written on sixty four bits only because `REX.W` is how the machine says the source is
    // eight bytes, with the top half of the destination cleared. The byte form is its own opcode,
    // `F0`, the way every byte form on this machine is, and the rest share `F1` and are told apart
    // by the prefixes. See `Size::WordDouble` for the sixteen bit one.
    bytes("crc32b", &RR, Double, &[0x0F, 0x38, 0xF0], pair(0, 1), NO_IMM),
    bytes("crc32w", &RR, WordDouble, &[0x0F, 0x38, 0xF1], pair(0, 1), NO_IMM),
    bytes("crc32l", &RR, Double, &[0x0F, 0x38, 0xF1], pair(0, 1), NO_IMM),
    bytes("crc32q", &RR, DoubleQuad, &[0x0F, 0x38, 0xF1], pair(0, 1), NO_IMM),
    bytes("crc32b", &MR, Double, &[0x0F, 0x38, 0xF0], pair(0, 1), NO_IMM),
    bytes("crc32w", &MR, WordDouble, &[0x0F, 0x38, 0xF1], pair(0, 1), NO_IMM),
    bytes("crc32l", &MR, Double, &[0x0F, 0x38, 0xF1], pair(0, 1), NO_IMM),
    bytes("crc32q", &MR, DoubleQuad, &[0x0F, 0x38, 0xF1], pair(0, 1), NO_IMM),
    // Turning a number round, which reverses the bytes of a register in place. The register is in
    // the low three bits of the second opcode byte rather than in an addressing byte, the way a
    // push and a pop hold theirs, so there is no `ModRM` here at all.
    //
    // No sixteen bit form, and this one is not about what can be spelled. `bswap %ax` assembles and
    // Intel's own description says the result is undefined, so the instruction exists and means
    // nothing. A program that wants two bytes the other way round writes a rotate by eight.
    bytes("bswapl", &R, Long, &[0x0F, 0xC8], plus(0), NO_IMM),
    bytes("bswapq", &R, Quad, &[0x0F, 0xC8], plus(0), NO_IMM),
    // A copy between registers, which is a store to a register rather than a load from one, so it
    // is written the same way round as the arithmetic above and not as the conversions.
    bytes("movb", &RR, Byte, &[0x88], pair(1, 0), NO_IMM),
    bytes("movw", &RR, Word, &[0x89], pair(1, 0), NO_IMM),
    bytes("movl", &RR, Long, &[0x89], pair(1, 0), NO_IMM),
    bytes("movq", &RR, Quad, &[0x89], pair(1, 0), NO_IMM),
    // The address computation, which is the one instruction that is given an address and does not
    // read it.
    bytes("leaq", &MR, Quad, &[0x8D], pair(0, 1), NO_IMM),
    // The same instruction keeping only the low thirty two bits of what it worked out, which this
    // compiler has no use for because a pointer here is sixty four bits wide and which hand written
    // code uses as an addition that does not touch the flags.
    bytes("leal", &MR, Long, &[0x8D], pair(0, 1), NO_IMM),
    // Reading and writing memory, which are one opcode apart and are the same instruction with
    // the two ends swapped.
    bytes("movb", &MR, Byte, &[0x8A], pair(0, 1), NO_IMM),
    bytes("movw", &MR, Word, &[0x8B], pair(0, 1), NO_IMM),
    bytes("movl", &MR, Long, &[0x8B], pair(0, 1), NO_IMM),
    bytes("movq", &MR, Quad, &[0x8B], pair(0, 1), NO_IMM),
    bytes("movb", &RM, Byte, &[0x88], pair(1, 0), NO_IMM),
    bytes("movw", &RM, Word, &[0x89], pair(1, 0), NO_IMM),
    bytes("movl", &RM, Long, &[0x89], pair(1, 0), NO_IMM),
    bytes("movq", &RM, Quad, &[0x89], pair(1, 0), NO_IMM),
    // Reading a byte and widening it in the one instruction, which is the same opcode as the
    // register form above with a memory operand where its register was. The byte the opcode reads
    // is a byte whether the operand is a register or an address, so the width here is the width
    // written rather than the width read, which is what the register form says too. This is how a
    // `_Bool` is read, and it is the only widening load, because it is the only one where the
    // value in memory is narrower than anything that will look at it.
    bytes("movzbl", &MR, Long, &[0x0F, 0xB6], pair(0, 1), NO_IMM),
    // A call, whose distance to the function it goes to is not known here.
    bytes("call", &D, Long, &[0xE8], NO_MODRM, ImmSize::Cd),
    // The same mnemonic through an address, which is a different row rather than a different
    // mnemonic because a lookup here is by what the arguments are and not only by what the
    // instruction is called. It is one of the eight that share `0xFF` and is told from the rest by
    // the three bits beside the register. Sixty four bits without a prefix saying so, the way a
    // jump and a push are, since there is no form of it that calls a thirty two bit address.
    bytes("call", &R, Long, &[0xFF], ext(0, 2), NO_IMM),
    // And through an address, which is the jump's other row seen from one place along. This
    // compiler loads the address into a register and calls the register, so it writes the row
    // above and never this one, and a file written by hand writes the load and the call as one
    // instruction because it can: `call *(%rax)` in libgmp's `tests/amd64call.asm` calls whatever
    // the global offset table entry it just loaded points at.
    bytes("call", &M, Long, &[0xFF], ext(0, 2), NO_IMM),
    // What a condition and the block layout come to. The test is a comparison against zero that
    // names the same register twice, so both of its arguments are the one operand.
    bytes("testb", &RR, Byte, &[0x84], pair(1, 0), NO_IMM),
    // The rest of it. A test against zero is the only one this compiler writes and a byte is the
    // only width it writes it at, because what it is testing is a condition that already came out
    // of a comparison. A file written by hand tests a register against itself at its own width and
    // tests single bits with an immediate, which is what `test $1, %r10` is, and neither of those
    // had a row.
    //
    // The immediate here is never sign extended from a byte. The eight instructions that share
    // `0x83` all have that form and this one does not, so a small number still costs the full
    // width, which is one of the few places the table cannot be filled in by analogy.
    bytes("testw", &RR, Word, &[0x85], pair(1, 0), NO_IMM),
    bytes("testl", &RR, Long, &[0x85], pair(1, 0), NO_IMM),
    bytes("testq", &RR, Quad, &[0x85], pair(1, 0), NO_IMM),
    bytes("testb", &RM, Byte, &[0x84], pair(1, 0), NO_IMM),
    bytes("testw", &RM, Word, &[0x85], pair(1, 0), NO_IMM),
    bytes("testl", &RM, Long, &[0x85], pair(1, 0), NO_IMM),
    bytes("testq", &RM, Quad, &[0x85], pair(1, 0), NO_IMM),
    bytes("testb", &MR, Byte, &[0x84], pair(0, 1), NO_IMM),
    bytes("testw", &MR, Word, &[0x85], pair(0, 1), NO_IMM),
    bytes("testl", &MR, Long, &[0x85], pair(0, 1), NO_IMM),
    bytes("testq", &MR, Quad, &[0x85], pair(0, 1), NO_IMM),
    takes("testb", &IR, Fits::Byte, Byte, &[0xF6], ext(1, 0), ImmSize::Ib),
    takes("testw", &IR, Fits::Word, Word, &[0xF7], ext(1, 0), ImmSize::Iw),
    takes("testl", &IR, Fits::Long, Long, &[0xF7], ext(1, 0), ImmSize::Id),
    takes("testq", &IR, Signed32, Quad, &[0xF7], ext(1, 0), ImmSize::Id),
    takes("testb", &IM, Fits::Byte, Byte, &[0xF6], ext(1, 0), ImmSize::Ib),
    takes("testw", &IM, Fits::Word, Word, &[0xF7], ext(1, 0), ImmSize::Iw),
    takes("testl", &IM, Fits::Long, Long, &[0xF7], ext(1, 0), ImmSize::Id),
    takes("testq", &IM, Signed32, Quad, &[0xF7], ext(1, 0), ImmSize::Id),
    // The three instructions that do nothing but touch the carry. A C expression has no carry to
    // touch and the selector never leaves one lying about on purpose, so none of these has been
    // wanted. GMP clears it before a loop that will add into it and complements it to turn a borrow
    // into a carry, and both of those are a whole instruction because there is nothing smaller.
    bytes("clc", &NO_ARGS, Long, &[0xF8], NO_MODRM, NO_IMM),
    bytes("stc", &NO_ARGS, Long, &[0xF9], NO_MODRM, NO_IMM),
    bytes("cmc", &NO_ARGS, Long, &[0xF5], NO_MODRM, NO_IMM),
    // The string move, which reads at `rsi` and writes at `rdi` and steps both, and which is one
    // instruction and a whole copy when a repeat prefix is put in front of it. Nothing this
    // compiler emits is a string instruction, because a copy it knows the length of comes out as a
    // loop it can schedule and one it does not comes out as a call to `memcpy`. A file that wants
    // the two byte version writes it itself, which is what GMP's `copyi` does.
    bytes("movsb", &NO_ARGS, Byte, &[0xA4], NO_MODRM, NO_IMM),
    bytes("movsw", &NO_ARGS, Word, &[0xA5], NO_MODRM, NO_IMM),
    bytes("movsl", &NO_ARGS, Long, &[0xA5], NO_MODRM, NO_IMM),
    bytes("movsq", &NO_ARGS, Quad, &[0xA5], NO_MODRM, NO_IMM),
    // The ten conditional jumps, which are one opcode column of sixteen and are told apart by the
    // low four bits the way the ten `setcc` above are. The low bits are the same ones: a jump on
    // a condition and a set on it differ in the byte before, `0x8` against `0x9`, and in nothing
    // else. A near jump reaches anywhere in the section, and the short form that fits its
    // distance in one byte is not here because choosing it is not an encoding question: it needs
    // the distance, the distance needs the layout, and the layout changes when a jump gets
    // shorter. That is a pass over a whole section and `je` above has been waiting for it since
    // before there was anything to jump on.
    bytes("je", &D, Long, &[0x0F, 0x84], NO_MODRM, ImmSize::Cd),
    bytes("jne", &D, Long, &[0x0F, 0x85], NO_MODRM, ImmSize::Cd),
    bytes("jl", &D, Long, &[0x0F, 0x8C], NO_MODRM, ImmSize::Cd),
    bytes("jle", &D, Long, &[0x0F, 0x8E], NO_MODRM, ImmSize::Cd),
    bytes("jg", &D, Long, &[0x0F, 0x8F], NO_MODRM, ImmSize::Cd),
    bytes("jge", &D, Long, &[0x0F, 0x8D], NO_MODRM, ImmSize::Cd),
    bytes("jb", &D, Long, &[0x0F, 0x82], NO_MODRM, ImmSize::Cd),
    bytes("jbe", &D, Long, &[0x0F, 0x86], NO_MODRM, ImmSize::Cd),
    bytes("ja", &D, Long, &[0x0F, 0x87], NO_MODRM, ImmSize::Cd),
    bytes("jae", &D, Long, &[0x0F, 0x83], NO_MODRM, ImmSize::Cd),
    // The other six of the sixteen, which sit in the same column and differ in the same four bits.
    // A loop that counts up to zero ends with `js` and a multiple precision add that has run out of
    // limbs ends with `jnc`, and neither of those is something a C expression asks for, so the ten
    // above were enough until a file somebody else wrote came along.
    bytes("jo", &D, Long, &[0x0F, 0x80], NO_MODRM, ImmSize::Cd),
    bytes("jno", &D, Long, &[0x0F, 0x81], NO_MODRM, ImmSize::Cd),
    bytes("js", &D, Long, &[0x0F, 0x88], NO_MODRM, ImmSize::Cd),
    bytes("jns", &D, Long, &[0x0F, 0x89], NO_MODRM, ImmSize::Cd),
    bytes("jp", &D, Long, &[0x0F, 0x8A], NO_MODRM, ImmSize::Cd),
    bytes("jnp", &D, Long, &[0x0F, 0x8B], NO_MODRM, ImmSize::Cd),
    bytes("jmp", &D, Long, &[0xE9], NO_MODRM, ImmSize::Cd),
    // The jump on a register being zero, which is the one branch on this machine that has no long
    // form at all: a hundred and twenty seven bytes either way is the whole of its reach, and a
    // program that needs further writes a test and one of the jumps above. It reads `rcx` and names
    // it in the mnemonic rather than in an operand, so there is nothing here but a destination.
    bytes("jrcxz", &D, Long, &[0xE3], NO_MODRM, ImmSize::Cb),
    // The loops, which count `rcx` down and branch while it is not zero, the last two also asking
    // about the zero flag. They have the same single byte of reach. The kernel's
    // `relocate_kernel_64.S` copies pages with one.
    bytes("loop", &D, Long, &[0xE2], NO_MODRM, ImmSize::Cb),
    bytes("loope", &D, Long, &[0xE1], NO_MODRM, ImmSize::Cb),
    bytes("loopz", &D, Long, &[0xE1], NO_MODRM, ImmSize::Cb),
    bytes("loopne", &D, Long, &[0xE0], NO_MODRM, ImmSize::Cb),
    bytes("loopnz", &D, Long, &[0xE0], NO_MODRM, ImmSize::Cb),
    // The same mnemonic through a register, which is a different row for the reason the call above
    // has two: what a row is looked up by is the arguments as well as the name. It is another of
    // the eight that share `0xFF` and sits one place along from the call, and it is sixty four bits
    // without a prefix saying so for the same reason the call is.
    bytes("jmp", &R, Long, &[0xFF], ext(0, 4), NO_IMM),
    // And the same mnemonic through an address, which is the row a jump table wants. A compiler
    // that owns both halves loads the entry and jumps through the register, which is the row above,
    // and a file written by hand writes the load and the jump as one instruction because it can:
    // `jmp *72(%r8,%rsi,8)` in libgmp's `mpn/x86_64/mod_34lsub1.asm` is the table at a fixed offset
    // from a register, indexed by a count, eight bytes to an entry. Same opcode and same three bits
    // as the register form, since what tells the two apart is the addressing byte rather than
    // anything in front of it.
    bytes("jmp", &M, Long, &[0xFF], ext(0, 4), NO_IMM),
    // The two through a register or an address again with `notrack` in front, which is what gcc
    // writes for the jump a switch table ends in when the file is built with `-fcf-protection`.
    bytes("notrack jmp", &R, Untracked, &[0xFF], ext(0, 4), NO_IMM),
    bytes("notrack jmp", &M, Untracked, &[0xFF], ext(0, 4), NO_IMM),
    bytes("notrack call", &R, Untracked, &[0xFF], ext(0, 2), NO_IMM),
    bytes("notrack call", &M, Untracked, &[0xFF], ext(0, 2), NO_IMM),
    // What a prologue and an epilogue are made of. A push and a pop move eight bytes without
    // being told to, so neither carries the prefix that would say so.
    bytes("pushq", &R, Long, &[0x50], plus(0), NO_IMM),
    bytes("popq", &R, Long, &[0x58], plus(0), NO_IMM),
    // The same two moving eight bytes to and from memory rather than a register, which are not the
    // short forms above at all: the push is another of the eight that share `0xFF` and the pop has
    // an opcode nothing else uses. Eight bytes without a prefix saying so, the way the short forms
    // are, and this compiler writes neither because a spill it made has a register in hand.
    bytes("pushq", &M, Long, &[0xFF], ext(0, 6), NO_IMM),
    bytes("popq", &M, Long, &[0x8F], ext(0, 0), NO_IMM),
    // A number pushed, which is eight bytes on the stack however few the number is written in. The
    // byte form is sign extended, so anything from -128 to 127 takes it.
    takes("pushq", &I, Signed8, Long, &[0x6A], NO_MODRM, ImmSize::Ib),
    takes("pushq", &I, Signed32, Long, &[0x68], NO_MODRM, ImmSize::Id),
    // The same two about the flags rather than about a value, which name what they move in the
    // mnemonic and take no operand at all. Eight bytes, since there is no other width of them in
    // long mode. libgmp's `tests/amd64call.asm` pushes the flags and pops them into a register,
    // which is how a program written in C reads a register C has no name for.
    bytes("pushfq", &NO_ARGS, Long, &[0x9C], NO_MODRM, NO_IMM),
    bytes("popfq", &NO_ARGS, Long, &[0x9D], NO_MODRM, NO_IMM),
    // Two bytes pushed and popped, which is the same opcodes behind the `0x66` prefix in either
    // mode. The kernel's `relocate_kernel_64.S` builds a far return frame out of these.
    bytes("pushw", &R, Word, &[0x50], plus(0), NO_IMM),
    bytes("popw", &R, Word, &[0x58], plus(0), NO_IMM),
    bytes("pushw", &M, Word, &[0xFF], ext(0, 6), NO_IMM),
    bytes("popw", &M, Word, &[0x8F], ext(0, 0), NO_IMM),
    takes("pushw", &I, Signed8, Word, &[0x6A], NO_MODRM, ImmSize::Ib),
    takes("pushw", &I, Fits::Word, Word, &[0x68], NO_MODRM, ImmSize::Iw),
    bytes("ret", &NO_ARGS, Long, &[0xC3], NO_MODRM, NO_IMM),
    // The same with a count of bytes to take off the stack after the return address, which is how
    // an i386 function gives back the address its result went through.
    takes("ret", &I, Fits::Word, Long, &[0xC2], NO_MODRM, ImmSize::Iw),
    // The frame taken down in one byte, which is `movq %rbp, %rsp` and `popq %rbp` together and
    // is sixty four bits without a prefix for the reason a pop is.
    bytes("leave", &NO_ARGS, Long, &[0xC9], NO_MODRM, NO_IMM),
    // The barrier. Three bytes with no operands, so the last of them is written as part of the
    // opcode rather than built: `0xF0` is the addressing byte that names no memory and no
    // register, and there is nothing here that could choose a different one.
    bytes("mfence", &NO_ARGS, Long, &[0x0F, 0xAE, 0xF0], NO_MODRM, NO_IMM),
    // The four hints, which are one opcode told apart by the three spare bits of the addressing
    // byte, the way the eight instructions sharing `0xFF` are. The size is `Long` because a row has
    // to name one and there is no prefix to write: the instruction is about a line in the cache and
    // not about however many bytes a later read will take out of it.
    bytes("prefetchnta", &M, Long, &[0x0F, 0x18], ext(0, 0), NO_IMM),
    bytes("prefetcht0", &M, Long, &[0x0F, 0x18], ext(0, 1), NO_IMM),
    bytes("prefetcht1", &M, Long, &[0x0F, 0x18], ext(0, 2), NO_IMM),
    bytes("prefetcht2", &M, Long, &[0x0F, 0x18], ext(0, 3), NO_IMM),
    // The two AMD added, the second of which fetches a line it is about to write. The kernel's
    // `prefetchw()` is the second, and every processor since Broadwell runs it.
    bytes("prefetch", &M, Long, &[0x0F, 0x0D], ext(0, 0), NO_IMM),
    bytes("prefetchw", &M, Long, &[0x0F, 0x0D], ext(0, 1), NO_IMM),
    // The instruction a program stops on. Two bytes and no operands, and what makes it work is
    // that the manual promises this opcode will never be given a meaning, so every processor there
    // is raises the fault for an instruction it does not know rather than doing something.
    bytes("ud2", &NO_ARGS, Long, &[0x0F, 0x0B], NO_MODRM, NO_IMM),
    // The breakpoint, one byte. `-mharden-sls=` puts one after a return and after an indirect
    // jump, where nothing runs it except a processor speculating straight past the branch, and it
    // stops that speculation there.
    bytes("int3", &NO_ARGS, Long, &[0xCC], NO_MODRM, NO_IMM),
    // The landing pad, and four bytes for the same reason the barrier is three: no operands, so
    // the addressing byte at the end of it is part of the opcode. A machine that does not check
    // reads the whole of it as a wider `nop`, which is what makes an object built with it run
    // everywhere rather than only where the check exists.
    bytes("endbr64", &NO_ARGS, Long, &[0xF3, 0x0F, 0x1E, 0xFA], NO_MODRM, NO_IMM),
    // The byte that does nothing, which is the one byte form rather than any of the longer ones.
    // Length is what `-fpatchable-function-entry=` counts, and a patcher writing over the room it
    // asked for wants a whole number of bytes it can start at, so the reserved space is that many
    // one byte instructions and not the shortest sequence that adds up.
    bytes("nop", &NO_ARGS, Long, &[0x90], NO_MODRM, NO_IMM),
    // The spin loop hint, which is the byte above with the repeat prefix in front of it. A machine
    // that has never heard of it decodes the prefix as having nothing to repeat and runs the `nop`,
    // which is why the hint could be added to the instruction set without breaking anything that
    // was already written.
    bytes("pause", &NO_ARGS, Long, &[0xF3, 0x90], NO_MODRM, NO_IMM),
    // What the processor is asked about itself. No arguments in the encoding for the reason there
    // are none in the text: every register it touches is named by the instruction rather than by
    // anything written beside it, so there is no addressing byte and nothing to put in one.
    bytes("cpuid", &NO_ARGS, Long, &[0x0F, 0xA2], NO_MODRM, NO_IMM),
    // Which parts of the register state the operating system saves on a switch, read from the
    // control register `%ecx` names into `%edx:%eax`. A program asks before it uses AVX or AVX-512,
    // since a processor that has the registers is no use when the kernel does not keep them. The
    // three bytes are one opcode with the addressing byte fixed, which is why there is no pair.
    bytes("xgetbv", &NO_ARGS, Long, &[0x0F, 0x01, 0xD0], NO_MODRM, NO_IMM),
    // The system instructions, which nothing this compiler generates and every kernel writes by
    // hand, in `.S` files and in `asm` statements. The bytes are the manual's and every one of them
    // is pinned in the tests below against what gas and llvm-mc write for the same line.
    //
    // First the ones with no operand, most of which are a two or three byte opcode whose last byte
    // is an addressing byte fixed by the manual, the way `mfence` is. The ones with a mandatory
    // prefix carry it in the opcode for the same reason `endbr64` does: there is no REX byte for it
    // to have to come in front of.
    bytes("clts", &NO_ARGS, Long, &[0x0F, 0x06], NO_MODRM, NO_IMM),
    bytes("invd", &NO_ARGS, Long, &[0x0F, 0x08], NO_MODRM, NO_IMM),
    bytes("wbinvd", &NO_ARGS, Long, &[0x0F, 0x09], NO_MODRM, NO_IMM),
    bytes("wbnoinvd", &NO_ARGS, Long, &[0xF3, 0x0F, 0x09], NO_MODRM, NO_IMM),
    bytes("wrmsr", &NO_ARGS, Long, &[0x0F, 0x30], NO_MODRM, NO_IMM),
    bytes("rdtsc", &NO_ARGS, Long, &[0x0F, 0x31], NO_MODRM, NO_IMM),
    bytes("rdmsr", &NO_ARGS, Long, &[0x0F, 0x32], NO_MODRM, NO_IMM),
    bytes("rdpmc", &NO_ARGS, Long, &[0x0F, 0x33], NO_MODRM, NO_IMM),
    bytes("wrmsrns", &NO_ARGS, Long, &[0x0F, 0x01, 0xC6], NO_MODRM, NO_IMM),
    bytes("rdtscp", &NO_ARGS, Long, &[0x0F, 0x01, 0xF9], NO_MODRM, NO_IMM),
    bytes("swapgs", &NO_ARGS, Long, &[0x0F, 0x01, 0xF8], NO_MODRM, NO_IMM),
    bytes("syscall", &NO_ARGS, Long, &[0x0F, 0x05], NO_MODRM, NO_IMM),
    bytes("sysenter", &NO_ARGS, Long, &[0x0F, 0x34], NO_MODRM, NO_IMM),
    // The returns from a system call and from an interrupt, which go back to thirty two bit code
    // without `REX.W` and to sixty four bit code with it. The name with no letter is the thirty two
    // bit one, which is what gas takes it for.
    bytes("sysret", &NO_ARGS, Long, &[0x0F, 0x07], NO_MODRM, NO_IMM),
    bytes("sysretl", &NO_ARGS, Long, &[0x0F, 0x07], NO_MODRM, NO_IMM),
    bytes("sysretq", &NO_ARGS, Quad, &[0x0F, 0x07], NO_MODRM, NO_IMM),
    bytes("sysexit", &NO_ARGS, Long, &[0x0F, 0x35], NO_MODRM, NO_IMM),
    bytes("sysexitl", &NO_ARGS, Long, &[0x0F, 0x35], NO_MODRM, NO_IMM),
    bytes("sysexitq", &NO_ARGS, Quad, &[0x0F, 0x35], NO_MODRM, NO_IMM),
    bytes("iret", &NO_ARGS, Long, &[0xCF], NO_MODRM, NO_IMM),
    bytes("iretw", &NO_ARGS, Word, &[0xCF], NO_MODRM, NO_IMM),
    bytes("iretl", &NO_ARGS, Long, &[0xCF], NO_MODRM, NO_IMM),
    bytes("iretq", &NO_ARGS, Quad, &[0xCF], NO_MODRM, NO_IMM),
    // The far return, which pops a segment as well as an address, and the form that also drops
    // that many bytes of arguments.
    bytes("lret", &NO_ARGS, Long, &[0xCB], NO_MODRM, NO_IMM),
    bytes("lretl", &NO_ARGS, Long, &[0xCB], NO_MODRM, NO_IMM),
    bytes("lretq", &NO_ARGS, Quad, &[0xCB], NO_MODRM, NO_IMM),
    takes("lret", &I, Fits::Word, Long, &[0xCA], NO_MODRM, ImmSize::Iw),
    takes("lretl", &I, Fits::Word, Long, &[0xCA], NO_MODRM, ImmSize::Iw),
    takes("lretq", &I, Fits::Word, Quad, &[0xCA], NO_MODRM, ImmSize::Iw),
    // The far jump and call through memory, which read a segment and an address from it. Four
    // bytes of address without `REX.W` and eight with it, and gas takes the name with no letter
    // for the first.
    bytes("ljmp", &M, Long, &[0xFF], ext(0, 5), NO_IMM),
    bytes("ljmpl", &M, Long, &[0xFF], ext(0, 5), NO_IMM),
    bytes("ljmpq", &M, Quad, &[0xFF], ext(0, 5), NO_IMM),
    bytes("lcall", &M, Long, &[0xFF], ext(0, 3), NO_IMM),
    bytes("lcalll", &M, Long, &[0xFF], ext(0, 3), NO_IMM),
    bytes("lcallq", &M, Quad, &[0xFF], ext(0, 3), NO_IMM),
    // Interrupts and the flags that mask them. `int $3` is two bytes rather than the one byte
    // `int3` further up, which is what gas writes for it and what a debugger looking for either tells apart.
    bytes("cli", &NO_ARGS, Long, &[0xFA], NO_MODRM, NO_IMM),
    bytes("sti", &NO_ARGS, Long, &[0xFB], NO_MODRM, NO_IMM),
    bytes("hlt", &NO_ARGS, Long, &[0xF4], NO_MODRM, NO_IMM),
    bytes("int1", &NO_ARGS, Long, &[0xF1], NO_MODRM, NO_IMM),
    bytes("icebp", &NO_ARGS, Long, &[0xF1], NO_MODRM, NO_IMM),
    takes("int", &I, Fits::Byte, Long, &[0xCD], NO_MODRM, ImmSize::Ib),
    bytes("cld", &NO_ARGS, Long, &[0xFC], NO_MODRM, NO_IMM),
    bytes("std", &NO_ARGS, Long, &[0xFD], NO_MODRM, NO_IMM),
    bytes("lahf", &NO_ARGS, Long, &[0x9F], NO_MODRM, NO_IMM),
    bytes("sahf", &NO_ARGS, Long, &[0x9E], NO_MODRM, NO_IMM),
    bytes("rsm", &NO_ARGS, Long, &[0x0F, 0xAA], NO_MODRM, NO_IMM),
    // SMAP, and the protection keys a user page may carry.
    bytes("clac", &NO_ARGS, Long, &[0x0F, 0x01, 0xCA], NO_MODRM, NO_IMM),
    bytes("stac", &NO_ARGS, Long, &[0x0F, 0x01, 0xCB], NO_MODRM, NO_IMM),
    bytes("rdpkru", &NO_ARGS, Long, &[0x0F, 0x01, 0xEE], NO_MODRM, NO_IMM),
    bytes("wrpkru", &NO_ARGS, Long, &[0x0F, 0x01, 0xEF], NO_MODRM, NO_IMM),
    // Waiting for a store to a line. The registers are fixed, `rax`, `ecx` and `edx` for the first
    // and `eax` and `ecx` for the second, so a file may name them or leave them off and the bytes
    // are the same. Which registers were named is checked where the line is read.
    bytes("monitor", &NO_ARGS, Long, &[0x0F, 0x01, 0xC8], NO_MODRM, NO_IMM),
    bytes("monitor", &RRR, Long, &[0x0F, 0x01, 0xC8], NO_MODRM, NO_IMM),
    bytes("mwait", &NO_ARGS, Long, &[0x0F, 0x01, 0xC9], NO_MODRM, NO_IMM),
    bytes("mwait", &RR, Long, &[0x0F, 0x01, 0xC9], NO_MODRM, NO_IMM),
    bytes("monitorx", &NO_ARGS, Long, &[0x0F, 0x01, 0xFA], NO_MODRM, NO_IMM),
    bytes("monitorx", &RRR, Long, &[0x0F, 0x01, 0xFA], NO_MODRM, NO_IMM),
    bytes("mwaitx", &NO_ARGS, Long, &[0x0F, 0x01, 0xFB], NO_MODRM, NO_IMM),
    bytes("mwaitx", &RRR, Long, &[0x0F, 0x01, 0xFB], NO_MODRM, NO_IMM),
    // The other two barriers beside `mfence`, and the one that waits for everything in flight.
    bytes("lfence", &NO_ARGS, Long, &[0x0F, 0xAE, 0xE8], NO_MODRM, NO_IMM),
    bytes("sfence", &NO_ARGS, Long, &[0x0F, 0xAE, 0xF8], NO_MODRM, NO_IMM),
    bytes("serialize", &NO_ARGS, Long, &[0x0F, 0x01, 0xE8], NO_MODRM, NO_IMM),
    bytes("endbr32", &NO_ARGS, Long, &[0xF3, 0x0F, 0x1E, 0xFB], NO_MODRM, NO_IMM),
    bytes("xsetbv", &NO_ARGS, Long, &[0x0F, 0x01, 0xD1], NO_MODRM, NO_IMM),
    bytes("xend", &NO_ARGS, Long, &[0x0F, 0x01, 0xD5], NO_MODRM, NO_IMM),
    bytes("xtest", &NO_ARGS, Long, &[0x0F, 0x01, 0xD6], NO_MODRM, NO_IMM),
    takes("xabort", &I, Fits::Byte, Long, &[0xC6, 0xF8], NO_MODRM, ImmSize::Ib),
    // The x87 and MMX state a kernel clears or saves by hand.
    bytes("fnclex", &NO_ARGS, Long, &[0xDB, 0xE2], NO_MODRM, NO_IMM),
    bytes("fwait", &NO_ARGS, Long, &[0x9B], NO_MODRM, NO_IMM),
    bytes("wait", &NO_ARGS, Long, &[0x9B], NO_MODRM, NO_IMM),
    bytes("emms", &NO_ARGS, Long, &[0x0F, 0x77], NO_MODRM, NO_IMM),
    bytes("fnsave", &M, Long, &[0xDD], ext(0, 6), NO_IMM),
    waits("fsave", &M, Long, &[0xDD], ext(0, 6)),
    bytes("frstor", &M, Long, &[0xDD], ext(0, 4), NO_IMM),
    bytes("fldenv", &M, Long, &[0xD9], ext(0, 4), NO_IMM),
    // VMX. The two that move a field of the current structure are always sixty four bits in long
    // mode, with no `REX.W`, and gas spells them with or without the `q`.
    bytes("vmcall", &NO_ARGS, Long, &[0x0F, 0x01, 0xC1], NO_MODRM, NO_IMM),
    bytes("vmlaunch", &NO_ARGS, Long, &[0x0F, 0x01, 0xC2], NO_MODRM, NO_IMM),
    bytes("vmresume", &NO_ARGS, Long, &[0x0F, 0x01, 0xC3], NO_MODRM, NO_IMM),
    bytes("vmxoff", &NO_ARGS, Long, &[0x0F, 0x01, 0xC4], NO_MODRM, NO_IMM),
    bytes("vmfunc", &NO_ARGS, Long, &[0x0F, 0x01, 0xD4], NO_MODRM, NO_IMM),
    bytes("vmxon", &M, Single, &[0x0F, 0xC7], ext(0, 6), NO_IMM),
    bytes("vmclear", &M, Word, &[0x0F, 0xC7], ext(0, 6), NO_IMM),
    bytes("vmptrld", &M, Long, &[0x0F, 0xC7], ext(0, 6), NO_IMM),
    bytes("vmptrst", &M, Long, &[0x0F, 0xC7], ext(0, 7), NO_IMM),
    bytes("vmreadq", &RR, Long, &[0x0F, 0x78], pair(1, 0), NO_IMM),
    bytes("vmreadq", &RM, Long, &[0x0F, 0x78], pair(1, 0), NO_IMM),
    bytes("vmwriteq", &RR, Long, &[0x0F, 0x79], pair(0, 1), NO_IMM),
    bytes("vmwriteq", &MR, Long, &[0x0F, 0x79], pair(0, 1), NO_IMM),
    bytes("invept", &MR, Word, &[0x0F, 0x38, 0x80], pair(0, 1), NO_IMM),
    bytes("invvpid", &MR, Word, &[0x0F, 0x38, 0x81], pair(0, 1), NO_IMM),
    // SVM. The register forms name `rax`, and `invlpga` names `rax` and `ecx`, and `skinit` names
    // `eax`, all fixed, the way `monitor` does.
    bytes("vmmcall", &NO_ARGS, Long, &[0x0F, 0x01, 0xD9], NO_MODRM, NO_IMM),
    bytes("vmgexit", &NO_ARGS, Long, &[0xF3, 0x0F, 0x01, 0xD9], NO_MODRM, NO_IMM),
    bytes("vmrun", &NO_ARGS, Long, &[0x0F, 0x01, 0xD8], NO_MODRM, NO_IMM),
    bytes("vmrun", &R, Long, &[0x0F, 0x01, 0xD8], NO_MODRM, NO_IMM),
    bytes("vmload", &NO_ARGS, Long, &[0x0F, 0x01, 0xDA], NO_MODRM, NO_IMM),
    bytes("vmload", &R, Long, &[0x0F, 0x01, 0xDA], NO_MODRM, NO_IMM),
    bytes("vmsave", &NO_ARGS, Long, &[0x0F, 0x01, 0xDB], NO_MODRM, NO_IMM),
    bytes("vmsave", &R, Long, &[0x0F, 0x01, 0xDB], NO_MODRM, NO_IMM),
    bytes("stgi", &NO_ARGS, Long, &[0x0F, 0x01, 0xDC], NO_MODRM, NO_IMM),
    bytes("clgi", &NO_ARGS, Long, &[0x0F, 0x01, 0xDD], NO_MODRM, NO_IMM),
    bytes("skinit", &NO_ARGS, Long, &[0x0F, 0x01, 0xDE], NO_MODRM, NO_IMM),
    bytes("skinit", &R, Long, &[0x0F, 0x01, 0xDE], NO_MODRM, NO_IMM),
    bytes("invlpga", &NO_ARGS, Long, &[0x0F, 0x01, 0xDF], NO_MODRM, NO_IMM),
    bytes("invlpga", &RR, Long, &[0x0F, 0x01, 0xDF], NO_MODRM, NO_IMM),
    // SEV-SNP, TDX, SGX and the platform configuration, which are fixed opcodes the same way.
    bytes("pvalidate", &NO_ARGS, Long, &[0xF2, 0x0F, 0x01, 0xFF], NO_MODRM, NO_IMM),
    bytes("rmpadjust", &NO_ARGS, Long, &[0xF3, 0x0F, 0x01, 0xFE], NO_MODRM, NO_IMM),
    bytes("rmpupdate", &NO_ARGS, Long, &[0xF2, 0x0F, 0x01, 0xFE], NO_MODRM, NO_IMM),
    bytes("psmash", &NO_ARGS, Long, &[0xF3, 0x0F, 0x01, 0xFF], NO_MODRM, NO_IMM),
    bytes("tdcall", &NO_ARGS, Long, &[0x66, 0x0F, 0x01, 0xCC], NO_MODRM, NO_IMM),
    bytes("seamret", &NO_ARGS, Long, &[0x66, 0x0F, 0x01, 0xCD], NO_MODRM, NO_IMM),
    bytes("seamops", &NO_ARGS, Long, &[0x66, 0x0F, 0x01, 0xCE], NO_MODRM, NO_IMM),
    bytes("seamcall", &NO_ARGS, Long, &[0x66, 0x0F, 0x01, 0xCF], NO_MODRM, NO_IMM),
    bytes("enclv", &NO_ARGS, Long, &[0x0F, 0x01, 0xC0], NO_MODRM, NO_IMM),
    bytes("pconfig", &NO_ARGS, Long, &[0x0F, 0x01, 0xC5], NO_MODRM, NO_IMM),
    bytes("encls", &NO_ARGS, Long, &[0x0F, 0x01, 0xCF], NO_MODRM, NO_IMM),
    bytes("enclu", &NO_ARGS, Long, &[0x0F, 0x01, 0xD7], NO_MODRM, NO_IMM),
    // FRED's two returns, from 6.9 on.
    bytes("eretu", &NO_ARGS, Long, &[0xF3, 0x0F, 0x01, 0xCA], NO_MODRM, NO_IMM),
    bytes("erets", &NO_ARGS, Long, &[0xF2, 0x0F, 0x01, 0xCA], NO_MODRM, NO_IMM),
    // The descriptor tables and the task register. The four table instructions read or write ten
    // bytes of memory in long mode whatever the letter says, and gas takes them with a `q` or
    // without. The selector ones read a word, from a register or from memory, and write no prefix
    // for it. Storing a selector into a register is the one that has a width, since it writes the
    // whole register, so those are named by the letter the register works out to.
    bytes("sgdt", &M, Long, &[0x0F, 0x01], ext(0, 0), NO_IMM),
    bytes("sgdtq", &M, Long, &[0x0F, 0x01], ext(0, 0), NO_IMM),
    bytes("sidt", &M, Long, &[0x0F, 0x01], ext(0, 1), NO_IMM),
    bytes("sidtq", &M, Long, &[0x0F, 0x01], ext(0, 1), NO_IMM),
    bytes("lgdt", &M, Long, &[0x0F, 0x01], ext(0, 2), NO_IMM),
    bytes("lgdtq", &M, Long, &[0x0F, 0x01], ext(0, 2), NO_IMM),
    bytes("lidt", &M, Long, &[0x0F, 0x01], ext(0, 3), NO_IMM),
    bytes("lidtq", &M, Long, &[0x0F, 0x01], ext(0, 3), NO_IMM),
    bytes("sldt", &M, Long, &[0x0F, 0x00], ext(0, 0), NO_IMM),
    bytes("sldtw", &R, Word, &[0x0F, 0x00], ext(0, 0), NO_IMM),
    bytes("sldtl", &R, Long, &[0x0F, 0x00], ext(0, 0), NO_IMM),
    bytes("sldtq", &R, Quad, &[0x0F, 0x00], ext(0, 0), NO_IMM),
    bytes("str", &M, Long, &[0x0F, 0x00], ext(0, 1), NO_IMM),
    bytes("strw", &R, Word, &[0x0F, 0x00], ext(0, 1), NO_IMM),
    bytes("strl", &R, Long, &[0x0F, 0x00], ext(0, 1), NO_IMM),
    bytes("strq", &R, Quad, &[0x0F, 0x00], ext(0, 1), NO_IMM),
    bytes("lldt", &R, Long, &[0x0F, 0x00], ext(0, 2), NO_IMM),
    bytes("lldt", &M, Long, &[0x0F, 0x00], ext(0, 2), NO_IMM),
    bytes("ltr", &R, Long, &[0x0F, 0x00], ext(0, 3), NO_IMM),
    bytes("ltr", &M, Long, &[0x0F, 0x00], ext(0, 3), NO_IMM),
    bytes("verr", &R, Long, &[0x0F, 0x00], ext(0, 4), NO_IMM),
    bytes("verr", &M, Long, &[0x0F, 0x00], ext(0, 4), NO_IMM),
    bytes("verw", &R, Long, &[0x0F, 0x00], ext(0, 5), NO_IMM),
    bytes("verw", &M, Long, &[0x0F, 0x00], ext(0, 5), NO_IMM),
    bytes("smsw", &M, Long, &[0x0F, 0x01], ext(0, 4), NO_IMM),
    bytes("smsww", &R, Word, &[0x0F, 0x01], ext(0, 4), NO_IMM),
    bytes("smswl", &R, Long, &[0x0F, 0x01], ext(0, 4), NO_IMM),
    bytes("smswq", &R, Quad, &[0x0F, 0x01], ext(0, 4), NO_IMM),
    bytes("lmsw", &R, Long, &[0x0F, 0x01], ext(0, 6), NO_IMM),
    bytes("lmsw", &M, Long, &[0x0F, 0x01], ext(0, 6), NO_IMM),
    // The limit and the access rights of a segment, which the vDSO reads the processor number out
    // of.
    bytes("larw", &RR, Word, &[0x0F, 0x02], pair(0, 1), NO_IMM),
    bytes("larw", &MR, Word, &[0x0F, 0x02], pair(0, 1), NO_IMM),
    bytes("larl", &RR, Long, &[0x0F, 0x02], pair(0, 1), NO_IMM),
    bytes("larl", &MR, Long, &[0x0F, 0x02], pair(0, 1), NO_IMM),
    bytes("larq", &RR, Quad, &[0x0F, 0x02], pair(0, 1), NO_IMM),
    bytes("larq", &MR, Quad, &[0x0F, 0x02], pair(0, 1), NO_IMM),
    bytes("lslw", &RR, Word, &[0x0F, 0x03], pair(0, 1), NO_IMM),
    bytes("lslw", &MR, Word, &[0x0F, 0x03], pair(0, 1), NO_IMM),
    bytes("lsll", &RR, Long, &[0x0F, 0x03], pair(0, 1), NO_IMM),
    bytes("lsll", &MR, Long, &[0x0F, 0x03], pair(0, 1), NO_IMM),
    bytes("lslq", &RR, Quad, &[0x0F, 0x03], pair(0, 1), NO_IMM),
    bytes("lslq", &MR, Quad, &[0x0F, 0x03], pair(0, 1), NO_IMM),
    // The control and debug registers, moved to and from a general purpose one. Always sixty four
    // bits in long mode and never with `REX.W`, and the special register is the one beside the
    // addressing byte, so `REX.R` is what reaches `%cr8`.
    bytes("movq", &CONTROL_R, Long, &[0x0F, 0x20], pair(1, 0), NO_IMM),
    bytes("movq", &R_CONTROL, Long, &[0x0F, 0x22], pair(0, 1), NO_IMM),
    bytes("movq", &DEBUG_R, Long, &[0x0F, 0x21], pair(1, 0), NO_IMM),
    bytes("movq", &R_DEBUG, Long, &[0x0F, 0x23], pair(0, 1), NO_IMM),
    // The same in thirty two bit mode, where the register is thirty two bits and so is the letter.
    bytes("movl", &CONTROL_R, Long, &[0x0F, 0x20], pair(1, 0), NO_IMM),
    bytes("movl", &R_CONTROL, Long, &[0x0F, 0x22], pair(0, 1), NO_IMM),
    bytes("movl", &DEBUG_R, Long, &[0x0F, 0x21], pair(1, 0), NO_IMM),
    bytes("movl", &R_DEBUG, Long, &[0x0F, 0x23], pair(0, 1), NO_IMM),
    // A segment register moved to and from a general purpose one or memory. Reading one into a
    // register writes as much of the register as the letter says, so that direction has a prefix
    // per width. Loading one reads a word whatever the letter is, and gas writes no prefix for a
    // `movw` into one, nor for a store of one to memory. A sixty four bit register carries
    // `REX.W` in both directions, which changes nothing about what is loaded and is what the
    // other assemblers write for it.
    bytes("movw", &SEG_R, Word, &[0x8C], pair(1, 0), NO_IMM),
    bytes("movl", &SEG_R, Long, &[0x8C], pair(1, 0), NO_IMM),
    bytes("movq", &SEG_R, Quad, &[0x8C], pair(1, 0), NO_IMM),
    bytes("movw", &R_SEG, Long, &[0x8E], pair(0, 1), NO_IMM),
    bytes("movl", &R_SEG, Long, &[0x8E], pair(0, 1), NO_IMM),
    bytes("movq", &R_SEG, Quad, &[0x8E], pair(0, 1), NO_IMM),
    bytes("mov", &SEG_M, Long, &[0x8C], pair(1, 0), NO_IMM),
    bytes("movw", &SEG_M, Long, &[0x8C], pair(1, 0), NO_IMM),
    bytes("mov", &M_SEG, Long, &[0x8E], pair(0, 1), NO_IMM),
    bytes("movw", &M_SEG, Long, &[0x8E], pair(0, 1), NO_IMM),
    // The only two segment registers long mode can push and pop, each an opcode of its own. They
    // are looked up under a name with the register in it, since which register it is is the whole
    // of which opcode it is and an argument cannot say that to a lookup by kind.
    bytes("pushq %fs", &NO_ARGS, Long, &[0x0F, 0xA0], NO_MODRM, NO_IMM),
    bytes("popq %fs", &NO_ARGS, Long, &[0x0F, 0xA1], NO_MODRM, NO_IMM),
    bytes("pushq %gs", &NO_ARGS, Long, &[0x0F, 0xA8], NO_MODRM, NO_IMM),
    bytes("popq %gs", &NO_ARGS, Long, &[0x0F, 0xA9], NO_MODRM, NO_IMM),
    // The base of `%fs` and `%gs` read and written without an MSR, at either width.
    bytes("rdfsbasel", &R, Single, &[0x0F, 0xAE], ext(0, 0), NO_IMM),
    bytes("rdfsbaseq", &R, SingleQuad, &[0x0F, 0xAE], ext(0, 0), NO_IMM),
    bytes("rdgsbasel", &R, Single, &[0x0F, 0xAE], ext(0, 1), NO_IMM),
    bytes("rdgsbaseq", &R, SingleQuad, &[0x0F, 0xAE], ext(0, 1), NO_IMM),
    bytes("wrfsbasel", &R, Single, &[0x0F, 0xAE], ext(0, 2), NO_IMM),
    bytes("wrfsbaseq", &R, SingleQuad, &[0x0F, 0xAE], ext(0, 2), NO_IMM),
    bytes("wrgsbasel", &R, Single, &[0x0F, 0xAE], ext(0, 3), NO_IMM),
    bytes("wrgsbaseq", &R, SingleQuad, &[0x0F, 0xAE], ext(0, 3), NO_IMM),
    // Paging and the caches. `invpcid` names its type in a register that is sixty four bits in
    // long mode without `REX.W`, and the descriptor in memory.
    bytes("invlpg", &M, Long, &[0x0F, 0x01], ext(0, 7), NO_IMM),
    bytes("invpcid", &MR, Word, &[0x0F, 0x38, 0x82], pair(0, 1), NO_IMM),
    bytes("clflush", &M, Long, &[0x0F, 0xAE], ext(0, 7), NO_IMM),
    bytes("clflushopt", &M, Word, &[0x0F, 0xAE], ext(0, 7), NO_IMM),
    bytes("clwb", &M, Word, &[0x0F, 0xAE], ext(0, 6), NO_IMM),
    // The extended state, saved and restored. The `64` forms are the same opcode with `REX.W`,
    // which is what makes the saved instruction pointers eight bytes wide, and `fxsaveq` is gas's
    // other name for `fxsave64`.
    bytes("fxsave", &M, Long, &[0x0F, 0xAE], ext(0, 0), NO_IMM),
    bytes("fxsave64", &M, Quad, &[0x0F, 0xAE], ext(0, 0), NO_IMM),
    bytes("fxsaveq", &M, Quad, &[0x0F, 0xAE], ext(0, 0), NO_IMM),
    bytes("fxrstor", &M, Long, &[0x0F, 0xAE], ext(0, 1), NO_IMM),
    bytes("fxrstor64", &M, Quad, &[0x0F, 0xAE], ext(0, 1), NO_IMM),
    bytes("fxrstorq", &M, Quad, &[0x0F, 0xAE], ext(0, 1), NO_IMM),
    bytes("ldmxcsr", &M, Long, &[0x0F, 0xAE], ext(0, 2), NO_IMM),
    bytes("stmxcsr", &M, Long, &[0x0F, 0xAE], ext(0, 3), NO_IMM),
    bytes("xsave", &M, Long, &[0x0F, 0xAE], ext(0, 4), NO_IMM),
    bytes("xsave64", &M, Quad, &[0x0F, 0xAE], ext(0, 4), NO_IMM),
    bytes("xrstor", &M, Long, &[0x0F, 0xAE], ext(0, 5), NO_IMM),
    bytes("xrstor64", &M, Quad, &[0x0F, 0xAE], ext(0, 5), NO_IMM),
    bytes("xsaveopt", &M, Long, &[0x0F, 0xAE], ext(0, 6), NO_IMM),
    bytes("xsaveopt64", &M, Quad, &[0x0F, 0xAE], ext(0, 6), NO_IMM),
    bytes("xrstors", &M, Long, &[0x0F, 0xC7], ext(0, 3), NO_IMM),
    bytes("xrstors64", &M, Quad, &[0x0F, 0xC7], ext(0, 3), NO_IMM),
    bytes("xsavec", &M, Long, &[0x0F, 0xC7], ext(0, 4), NO_IMM),
    bytes("xsavec64", &M, Quad, &[0x0F, 0xC7], ext(0, 4), NO_IMM),
    bytes("xsaves", &M, Long, &[0x0F, 0xC7], ext(0, 5), NO_IMM),
    bytes("xsaves64", &M, Quad, &[0x0F, 0xC7], ext(0, 5), NO_IMM),
    // Random numbers from the processor, and its own number.
    bytes("rdrandw", &R, Word, &[0x0F, 0xC7], ext(0, 6), NO_IMM),
    bytes("rdrandl", &R, Long, &[0x0F, 0xC7], ext(0, 6), NO_IMM),
    bytes("rdrandq", &R, Quad, &[0x0F, 0xC7], ext(0, 6), NO_IMM),
    bytes("rdseedw", &R, Word, &[0x0F, 0xC7], ext(0, 7), NO_IMM),
    bytes("rdseedl", &R, Long, &[0x0F, 0xC7], ext(0, 7), NO_IMM),
    bytes("rdseedq", &R, Quad, &[0x0F, 0xC7], ext(0, 7), NO_IMM),
    bytes("rdpid", &R, Single, &[0x0F, 0xC7], ext(0, 7), NO_IMM),
    // The instruction that is undefined on purpose and carries an addressing byte, which is what
    // a kernel's warnings are made of when it wants to say which one it was.
    bytes("ud1l", &RR, Long, &[0x0F, 0xB9], pair(0, 1), NO_IMM),
    bytes("ud1l", &MR, Long, &[0x0F, 0xB9], pair(0, 1), NO_IMM),
    bytes("ud1q", &RR, Quad, &[0x0F, 0xB9], pair(0, 1), NO_IMM),
    bytes("ud1q", &MR, Quad, &[0x0F, 0xB9], pair(0, 1), NO_IMM),
    // Stores of sixty four bytes in one go to a device, and direct stores. The destination is an
    // address held in a register, which is sixty four bits in long mode without `REX.W`.
    bytes("movdir64b", &MR, Word, &[0x0F, 0x38, 0xF8], pair(0, 1), NO_IMM),
    bytes("enqcmds", &MR, Single, &[0x0F, 0x38, 0xF8], pair(0, 1), NO_IMM),
    bytes("enqcmd", &MR, Double, &[0x0F, 0x38, 0xF8], pair(0, 1), NO_IMM),
    bytes("movdiril", &RM, Long, &[0x0F, 0x38, 0xF9], pair(1, 0), NO_IMM),
    bytes("movdiriq", &RM, Quad, &[0x0F, 0x38, 0xF9], pair(1, 0), NO_IMM),
    // The shadow stack, which gas names with `d` and `q` rather than `l` and `q`.
    bytes("wrssd", &RM, Long, &[0x0F, 0x38, 0xF6], pair(1, 0), NO_IMM),
    bytes("wrssq", &RM, Quad, &[0x0F, 0x38, 0xF6], pair(1, 0), NO_IMM),
    bytes("wrussd", &RM, Word, &[0x0F, 0x38, 0xF5], pair(1, 0), NO_IMM),
    bytes("wrussq", &RM, WordQuad, &[0x0F, 0x38, 0xF5], pair(1, 0), NO_IMM),
    bytes("rdsspd", &R, Single, &[0x0F, 0x1E], ext(0, 1), NO_IMM),
    bytes("rdsspq", &R, SingleQuad, &[0x0F, 0x1E], ext(0, 1), NO_IMM),
    bytes("incsspd", &R, Single, &[0x0F, 0xAE], ext(0, 5), NO_IMM),
    bytes("incsspq", &R, SingleQuad, &[0x0F, 0xAE], ext(0, 5), NO_IMM),
    bytes("rstorssp", &M, Single, &[0x0F, 0x01], ext(0, 5), NO_IMM),
    bytes("clrssbsy", &M, Single, &[0x0F, 0xAE], ext(0, 6), NO_IMM),
    bytes("saveprevssp", &NO_ARGS, Long, &[0xF3, 0x0F, 0x01, 0xEA], NO_MODRM, NO_IMM),
    bytes("setssbsy", &NO_ARGS, Long, &[0xF3, 0x0F, 0x01, 0xE8], NO_MODRM, NO_IMM),
    // Waiting for a while or for a store, from user space.
    bytes("tpause", &R, Word, &[0x0F, 0xAE], ext(0, 6), NO_IMM),
    bytes("umwait", &R, Double, &[0x0F, 0xAE], ext(0, 6), NO_IMM),
    bytes("umonitor", &R, Single, &[0x0F, 0xAE], ext(0, 6), NO_IMM),
    // Port I/O. The port is `dx` or a byte the instruction carries and the value is in the
    // accumulator, both fixed, so the registers are checked where the line is read and write
    // nothing here. The word forms carry the operand size prefix and the long ones do not.
    bytes("inb", &RR, Long, &[0xEC], NO_MODRM, NO_IMM),
    bytes("inw", &RR, Word, &[0xED], NO_MODRM, NO_IMM),
    bytes("inl", &RR, Long, &[0xED], NO_MODRM, NO_IMM),
    takes("inb", &IR, Fits::Byte, Long, &[0xE4], NO_MODRM, ImmSize::Ib),
    takes("inw", &IR, Fits::Byte, Word, &[0xE5], NO_MODRM, ImmSize::Ib),
    takes("inl", &IR, Fits::Byte, Long, &[0xE5], NO_MODRM, ImmSize::Ib),
    bytes("outb", &RR, Long, &[0xEE], NO_MODRM, NO_IMM),
    bytes("outw", &RR, Word, &[0xEF], NO_MODRM, NO_IMM),
    bytes("outl", &RR, Long, &[0xEF], NO_MODRM, NO_IMM),
    takes("outb", &RI, Fits::Byte, Long, &[0xE6], NO_MODRM, ImmSize::Ib),
    takes("outw", &RI, Fits::Byte, Word, &[0xE7], NO_MODRM, ImmSize::Ib),
    takes("outl", &RI, Fits::Byte, Long, &[0xE7], NO_MODRM, ImmSize::Ib),
    // The string forms, alone and repeated, with the repeat prefix behind the operand size one
    // the way the other string instructions have it.
    bytes("insb", &NO_ARGS, Byte, &[0x6C], NO_MODRM, NO_IMM),
    bytes("insw", &NO_ARGS, Word, &[0x6D], NO_MODRM, NO_IMM),
    bytes("insl", &NO_ARGS, Long, &[0x6D], NO_MODRM, NO_IMM),
    bytes("outsb", &NO_ARGS, Byte, &[0x6E], NO_MODRM, NO_IMM),
    bytes("outsw", &NO_ARGS, Word, &[0x6F], NO_MODRM, NO_IMM),
    bytes("outsl", &NO_ARGS, Long, &[0x6F], NO_MODRM, NO_IMM),
    bytes("rep insb", &NO_ARGS, Single, &[0x6C], NO_MODRM, NO_IMM),
    bytes("rep insw", &NO_ARGS, Word, &[0xF3, 0x6D], NO_MODRM, NO_IMM),
    bytes("rep insl", &NO_ARGS, Single, &[0x6D], NO_MODRM, NO_IMM),
    bytes("rep outsb", &NO_ARGS, Single, &[0x6E], NO_MODRM, NO_IMM),
    bytes("rep outsw", &NO_ARGS, Word, &[0xF3, 0x6F], NO_MODRM, NO_IMM),
    bytes("rep outsl", &NO_ARGS, Single, &[0x6F], NO_MODRM, NO_IMM),
    bytes("rep lodsb", &NO_ARGS, Single, &[0xAC], NO_MODRM, NO_IMM),
    bytes("rep lodsw", &NO_ARGS, Word, &[0xF3, 0xAD], NO_MODRM, NO_IMM),
    bytes("rep lodsl", &NO_ARGS, Single, &[0xAD], NO_MODRM, NO_IMM),
    bytes("rep lodsq", &NO_ARGS, SingleQuad, &[0xAD], NO_MODRM, NO_IMM),
    // The other prefixes, each a row of its own for the reason `lock` is one, so that a file may
    // write one on a line by itself. `notrack` is the byte `ds` is. gcc writes `cs` on its own in
    // front of a call or jump to a retpoline thunk through `r8` to `r15` under
    // `-mindirect-branch-cs-prefix`, which makes it six bytes, the length the kernel needs to write
    // `lfence; call *%r11` over it in place.
    bytes("es", &NO_ARGS, Long, &[0x26], NO_MODRM, NO_IMM),
    bytes("cs", &NO_ARGS, Long, &[0x2E], NO_MODRM, NO_IMM),
    bytes("ss", &NO_ARGS, Long, &[0x36], NO_MODRM, NO_IMM),
    bytes("ds", &NO_ARGS, Long, &[0x3E], NO_MODRM, NO_IMM),
    bytes("notrack", &NO_ARGS, Long, &[0x3E], NO_MODRM, NO_IMM),
    bytes("fs", &NO_ARGS, Long, &[0x64], NO_MODRM, NO_IMM),
    bytes("gs", &NO_ARGS, Long, &[0x65], NO_MODRM, NO_IMM),
    bytes("data16", &NO_ARGS, Long, &[0x66], NO_MODRM, NO_IMM),
    bytes("addr32", &NO_ARGS, Long, &[0x67], NO_MODRM, NO_IMM),
    bytes("rex64", &NO_ARGS, Long, &[0x48], NO_MODRM, NO_IMM),
    bytes("xacquire", &NO_ARGS, Long, &[0xF2], NO_MODRM, NO_IMM),
    bytes("xrelease", &NO_ARGS, Long, &[0xF3], NO_MODRM, NO_IMM),
    // The other string instructions and the move again with a repeat prefix, whose operands are
    // registers the opcode names for itself. A repeat
    // prefix is one of the mandatory prefixes as far as the table is concerned, since it has to
    // come in front of the `REX` the quadword forms carry. The word forms put it after the operand
    // size prefix instead, which is as good to the processor and needs no size of its own here.
    bytes("rep movsb", &NO_ARGS, Single, &[0xA4], NO_MODRM, NO_IMM),
    bytes("rep movsw", &NO_ARGS, Word, &[0xF3, 0xA5], NO_MODRM, NO_IMM),
    bytes("rep movsl", &NO_ARGS, Single, &[0xA5], NO_MODRM, NO_IMM),
    bytes("rep movsq", &NO_ARGS, SingleQuad, &[0xA5], NO_MODRM, NO_IMM),
    bytes("stosb", &NO_ARGS, Byte, &[0xAA], NO_MODRM, NO_IMM),
    bytes("stosw", &NO_ARGS, Word, &[0xAB], NO_MODRM, NO_IMM),
    bytes("stosl", &NO_ARGS, Long, &[0xAB], NO_MODRM, NO_IMM),
    bytes("stosq", &NO_ARGS, Quad, &[0xAB], NO_MODRM, NO_IMM),
    bytes("rep stosb", &NO_ARGS, Single, &[0xAA], NO_MODRM, NO_IMM),
    bytes("rep stosw", &NO_ARGS, Word, &[0xF3, 0xAB], NO_MODRM, NO_IMM),
    bytes("rep stosl", &NO_ARGS, Single, &[0xAB], NO_MODRM, NO_IMM),
    bytes("rep stosq", &NO_ARGS, SingleQuad, &[0xAB], NO_MODRM, NO_IMM),
    bytes("lodsb", &NO_ARGS, Byte, &[0xAC], NO_MODRM, NO_IMM),
    bytes("lodsw", &NO_ARGS, Word, &[0xAD], NO_MODRM, NO_IMM),
    bytes("lodsl", &NO_ARGS, Long, &[0xAD], NO_MODRM, NO_IMM),
    bytes("lodsq", &NO_ARGS, Quad, &[0xAD], NO_MODRM, NO_IMM),
    bytes("scasb", &NO_ARGS, Byte, &[0xAE], NO_MODRM, NO_IMM),
    bytes("scasw", &NO_ARGS, Word, &[0xAF], NO_MODRM, NO_IMM),
    bytes("scasl", &NO_ARGS, Long, &[0xAF], NO_MODRM, NO_IMM),
    bytes("scasq", &NO_ARGS, Quad, &[0xAF], NO_MODRM, NO_IMM),
    bytes("repe scasb", &NO_ARGS, Single, &[0xAE], NO_MODRM, NO_IMM),
    bytes("repe scasw", &NO_ARGS, Word, &[0xF3, 0xAF], NO_MODRM, NO_IMM),
    bytes("repe scasl", &NO_ARGS, Single, &[0xAF], NO_MODRM, NO_IMM),
    bytes("repe scasq", &NO_ARGS, SingleQuad, &[0xAF], NO_MODRM, NO_IMM),
    bytes("repne scasb", &NO_ARGS, Double, &[0xAE], NO_MODRM, NO_IMM),
    bytes("repne scasw", &NO_ARGS, Word, &[0xF2, 0xAF], NO_MODRM, NO_IMM),
    bytes("repne scasl", &NO_ARGS, Double, &[0xAF], NO_MODRM, NO_IMM),
    bytes("repne scasq", &NO_ARGS, DoubleQuad, &[0xAF], NO_MODRM, NO_IMM),
    bytes("cmpsb", &NO_ARGS, Byte, &[0xA6], NO_MODRM, NO_IMM),
    bytes("cmpsw", &NO_ARGS, Word, &[0xA7], NO_MODRM, NO_IMM),
    bytes("cmpsl", &NO_ARGS, Long, &[0xA7], NO_MODRM, NO_IMM),
    bytes("cmpsq", &NO_ARGS, Quad, &[0xA7], NO_MODRM, NO_IMM),
    bytes("repe cmpsb", &NO_ARGS, Single, &[0xA6], NO_MODRM, NO_IMM),
    bytes("repe cmpsw", &NO_ARGS, Word, &[0xF3, 0xA7], NO_MODRM, NO_IMM),
    bytes("repe cmpsl", &NO_ARGS, Single, &[0xA7], NO_MODRM, NO_IMM),
    bytes("repe cmpsq", &NO_ARGS, SingleQuad, &[0xA7], NO_MODRM, NO_IMM),
    bytes("repne cmpsb", &NO_ARGS, Double, &[0xA6], NO_MODRM, NO_IMM),
    bytes("repne cmpsw", &NO_ARGS, Word, &[0xF2, 0xA7], NO_MODRM, NO_IMM),
    bytes("repne cmpsl", &NO_ARGS, Double, &[0xA7], NO_MODRM, NO_IMM),
    bytes("repne cmpsq", &NO_ARGS, DoubleQuad, &[0xA7], NO_MODRM, NO_IMM),
    // The lock prefix, which is a row of its own because that is what it is in the encoding: one
    // byte in front of the instruction it applies to, and not a bit of anything the instruction
    // itself writes. An assembler reads it the same way, so the text form is the word on a line of
    // its own in front of the instruction, which is what an opcode with two spellings already does
    // for a comparison and the byte it sets.
    //
    // No arguments, so no addressing byte and no REX, and the size is `Long` only because a row
    // has to name one and `Long` is the size that writes no prefix at all.
    bytes("lock", &NO_ARGS, Long, &[0xF0], NO_MODRM, NO_IMM),
    // The repeat prefixes, which are rows of their own for the same reason the lock prefix is one.
    // A string instruction behind one of these runs until `rcx` reaches nothing, and the two byte
    // values are the two answers the comparing forms stop on, which is why the equal spelling and
    // the plain one are the same byte: the plain one is only ever written in front of an
    // instruction that does not compare, where there is nothing for the condition to mean.
    //
    // A library written by hand also puts one of these in front of an instruction that is not a
    // string instruction at all, to ask a newer processor for the faster of two answers to the same
    // question while an older one ignores the byte entirely. That is the same byte in front of the
    // same instruction either way, so nothing here has to know which of the two it is being asked.
    bytes("rep", &NO_ARGS, Long, &[0xF3], NO_MODRM, NO_IMM),
    bytes("repe", &NO_ARGS, Long, &[0xF3], NO_MODRM, NO_IMM),
    bytes("repz", &NO_ARGS, Long, &[0xF3], NO_MODRM, NO_IMM),
    bytes("repne", &NO_ARGS, Long, &[0xF2], NO_MODRM, NO_IMM),
    bytes("repnz", &NO_ARGS, Long, &[0xF2], NO_MODRM, NO_IMM),
    // Compare and exchange, which is the one instruction on this machine that reads a register the
    // program did not name: it compares what is at the address against `rax` and puts what it
    // found there whichever way the comparison went. The byte form is one opcode below the rest,
    // the way every other pair of a byte form and a wider one here is.
    bytes("cmpxchgb", &RM, Byte, &[0x0F, 0xB0], pair(1, 0), NO_IMM),
    bytes("cmpxchgw", &RM, Word, &[0x0F, 0xB1], pair(1, 0), NO_IMM),
    bytes("cmpxchgl", &RM, Long, &[0x0F, 0xB1], pair(1, 0), NO_IMM),
    bytes("cmpxchgq", &RM, Quad, &[0x0F, 0xB1], pair(1, 0), NO_IMM),
    // The compare and exchange of two words at once, against `edx:eax` or `rdx:rax` and with
    // `ecx:ebx` or `rcx:rbx` to store. Every register is fixed, so the one operand is the address.
    // The kernel's SLUB allocator swaps a freelist and a counter together with the second.
    bytes("cmpxchg8b", &M, Long, &[0x0F, 0xC7], ext(0, 1), NO_IMM),
    bytes("cmpxchg16b", &M, Quad, &[0x0F, 0xC7], ext(0, 1), NO_IMM),
    // The exchange and the exchange and add, which are the two read modify writes this machine does
    // in one instruction. Both put the register beside the addressing byte and the object in the
    // addressing mode, the way a compare and exchange does, and both are a byte form one opcode
    // below a form for the three wider sizes.
    bytes("xchgb", &RM, Byte, &[0x86], pair(1, 0), NO_IMM),
    bytes("xchgw", &RM, Word, &[0x87], pair(1, 0), NO_IMM),
    bytes("xchgl", &RM, Long, &[0x87], pair(1, 0), NO_IMM),
    bytes("xchgq", &RM, Quad, &[0x87], pair(1, 0), NO_IMM),
    // The exchange between two registers, which is the same opcode with a register where the
    // address was. It is not atomic and needs no lock prefix, since nothing else can see either end
    // of it, which is why this compiler only ever reaches for the form above.
    bytes("xchgb", &RR, Byte, &[0x86], pair(1, 0), NO_IMM),
    bytes("xchgw", &RR, Word, &[0x87], pair(1, 0), NO_IMM),
    bytes("xchgl", &RR, Long, &[0x87], pair(1, 0), NO_IMM),
    bytes("xchgq", &RR, Quad, &[0x87], pair(1, 0), NO_IMM),
    bytes("xaddb", &RM, Byte, &[0x0F, 0xC0], pair(1, 0), NO_IMM),
    bytes("xaddw", &RM, Word, &[0x0F, 0xC1], pair(1, 0), NO_IMM),
    bytes("xaddl", &RM, Long, &[0x0F, 0xC1], pair(1, 0), NO_IMM),
    bytes("xaddq", &RM, Quad, &[0x0F, 0xC1], pair(1, 0), NO_IMM),
    // The vector moves, which are the same three shapes as the general purpose ones and are one
    // opcode apart the same way.
    bytes("movaps", &VV, Long, &[0x0F, 0x28], pair(0, 1), NO_IMM),
    bytes("movaps", &MV, Long, &[0x0F, 0x28], pair(0, 1), NO_IMM),
    bytes("movaps", &VM, Long, &[0x0F, 0x29], pair(1, 0), NO_IMM),
    // A scalar move, which is the same pair of opcodes one lower and behind the prefix that says
    // which format it is. The load is `0x10` and the store is `0x11`, the way `movaps` is `0x28`
    // and `0x29`, and the destination is the register beside the addressing byte in both.
    bytes("movss", &MV, Single, &[0x0F, 0x10], pair(0, 1), NO_IMM),
    bytes("movsd", &MV, Double, &[0x0F, 0x10], pair(0, 1), NO_IMM),
    bytes("movss", &VM, Single, &[0x0F, 0x11], pair(1, 0), NO_IMM),
    bytes("movsd", &VM, Double, &[0x0F, 0x11], pair(1, 0), NO_IMM),
    // The same move between two vector registers, which takes the load opcode because the load is
    // the one whose destination is the register beside the addressing byte. This compiler writes
    // `movaps` for a copy instead, since it moves the whole register and has no prefix to carry,
    // but a file somebody else wrote is entitled to say what it means.
    bytes("movss", &VV, Single, &[0x0F, 0x10], pair(0, 1), NO_IMM),
    bytes("movsd", &VV, Double, &[0x0F, 0x10], pair(0, 1), NO_IMM),
    // Scalar arithmetic. The four opcodes are consecutive, which is worth reading as a group: add
    // is `0x58`, multiply `0x59`, subtract `0x5C` and divide `0x5E`, and the `float` and the
    // `double` of each are the same byte behind a different prefix. The destination is the
    // register beside the addressing byte here, the opposite way round from the integer
    // arithmetic, because these instructions read their addressed operand and write the other.
    bytes("addss", &VV, Single, &[0x0F, 0x58], pair(0, 1), NO_IMM),
    bytes("addsd", &VV, Double, &[0x0F, 0x58], pair(0, 1), NO_IMM),
    bytes("mulss", &VV, Single, &[0x0F, 0x59], pair(0, 1), NO_IMM),
    bytes("mulsd", &VV, Double, &[0x0F, 0x59], pair(0, 1), NO_IMM),
    bytes("subss", &VV, Single, &[0x0F, 0x5C], pair(0, 1), NO_IMM),
    bytes("subsd", &VV, Double, &[0x0F, 0x5C], pair(0, 1), NO_IMM),
    bytes("divss", &VV, Single, &[0x0F, 0x5E], pair(0, 1), NO_IMM),
    bytes("divsd", &VV, Double, &[0x0F, 0x5E], pair(0, 1), NO_IMM),
    // One format to the other, which is one opcode with the prefix saying which way round it
    // goes: behind `0xF3` it reads a `float` and writes a `double` and behind `0xF2` it does the
    // opposite, because the prefix says what the instruction reads.
    bytes("cvtss2sd", &VV, Single, &[0x0F, 0x5A], pair(0, 1), NO_IMM),
    bytes("cvtsd2ss", &VV, Double, &[0x0F, 0x5A], pair(0, 1), NO_IMM),
    // A float to an integer, cutting towards zero, which is the rounding C asks for and is why
    // the mnemonic has two `t`s in it: `cvtss2si` is the one that rounds and no C conversion
    // wants it. The prefix says which format is read and `REX.W` says how wide the integer
    // written is, which is the pair of questions the four rows are the four answers to. The
    // suffix on the mnemonic is what tells two of these rows apart, since a row is found by what
    // its arguments are and both widths of the answer are a general purpose register.
    bytes("cvttss2sil", &VR, Single, &[0x0F, 0x2C], pair(0, 1), NO_IMM),
    bytes("cvttss2siq", &VR, SingleQuad, &[0x0F, 0x2C], pair(0, 1), NO_IMM),
    bytes("cvttsd2sil", &VR, Double, &[0x0F, 0x2C], pair(0, 1), NO_IMM),
    bytes("cvttsd2siq", &VR, DoubleQuad, &[0x0F, 0x2C], pair(0, 1), NO_IMM),
    // An integer to a float, which is the same two questions the other way round and one opcode
    // lower. The mnemonic carries the width of the integer here because the register it reads is
    // the one the assembler cannot see in a memory form, and this table writes the suffix on
    // every one of them so that the four read as four rather than as two written twice.
    bytes("cvtsi2ssl", &RV, Single, &[0x0F, 0x2A], pair(0, 1), NO_IMM),
    bytes("cvtsi2ssq", &RV, SingleQuad, &[0x0F, 0x2A], pair(0, 1), NO_IMM),
    bytes("cvtsi2sdl", &RV, Double, &[0x0F, 0x2A], pair(0, 1), NO_IMM),
    bytes("cvtsi2sdq", &RV, DoubleQuad, &[0x0F, 0x2A], pair(0, 1), NO_IMM),
    // The same bits moved from one file to the other, which is what a reinterpretation is. Two
    // opcodes, `0x6E` towards the vector register and `0x7E` away from it, and the mnemonic is
    // the width rather than the direction because the direction is which argument is which.
    bytes("movd", &RV, Word, &[0x0F, 0x6E], pair(0, 1), NO_IMM),
    bytes("movq", &RV, WordQuad, &[0x0F, 0x6E], pair(0, 1), NO_IMM),
    bytes("movd", &VR, Word, &[0x0F, 0x7E], pair(1, 0), NO_IMM),
    bytes("movq", &VR, WordQuad, &[0x0F, 0x7E], pair(1, 0), NO_IMM),
    // Sixteen bits of a vector register, named by an immediate that says which sixteen. That is
    // the one width the moves above do not have, and it is the width a `_Float16` is, so these
    // three are how a half gets into a vector register and back out of it. The immediate is always
    // zero here, since the low sixteen bits are where the psABI puts a half and where every
    // runtime routine that takes one looks, but it is an operand of the instruction rather than
    // part of the opcode and the assembler takes any of the eight a person writes.
    bytes("pinsrw", &IMV, Word, &[0x0F, 0xC4], pair(1, 2), ImmSize::Ib),
    bytes("pinsrw", &IRV, Word, &[0x0F, 0xC4], pair(1, 2), ImmSize::Ib),
    // The way back is to a general purpose register and never to memory, because the form that
    // writes memory is `0x3A 0x15` and is SSE4.1, which is above the baseline of this target. A
    // program storing a half therefore writes two instructions, which is what gcc writes as well.
    bytes("pextrw", &IVR, Word, &[0x0F, 0xC5], pair(1, 2), ImmSize::Ib),
    // Comparing two floats and setting the flags, which is one opcode with the prefix saying which
    // format is read: no prefix for a `float` and `0x66` for a `double`, which is the pairing the
    // moves at the top of this group have and not the one the arithmetic has. The register beside
    // the addressing byte is the left hand side, so the comparison reads the same way round as
    // `cvtss2sd` and the opposite way round from `cmpl`.
    bytes("ucomiss", &VV, Long, &[0x0F, 0x2E], pair(0, 1), NO_IMM),
    bytes("ucomisd", &VV, Word, &[0x0F, 0x2E], pair(0, 1), NO_IMM),
    // The integer half of the vector unit, which this compiler has no use for and a library that
    // moves words around by the pair does nothing else with. A C expression on a `double` is what
    // everything above reaches, and an instruction that treats a vector register as two sixty four
    // bit numbers is reached by a person deciding to move two limbs at a time. All of it is behind
    // `0x66`, which here is not a claim that anything is sixteen bits: an integer vector opcode is
    // the same byte as a floating point one and the prefix is what tells the two apart, the way
    // `0xF3` tells a `float` from a vector of them.
    //
    // The quadword move first, which is the odd one of the group. A vector register holds two
    // words, so moving one word between it and memory is neither the whole register nor a scalar
    // `double`, and the machine gives it two opcodes that are not a pair: the load is `0x7E` behind
    // `0xF3` and the store is `0xD6` behind `0x66`. Both clear the top half on a load, which is why
    // a library can use it to read the last limb of an odd length array without touching what is
    // beside it.
    bytes("movq", &MV, Single, &[0x0F, 0x7E], pair(0, 1), NO_IMM),
    bytes("movq", &VM, Word, &[0x0F, 0xD6], pair(1, 0), NO_IMM),
    // The whole register moved, aligned and unaligned, which is the pair `movaps` is for floats.
    // `0x6F` towards the register and `0x7F` away from it, with `0x66` for the form that faults on
    // an address that is not a multiple of sixteen and `0xF3` for the form that does not. A library
    // reads with the unaligned one and writes with the aligned one, because it aligned the
    // destination itself and has no say over where the caller's source begins.
    bytes("movdqa", &VV, Word, &[0x0F, 0x6F], pair(0, 1), NO_IMM),
    bytes("movdqa", &MV, Word, &[0x0F, 0x6F], pair(0, 1), NO_IMM),
    bytes("movdqa", &VM, Word, &[0x0F, 0x7F], pair(1, 0), NO_IMM),
    bytes("movdqu", &VV, Single, &[0x0F, 0x6F], pair(0, 1), NO_IMM),
    bytes("movdqu", &MV, Single, &[0x0F, 0x6F], pair(0, 1), NO_IMM),
    bytes("movdqu", &VM, Single, &[0x0F, 0x7F], pair(1, 0), NO_IMM),
    // Putting the low words of two registers together, which is how a pair of limbs read one at a
    // time becomes one vector, and taking the high words, which is the other half of the same idea.
    bytes("punpcklqdq", &VV, Word, &[0x0F, 0x6C], pair(0, 1), NO_IMM),
    bytes("punpcklqdq", &MV, Word, &[0x0F, 0x6C], pair(0, 1), NO_IMM),
    bytes("punpckhqdq", &VV, Word, &[0x0F, 0x6D], pair(0, 1), NO_IMM),
    bytes("punpckhqdq", &MV, Word, &[0x0F, 0x6D], pair(0, 1), NO_IMM),
    // The four logical instructions, which have no width in their names because a bit is a bit
    // whatever the register is being read as. `pandn` is the one worth reading twice: it complements
    // the register beside the addressing byte and not the addressed one, so the operands are not
    // interchangeable the way the other three are.
    bytes("pand", &VV, Word, &[0x0F, 0xDB], pair(0, 1), NO_IMM),
    bytes("pand", &MV, Word, &[0x0F, 0xDB], pair(0, 1), NO_IMM),
    bytes("pandn", &VV, Word, &[0x0F, 0xDF], pair(0, 1), NO_IMM),
    bytes("pandn", &MV, Word, &[0x0F, 0xDF], pair(0, 1), NO_IMM),
    bytes("por", &VV, Word, &[0x0F, 0xEB], pair(0, 1), NO_IMM),
    bytes("por", &MV, Word, &[0x0F, 0xEB], pair(0, 1), NO_IMM),
    bytes("pxor", &VV, Word, &[0x0F, 0xEF], pair(0, 1), NO_IMM),
    bytes("pxor", &MV, Word, &[0x0F, 0xEF], pair(0, 1), NO_IMM),
    // Comparing for equality, which writes all ones or all zeroes into each piece rather than
    // setting a flag, because there is no one answer to give about sixteen comparisons at once. A
    // register compared against itself is every piece equal to itself, so `pcmpeqb %xmm3, %xmm3` is
    // how a file written by hand fills a register with ones without reading a constant from memory.
    bytes("pcmpeqb", &VV, Word, &[0x0F, 0x74], pair(0, 1), NO_IMM),
    bytes("pcmpeqb", &MV, Word, &[0x0F, 0x74], pair(0, 1), NO_IMM),
    bytes("pcmpeqw", &VV, Word, &[0x0F, 0x75], pair(0, 1), NO_IMM),
    bytes("pcmpeqw", &MV, Word, &[0x0F, 0x75], pair(0, 1), NO_IMM),
    bytes("pcmpeqd", &VV, Word, &[0x0F, 0x76], pair(0, 1), NO_IMM),
    bytes("pcmpeqd", &MV, Word, &[0x0F, 0x76], pair(0, 1), NO_IMM),
    // Adding and subtracting each piece without carrying between them, which is what makes these
    // different instructions per width rather than one instruction with a prefix. Nothing carries
    // out of a piece into the piece above it, so a library adding numbers wider than a register
    // cannot use them for that and uses them for everything else.
    bytes("paddb", &VV, Word, &[0x0F, 0xFC], pair(0, 1), NO_IMM),
    bytes("paddw", &VV, Word, &[0x0F, 0xFD], pair(0, 1), NO_IMM),
    bytes("paddd", &VV, Word, &[0x0F, 0xFE], pair(0, 1), NO_IMM),
    bytes("paddq", &VV, Word, &[0x0F, 0xD4], pair(0, 1), NO_IMM),
    bytes("psubb", &VV, Word, &[0x0F, 0xF8], pair(0, 1), NO_IMM),
    bytes("psubw", &VV, Word, &[0x0F, 0xF9], pair(0, 1), NO_IMM),
    bytes("psubd", &VV, Word, &[0x0F, 0xFA], pair(0, 1), NO_IMM),
    bytes("psubq", &VV, Word, &[0x0F, 0xFB], pair(0, 1), NO_IMM),
    // Shifting each piece, by a count in a second vector register and by a count written down. The
    // two are different opcodes rather than one opcode with the count in a different place, and the
    // written down one shares three opcodes between eight instructions the way the general purpose
    // group shares `0xF7`, with the extension in the addressing byte saying which.
    //
    // The count is the whole low sixty four bits of the second register and not its low byte, so a
    // count of more than the width of a piece is every piece zero rather than a count taken modulo
    // anything, which is the opposite of what a general purpose shift does and is the point: a
    // library shifting a number across limb boundaries feeds these a count it worked out and wants
    // the answer for a count of sixty four to be nothing rather than everything.
    bytes("psllw", &VV, Word, &[0x0F, 0xF1], pair(0, 1), NO_IMM),
    bytes("pslld", &VV, Word, &[0x0F, 0xF2], pair(0, 1), NO_IMM),
    bytes("psllq", &VV, Word, &[0x0F, 0xF3], pair(0, 1), NO_IMM),
    bytes("psrlw", &VV, Word, &[0x0F, 0xD1], pair(0, 1), NO_IMM),
    bytes("psrld", &VV, Word, &[0x0F, 0xD2], pair(0, 1), NO_IMM),
    bytes("psrlq", &VV, Word, &[0x0F, 0xD3], pair(0, 1), NO_IMM),
    bytes("psraw", &VV, Word, &[0x0F, 0xE1], pair(0, 1), NO_IMM),
    bytes("psrad", &VV, Word, &[0x0F, 0xE2], pair(0, 1), NO_IMM),
    bytes("psllw", &IV, Word, &[0x0F, 0x71], ext(1, 6), ImmSize::Ib),
    bytes("psrlw", &IV, Word, &[0x0F, 0x71], ext(1, 2), ImmSize::Ib),
    bytes("psraw", &IV, Word, &[0x0F, 0x71], ext(1, 4), ImmSize::Ib),
    bytes("pslld", &IV, Word, &[0x0F, 0x72], ext(1, 6), ImmSize::Ib),
    bytes("psrld", &IV, Word, &[0x0F, 0x72], ext(1, 2), ImmSize::Ib),
    bytes("psrad", &IV, Word, &[0x0F, 0x72], ext(1, 4), ImmSize::Ib),
    bytes("psllq", &IV, Word, &[0x0F, 0x73], ext(1, 6), ImmSize::Ib),
    bytes("psrlq", &IV, Word, &[0x0F, 0x73], ext(1, 2), ImmSize::Ib),
    // And the two that shift the whole register rather than each piece of it, whose count is in
    // bytes rather than in bits because that is the only thing moving a register sideways can mean.
    bytes("pslldq", &IV, Word, &[0x0F, 0x73], ext(1, 7), ImmSize::Ib),
    bytes("psrldq", &IV, Word, &[0x0F, 0x73], ext(1, 3), ImmSize::Ib),
    // What a file gcc wrote reads from SSE and this compiler does not write itself. Most of it is
    // a form above with the source in memory, which gcc uses wherever a constant or a spilled value
    // is read once, and the rest is instructions gcc reaches for and this compiler does without.
    bytes("addss", &MV, Single, &[0x0F, 0x58], pair(0, 1), NO_IMM),
    bytes("addsd", &MV, Double, &[0x0F, 0x58], pair(0, 1), NO_IMM),
    bytes("mulss", &MV, Single, &[0x0F, 0x59], pair(0, 1), NO_IMM),
    bytes("mulsd", &MV, Double, &[0x0F, 0x59], pair(0, 1), NO_IMM),
    bytes("subss", &MV, Single, &[0x0F, 0x5C], pair(0, 1), NO_IMM),
    bytes("subsd", &MV, Double, &[0x0F, 0x5C], pair(0, 1), NO_IMM),
    bytes("divss", &MV, Single, &[0x0F, 0x5E], pair(0, 1), NO_IMM),
    bytes("divsd", &MV, Double, &[0x0F, 0x5E], pair(0, 1), NO_IMM),
    // The square root, the smaller and the larger, which gcc writes for `sqrt`, `fmin` and `fmax`
    // and for a comparison and a pick it can see is one of the two.
    bytes("sqrtss", &VV, Single, &[0x0F, 0x51], pair(0, 1), NO_IMM),
    bytes("sqrtsd", &VV, Double, &[0x0F, 0x51], pair(0, 1), NO_IMM),
    bytes("sqrtss", &MV, Single, &[0x0F, 0x51], pair(0, 1), NO_IMM),
    bytes("sqrtsd", &MV, Double, &[0x0F, 0x51], pair(0, 1), NO_IMM),
    bytes("minss", &VV, Single, &[0x0F, 0x5D], pair(0, 1), NO_IMM),
    bytes("minsd", &VV, Double, &[0x0F, 0x5D], pair(0, 1), NO_IMM),
    bytes("minss", &MV, Single, &[0x0F, 0x5D], pair(0, 1), NO_IMM),
    bytes("minsd", &MV, Double, &[0x0F, 0x5D], pair(0, 1), NO_IMM),
    bytes("maxss", &VV, Single, &[0x0F, 0x5F], pair(0, 1), NO_IMM),
    bytes("maxsd", &VV, Double, &[0x0F, 0x5F], pair(0, 1), NO_IMM),
    bytes("maxss", &MV, Single, &[0x0F, 0x5F], pair(0, 1), NO_IMM),
    bytes("maxsd", &MV, Double, &[0x0F, 0x5F], pair(0, 1), NO_IMM),
    // The conversions again with the source in memory.
    bytes("cvtss2sd", &MV, Single, &[0x0F, 0x5A], pair(0, 1), NO_IMM),
    bytes("cvtsd2ss", &MV, Double, &[0x0F, 0x5A], pair(0, 1), NO_IMM),
    bytes("cvtsi2ssl", &MV, Single, &[0x0F, 0x2A], pair(0, 1), NO_IMM),
    bytes("cvtsi2ssq", &MV, SingleQuad, &[0x0F, 0x2A], pair(0, 1), NO_IMM),
    bytes("cvtsi2sdl", &MV, Double, &[0x0F, 0x2A], pair(0, 1), NO_IMM),
    bytes("cvtsi2sdq", &MV, DoubleQuad, &[0x0F, 0x2A], pair(0, 1), NO_IMM),
    bytes("cvttss2sil", &MR, Single, &[0x0F, 0x2C], pair(0, 1), NO_IMM),
    bytes("cvttss2siq", &MR, SingleQuad, &[0x0F, 0x2C], pair(0, 1), NO_IMM),
    bytes("cvttsd2sil", &MR, Double, &[0x0F, 0x2C], pair(0, 1), NO_IMM),
    bytes("cvttsd2siq", &MR, DoubleQuad, &[0x0F, 0x2C], pair(0, 1), NO_IMM),
    // The comparisons with memory on the left, and the ones that also raise the invalid exception
    // on a quiet NaN, which is what an ordered comparison in C is and what gcc writes for `<`.
    bytes("ucomiss", &MV, Long, &[0x0F, 0x2E], pair(0, 1), NO_IMM),
    bytes("ucomisd", &MV, Word, &[0x0F, 0x2E], pair(0, 1), NO_IMM),
    bytes("comiss", &VV, Long, &[0x0F, 0x2F], pair(0, 1), NO_IMM),
    bytes("comisd", &VV, Word, &[0x0F, 0x2F], pair(0, 1), NO_IMM),
    bytes("comiss", &MV, Long, &[0x0F, 0x2F], pair(0, 1), NO_IMM),
    bytes("comisd", &MV, Word, &[0x0F, 0x2F], pair(0, 1), NO_IMM),
    // The moves of a whole register that do not ask for sixteen byte alignment, and the `double`
    // spelling of the aligned one. gcc copies a small struct with `movups` more than with anything.
    bytes("movups", &VV, Long, &[0x0F, 0x10], pair(0, 1), NO_IMM),
    bytes("movups", &MV, Long, &[0x0F, 0x10], pair(0, 1), NO_IMM),
    bytes("movups", &VM, Long, &[0x0F, 0x11], pair(1, 0), NO_IMM),
    bytes("movupd", &VV, Word, &[0x0F, 0x10], pair(0, 1), NO_IMM),
    bytes("movupd", &MV, Word, &[0x0F, 0x10], pair(0, 1), NO_IMM),
    bytes("movupd", &VM, Word, &[0x0F, 0x11], pair(1, 0), NO_IMM),
    bytes("movapd", &VV, Word, &[0x0F, 0x28], pair(0, 1), NO_IMM),
    bytes("movapd", &MV, Word, &[0x0F, 0x28], pair(0, 1), NO_IMM),
    bytes("movapd", &VM, Word, &[0x0F, 0x29], pair(1, 0), NO_IMM),
    // The bitwise operations on the float formats, which is how gcc takes an absolute value or
    // flips a sign: a mask from memory and one of these.
    bytes("andps", &VV, Long, &[0x0F, 0x54], pair(0, 1), NO_IMM),
    bytes("andpd", &VV, Word, &[0x0F, 0x54], pair(0, 1), NO_IMM),
    bytes("andps", &MV, Long, &[0x0F, 0x54], pair(0, 1), NO_IMM),
    bytes("andpd", &MV, Word, &[0x0F, 0x54], pair(0, 1), NO_IMM),
    bytes("andnps", &VV, Long, &[0x0F, 0x55], pair(0, 1), NO_IMM),
    bytes("andnpd", &VV, Word, &[0x0F, 0x55], pair(0, 1), NO_IMM),
    bytes("andnps", &MV, Long, &[0x0F, 0x55], pair(0, 1), NO_IMM),
    bytes("andnpd", &MV, Word, &[0x0F, 0x55], pair(0, 1), NO_IMM),
    bytes("orps", &VV, Long, &[0x0F, 0x56], pair(0, 1), NO_IMM),
    bytes("orpd", &VV, Word, &[0x0F, 0x56], pair(0, 1), NO_IMM),
    bytes("orps", &MV, Long, &[0x0F, 0x56], pair(0, 1), NO_IMM),
    bytes("orpd", &MV, Word, &[0x0F, 0x56], pair(0, 1), NO_IMM),
    bytes("xorps", &VV, Long, &[0x0F, 0x57], pair(0, 1), NO_IMM),
    bytes("xorpd", &VV, Word, &[0x0F, 0x57], pair(0, 1), NO_IMM),
    bytes("xorps", &MV, Long, &[0x0F, 0x57], pair(0, 1), NO_IMM),
    bytes("xorpd", &MV, Word, &[0x0F, 0x57], pair(0, 1), NO_IMM),
    // Half a register to or from memory, and the high half of one register into the other.
    bytes("movlps", &MV, Long, &[0x0F, 0x12], pair(0, 1), NO_IMM),
    bytes("movlps", &VM, Long, &[0x0F, 0x13], pair(1, 0), NO_IMM),
    bytes("movhps", &MV, Long, &[0x0F, 0x16], pair(0, 1), NO_IMM),
    bytes("movhps", &VM, Long, &[0x0F, 0x17], pair(1, 0), NO_IMM),
    bytes("movlpd", &MV, Word, &[0x0F, 0x12], pair(0, 1), NO_IMM),
    bytes("movlpd", &VM, Word, &[0x0F, 0x13], pair(1, 0), NO_IMM),
    bytes("movhpd", &MV, Word, &[0x0F, 0x16], pair(0, 1), NO_IMM),
    bytes("movhpd", &VM, Word, &[0x0F, 0x17], pair(1, 0), NO_IMM),
    bytes("movhlps", &VV, Long, &[0x0F, 0x12], pair(0, 1), NO_IMM),
    bytes("movlhps", &VV, Long, &[0x0F, 0x16], pair(0, 1), NO_IMM),
    // Thirty two bits of a vector register to or from memory.
    bytes("movd", &MV, Word, &[0x0F, 0x6E], pair(0, 1), NO_IMM),
    bytes("movd", &VM, Word, &[0x0F, 0x7E], pair(1, 0), NO_IMM),
    // The shuffles, each an immediate, a source and a destination.
    bytes("shufps", &IVV, Long, &[0x0F, 0xC6], pair(1, 2), ImmSize::Ib),
    bytes("shufps", &IMV, Long, &[0x0F, 0xC6], pair(1, 2), ImmSize::Ib),
    bytes("shufpd", &IVV, Word, &[0x0F, 0xC6], pair(1, 2), ImmSize::Ib),
    bytes("shufpd", &IMV, Word, &[0x0F, 0xC6], pair(1, 2), ImmSize::Ib),
    bytes("pshufd", &IVV, Word, &[0x0F, 0x70], pair(1, 2), ImmSize::Ib),
    bytes("pshufd", &IMV, Word, &[0x0F, 0x70], pair(1, 2), ImmSize::Ib),
    bytes("pshuflw", &IVV, Double, &[0x0F, 0x70], pair(1, 2), ImmSize::Ib),
    bytes("pshuflw", &IMV, Double, &[0x0F, 0x70], pair(1, 2), ImmSize::Ib),
    bytes("pshufhw", &IVV, Single, &[0x0F, 0x70], pair(1, 2), ImmSize::Ib),
    bytes("pshufhw", &IMV, Single, &[0x0F, 0x70], pair(1, 2), ImmSize::Ib),
    // Above the baseline and never written by the compiler, but hand written code that checks the
    // processor first uses them, such as busybox's SHA routines. `pshufb` and `palignr` are SSSE3,
    // behind the `0x38` and `0x3A` escapes.
    bytes("pshufb", &VV, Word, &[0x0F, 0x38, 0x00], pair(0, 1), NO_IMM),
    bytes("pshufb", &MV, Word, &[0x0F, 0x38, 0x00], pair(0, 1), NO_IMM),
    bytes("palignr", &IVV, Word, &[0x0F, 0x3A, 0x0F], pair(1, 2), ImmSize::Ib),
    bytes("palignr", &IMV, Word, &[0x0F, 0x3A, 0x0F], pair(1, 2), ImmSize::Ib),
    // AES-NI and carry-less multiplication, which the kernel's crypto code is written in.
    bytes("aesenc", &VV, Word, &[0x0F, 0x38, 0xDC], pair(0, 1), NO_IMM),
    bytes("aesenc", &MV, Word, &[0x0F, 0x38, 0xDC], pair(0, 1), NO_IMM),
    bytes("aesenclast", &VV, Word, &[0x0F, 0x38, 0xDD], pair(0, 1), NO_IMM),
    bytes("aesenclast", &MV, Word, &[0x0F, 0x38, 0xDD], pair(0, 1), NO_IMM),
    bytes("aesdec", &VV, Word, &[0x0F, 0x38, 0xDE], pair(0, 1), NO_IMM),
    bytes("aesdec", &MV, Word, &[0x0F, 0x38, 0xDE], pair(0, 1), NO_IMM),
    bytes("aesdeclast", &VV, Word, &[0x0F, 0x38, 0xDF], pair(0, 1), NO_IMM),
    bytes("aesdeclast", &MV, Word, &[0x0F, 0x38, 0xDF], pair(0, 1), NO_IMM),
    bytes("aesimc", &VV, Word, &[0x0F, 0x38, 0xDB], pair(0, 1), NO_IMM),
    bytes("aesimc", &MV, Word, &[0x0F, 0x38, 0xDB], pair(0, 1), NO_IMM),
    bytes("aeskeygenassist", &IVV, Word, &[0x0F, 0x3A, 0xDF], pair(1, 2), ImmSize::Ib),
    bytes("aeskeygenassist", &IMV, Word, &[0x0F, 0x3A, 0xDF], pair(1, 2), ImmSize::Ib),
    bytes("pclmulqdq", &IVV, Word, &[0x0F, 0x3A, 0x44], pair(1, 2), ImmSize::Ib),
    bytes("pclmulqdq", &IMV, Word, &[0x0F, 0x3A, 0x44], pair(1, 2), ImmSize::Ib),
    // SSE4.1 lanes in and out. The general register or the address is always the one in the low
    // bits of the addressing byte, so for an extract that is the destination.
    bytes("pinsrb", &IRV, Word, &[0x0F, 0x3A, 0x20], pair(1, 2), ImmSize::Ib),
    bytes("pinsrb", &IMV, Word, &[0x0F, 0x3A, 0x20], pair(1, 2), ImmSize::Ib),
    bytes("pinsrd", &IRV, Word, &[0x0F, 0x3A, 0x22], pair(1, 2), ImmSize::Ib),
    bytes("pinsrd", &IMV, Word, &[0x0F, 0x3A, 0x22], pair(1, 2), ImmSize::Ib),
    bytes("pinsrq", &IRV, WordQuad, &[0x0F, 0x3A, 0x22], pair(1, 2), ImmSize::Ib),
    bytes("pinsrq", &IMV, WordQuad, &[0x0F, 0x3A, 0x22], pair(1, 2), ImmSize::Ib),
    bytes("pextrb", &IVR, Word, &[0x0F, 0x3A, 0x14], pair(2, 1), ImmSize::Ib),
    bytes("pextrb", &IVM, Word, &[0x0F, 0x3A, 0x14], pair(2, 1), ImmSize::Ib),
    bytes("pextrd", &IVR, Word, &[0x0F, 0x3A, 0x16], pair(2, 1), ImmSize::Ib),
    bytes("pextrd", &IVM, Word, &[0x0F, 0x3A, 0x16], pair(2, 1), ImmSize::Ib),
    bytes("pextrq", &IVR, WordQuad, &[0x0F, 0x3A, 0x16], pair(2, 1), ImmSize::Ib),
    bytes("pextrq", &IVM, WordQuad, &[0x0F, 0x3A, 0x16], pair(2, 1), ImmSize::Ib),
    // SSE3, each behind one of the three prefixes and the plain escape. `lddqu` reads memory and
    // nothing else, since its point is how it reads it.
    bytes("addsubps", &VV, Double, &[0x0F, 0xD0], pair(0, 1), NO_IMM),
    bytes("addsubps", &MV, Double, &[0x0F, 0xD0], pair(0, 1), NO_IMM),
    bytes("addsubpd", &VV, Word, &[0x0F, 0xD0], pair(0, 1), NO_IMM),
    bytes("addsubpd", &MV, Word, &[0x0F, 0xD0], pair(0, 1), NO_IMM),
    bytes("haddps", &VV, Double, &[0x0F, 0x7C], pair(0, 1), NO_IMM),
    bytes("haddps", &MV, Double, &[0x0F, 0x7C], pair(0, 1), NO_IMM),
    bytes("haddpd", &VV, Word, &[0x0F, 0x7C], pair(0, 1), NO_IMM),
    bytes("haddpd", &MV, Word, &[0x0F, 0x7C], pair(0, 1), NO_IMM),
    bytes("hsubps", &VV, Double, &[0x0F, 0x7D], pair(0, 1), NO_IMM),
    bytes("hsubps", &MV, Double, &[0x0F, 0x7D], pair(0, 1), NO_IMM),
    bytes("hsubpd", &VV, Word, &[0x0F, 0x7D], pair(0, 1), NO_IMM),
    bytes("hsubpd", &MV, Word, &[0x0F, 0x7D], pair(0, 1), NO_IMM),
    bytes("movshdup", &VV, Single, &[0x0F, 0x16], pair(0, 1), NO_IMM),
    bytes("movshdup", &MV, Single, &[0x0F, 0x16], pair(0, 1), NO_IMM),
    bytes("movsldup", &VV, Single, &[0x0F, 0x12], pair(0, 1), NO_IMM),
    bytes("movsldup", &MV, Single, &[0x0F, 0x12], pair(0, 1), NO_IMM),
    bytes("movddup", &VV, Double, &[0x0F, 0x12], pair(0, 1), NO_IMM),
    bytes("movddup", &MV, Double, &[0x0F, 0x12], pair(0, 1), NO_IMM),
    bytes("lddqu", &MV, Double, &[0x0F, 0xF0], pair(0, 1), NO_IMM),
    // The rest of SSSE3, all behind `0x66` and the `0x38` escape. The eight byte MMX forms are not
    // here, since nothing in this compiler writes an MMX register.
    bytes("phaddw", &VV, Word, &[0x0F, 0x38, 0x01], pair(0, 1), NO_IMM),
    bytes("phaddw", &MV, Word, &[0x0F, 0x38, 0x01], pair(0, 1), NO_IMM),
    bytes("phaddd", &VV, Word, &[0x0F, 0x38, 0x02], pair(0, 1), NO_IMM),
    bytes("phaddd", &MV, Word, &[0x0F, 0x38, 0x02], pair(0, 1), NO_IMM),
    bytes("phaddsw", &VV, Word, &[0x0F, 0x38, 0x03], pair(0, 1), NO_IMM),
    bytes("phaddsw", &MV, Word, &[0x0F, 0x38, 0x03], pair(0, 1), NO_IMM),
    bytes("pmaddubsw", &VV, Word, &[0x0F, 0x38, 0x04], pair(0, 1), NO_IMM),
    bytes("pmaddubsw", &MV, Word, &[0x0F, 0x38, 0x04], pair(0, 1), NO_IMM),
    bytes("phsubw", &VV, Word, &[0x0F, 0x38, 0x05], pair(0, 1), NO_IMM),
    bytes("phsubw", &MV, Word, &[0x0F, 0x38, 0x05], pair(0, 1), NO_IMM),
    bytes("phsubd", &VV, Word, &[0x0F, 0x38, 0x06], pair(0, 1), NO_IMM),
    bytes("phsubd", &MV, Word, &[0x0F, 0x38, 0x06], pair(0, 1), NO_IMM),
    bytes("phsubsw", &VV, Word, &[0x0F, 0x38, 0x07], pair(0, 1), NO_IMM),
    bytes("phsubsw", &MV, Word, &[0x0F, 0x38, 0x07], pair(0, 1), NO_IMM),
    bytes("psignb", &VV, Word, &[0x0F, 0x38, 0x08], pair(0, 1), NO_IMM),
    bytes("psignb", &MV, Word, &[0x0F, 0x38, 0x08], pair(0, 1), NO_IMM),
    bytes("psignw", &VV, Word, &[0x0F, 0x38, 0x09], pair(0, 1), NO_IMM),
    bytes("psignw", &MV, Word, &[0x0F, 0x38, 0x09], pair(0, 1), NO_IMM),
    bytes("psignd", &VV, Word, &[0x0F, 0x38, 0x0A], pair(0, 1), NO_IMM),
    bytes("psignd", &MV, Word, &[0x0F, 0x38, 0x0A], pair(0, 1), NO_IMM),
    bytes("pmulhrsw", &VV, Word, &[0x0F, 0x38, 0x0B], pair(0, 1), NO_IMM),
    bytes("pmulhrsw", &MV, Word, &[0x0F, 0x38, 0x0B], pair(0, 1), NO_IMM),
    bytes("pabsb", &VV, Word, &[0x0F, 0x38, 0x1C], pair(0, 1), NO_IMM),
    bytes("pabsb", &MV, Word, &[0x0F, 0x38, 0x1C], pair(0, 1), NO_IMM),
    bytes("pabsw", &VV, Word, &[0x0F, 0x38, 0x1D], pair(0, 1), NO_IMM),
    bytes("pabsw", &MV, Word, &[0x0F, 0x38, 0x1D], pair(0, 1), NO_IMM),
    bytes("pabsd", &VV, Word, &[0x0F, 0x38, 0x1E], pair(0, 1), NO_IMM),
    bytes("pabsd", &MV, Word, &[0x0F, 0x38, 0x1E], pair(0, 1), NO_IMM),
    // SSE4.1 and the one SSE4.2 comparison behind the `0x38` escape. The three variable blends read
    // their mask from `xmm0`, which is not encoded, so the reader drops it when a file names it, as
    // it does for `sha256rnds2`. `movntdqa` reads memory and nothing else.
    bytes("pblendvb", &VV, Word, &[0x0F, 0x38, 0x10], pair(0, 1), NO_IMM),
    bytes("pblendvb", &MV, Word, &[0x0F, 0x38, 0x10], pair(0, 1), NO_IMM),
    bytes("blendvps", &VV, Word, &[0x0F, 0x38, 0x14], pair(0, 1), NO_IMM),
    bytes("blendvps", &MV, Word, &[0x0F, 0x38, 0x14], pair(0, 1), NO_IMM),
    bytes("blendvpd", &VV, Word, &[0x0F, 0x38, 0x15], pair(0, 1), NO_IMM),
    bytes("blendvpd", &MV, Word, &[0x0F, 0x38, 0x15], pair(0, 1), NO_IMM),
    bytes("ptest", &VV, Word, &[0x0F, 0x38, 0x17], pair(0, 1), NO_IMM),
    bytes("ptest", &MV, Word, &[0x0F, 0x38, 0x17], pair(0, 1), NO_IMM),
    bytes("pmovsxbw", &VV, Word, &[0x0F, 0x38, 0x20], pair(0, 1), NO_IMM),
    bytes("pmovsxbw", &MV, Word, &[0x0F, 0x38, 0x20], pair(0, 1), NO_IMM),
    bytes("pmovsxbd", &VV, Word, &[0x0F, 0x38, 0x21], pair(0, 1), NO_IMM),
    bytes("pmovsxbd", &MV, Word, &[0x0F, 0x38, 0x21], pair(0, 1), NO_IMM),
    bytes("pmovsxbq", &VV, Word, &[0x0F, 0x38, 0x22], pair(0, 1), NO_IMM),
    bytes("pmovsxbq", &MV, Word, &[0x0F, 0x38, 0x22], pair(0, 1), NO_IMM),
    bytes("pmovsxwd", &VV, Word, &[0x0F, 0x38, 0x23], pair(0, 1), NO_IMM),
    bytes("pmovsxwd", &MV, Word, &[0x0F, 0x38, 0x23], pair(0, 1), NO_IMM),
    bytes("pmovsxwq", &VV, Word, &[0x0F, 0x38, 0x24], pair(0, 1), NO_IMM),
    bytes("pmovsxwq", &MV, Word, &[0x0F, 0x38, 0x24], pair(0, 1), NO_IMM),
    bytes("pmovsxdq", &VV, Word, &[0x0F, 0x38, 0x25], pair(0, 1), NO_IMM),
    bytes("pmovsxdq", &MV, Word, &[0x0F, 0x38, 0x25], pair(0, 1), NO_IMM),
    bytes("pmuldq", &VV, Word, &[0x0F, 0x38, 0x28], pair(0, 1), NO_IMM),
    bytes("pmuldq", &MV, Word, &[0x0F, 0x38, 0x28], pair(0, 1), NO_IMM),
    bytes("pcmpeqq", &VV, Word, &[0x0F, 0x38, 0x29], pair(0, 1), NO_IMM),
    bytes("pcmpeqq", &MV, Word, &[0x0F, 0x38, 0x29], pair(0, 1), NO_IMM),
    bytes("packusdw", &VV, Word, &[0x0F, 0x38, 0x2B], pair(0, 1), NO_IMM),
    bytes("packusdw", &MV, Word, &[0x0F, 0x38, 0x2B], pair(0, 1), NO_IMM),
    bytes("pmovzxbw", &VV, Word, &[0x0F, 0x38, 0x30], pair(0, 1), NO_IMM),
    bytes("pmovzxbw", &MV, Word, &[0x0F, 0x38, 0x30], pair(0, 1), NO_IMM),
    bytes("pmovzxbd", &VV, Word, &[0x0F, 0x38, 0x31], pair(0, 1), NO_IMM),
    bytes("pmovzxbd", &MV, Word, &[0x0F, 0x38, 0x31], pair(0, 1), NO_IMM),
    bytes("pmovzxbq", &VV, Word, &[0x0F, 0x38, 0x32], pair(0, 1), NO_IMM),
    bytes("pmovzxbq", &MV, Word, &[0x0F, 0x38, 0x32], pair(0, 1), NO_IMM),
    bytes("pmovzxwd", &VV, Word, &[0x0F, 0x38, 0x33], pair(0, 1), NO_IMM),
    bytes("pmovzxwd", &MV, Word, &[0x0F, 0x38, 0x33], pair(0, 1), NO_IMM),
    bytes("pmovzxwq", &VV, Word, &[0x0F, 0x38, 0x34], pair(0, 1), NO_IMM),
    bytes("pmovzxwq", &MV, Word, &[0x0F, 0x38, 0x34], pair(0, 1), NO_IMM),
    bytes("pmovzxdq", &VV, Word, &[0x0F, 0x38, 0x35], pair(0, 1), NO_IMM),
    bytes("pmovzxdq", &MV, Word, &[0x0F, 0x38, 0x35], pair(0, 1), NO_IMM),
    bytes("pcmpgtq", &VV, Word, &[0x0F, 0x38, 0x37], pair(0, 1), NO_IMM),
    bytes("pcmpgtq", &MV, Word, &[0x0F, 0x38, 0x37], pair(0, 1), NO_IMM),
    bytes("pminsb", &VV, Word, &[0x0F, 0x38, 0x38], pair(0, 1), NO_IMM),
    bytes("pminsb", &MV, Word, &[0x0F, 0x38, 0x38], pair(0, 1), NO_IMM),
    bytes("pminsd", &VV, Word, &[0x0F, 0x38, 0x39], pair(0, 1), NO_IMM),
    bytes("pminsd", &MV, Word, &[0x0F, 0x38, 0x39], pair(0, 1), NO_IMM),
    bytes("pminuw", &VV, Word, &[0x0F, 0x38, 0x3A], pair(0, 1), NO_IMM),
    bytes("pminuw", &MV, Word, &[0x0F, 0x38, 0x3A], pair(0, 1), NO_IMM),
    bytes("pminud", &VV, Word, &[0x0F, 0x38, 0x3B], pair(0, 1), NO_IMM),
    bytes("pminud", &MV, Word, &[0x0F, 0x38, 0x3B], pair(0, 1), NO_IMM),
    bytes("pmaxsb", &VV, Word, &[0x0F, 0x38, 0x3C], pair(0, 1), NO_IMM),
    bytes("pmaxsb", &MV, Word, &[0x0F, 0x38, 0x3C], pair(0, 1), NO_IMM),
    bytes("pmaxsd", &VV, Word, &[0x0F, 0x38, 0x3D], pair(0, 1), NO_IMM),
    bytes("pmaxsd", &MV, Word, &[0x0F, 0x38, 0x3D], pair(0, 1), NO_IMM),
    bytes("pmaxuw", &VV, Word, &[0x0F, 0x38, 0x3E], pair(0, 1), NO_IMM),
    bytes("pmaxuw", &MV, Word, &[0x0F, 0x38, 0x3E], pair(0, 1), NO_IMM),
    bytes("pmaxud", &VV, Word, &[0x0F, 0x38, 0x3F], pair(0, 1), NO_IMM),
    bytes("pmaxud", &MV, Word, &[0x0F, 0x38, 0x3F], pair(0, 1), NO_IMM),
    bytes("pmulld", &VV, Word, &[0x0F, 0x38, 0x40], pair(0, 1), NO_IMM),
    bytes("pmulld", &MV, Word, &[0x0F, 0x38, 0x40], pair(0, 1), NO_IMM),
    bytes("phminposuw", &VV, Word, &[0x0F, 0x38, 0x41], pair(0, 1), NO_IMM),
    bytes("phminposuw", &MV, Word, &[0x0F, 0x38, 0x41], pair(0, 1), NO_IMM),
    bytes("movntdqa", &MV, Word, &[0x0F, 0x38, 0x2A], pair(0, 1), NO_IMM),
    // The store the other way, which goes around the cache, and is how lib/raid6 writes the
    // parity it worked out.
    bytes("movntdq", &VM, Word, &[0x0F, 0xE7], pair(1, 0), NO_IMM),
    // The non-temporal store from a general purpose register, which the kernel's uncached user
    // copy writes. The width comes from the register, so the letter is found the way it is for
    // any other mnemonic written without one.
    bytes("movntil", &RM, Long, &[0x0F, 0xC3], pair(1, 0), NO_IMM),
    bytes("movntiq", &RM, Quad, &[0x0F, 0xC3], pair(1, 0), NO_IMM),
    // SSE4.1 and the SSE4.2 string comparisons behind the `0x3A` escape, each with its immediate.
    // `extractps` writes a general register or memory, which is the low bits of the addressing byte
    // the way it is for `pextrd`.
    bytes("roundps", &IVV, Word, &[0x0F, 0x3A, 0x08], pair(1, 2), ImmSize::Ib),
    bytes("roundps", &IMV, Word, &[0x0F, 0x3A, 0x08], pair(1, 2), ImmSize::Ib),
    bytes("roundpd", &IVV, Word, &[0x0F, 0x3A, 0x09], pair(1, 2), ImmSize::Ib),
    bytes("roundpd", &IMV, Word, &[0x0F, 0x3A, 0x09], pair(1, 2), ImmSize::Ib),
    bytes("roundss", &IVV, Word, &[0x0F, 0x3A, 0x0A], pair(1, 2), ImmSize::Ib),
    bytes("roundss", &IMV, Word, &[0x0F, 0x3A, 0x0A], pair(1, 2), ImmSize::Ib),
    bytes("roundsd", &IVV, Word, &[0x0F, 0x3A, 0x0B], pair(1, 2), ImmSize::Ib),
    bytes("roundsd", &IMV, Word, &[0x0F, 0x3A, 0x0B], pair(1, 2), ImmSize::Ib),
    bytes("blendps", &IVV, Word, &[0x0F, 0x3A, 0x0C], pair(1, 2), ImmSize::Ib),
    bytes("blendps", &IMV, Word, &[0x0F, 0x3A, 0x0C], pair(1, 2), ImmSize::Ib),
    bytes("blendpd", &IVV, Word, &[0x0F, 0x3A, 0x0D], pair(1, 2), ImmSize::Ib),
    bytes("blendpd", &IMV, Word, &[0x0F, 0x3A, 0x0D], pair(1, 2), ImmSize::Ib),
    bytes("pblendw", &IVV, Word, &[0x0F, 0x3A, 0x0E], pair(1, 2), ImmSize::Ib),
    bytes("pblendw", &IMV, Word, &[0x0F, 0x3A, 0x0E], pair(1, 2), ImmSize::Ib),
    bytes("insertps", &IVV, Word, &[0x0F, 0x3A, 0x21], pair(1, 2), ImmSize::Ib),
    bytes("insertps", &IMV, Word, &[0x0F, 0x3A, 0x21], pair(1, 2), ImmSize::Ib),
    bytes("dpps", &IVV, Word, &[0x0F, 0x3A, 0x40], pair(1, 2), ImmSize::Ib),
    bytes("dpps", &IMV, Word, &[0x0F, 0x3A, 0x40], pair(1, 2), ImmSize::Ib),
    bytes("dppd", &IVV, Word, &[0x0F, 0x3A, 0x41], pair(1, 2), ImmSize::Ib),
    bytes("dppd", &IMV, Word, &[0x0F, 0x3A, 0x41], pair(1, 2), ImmSize::Ib),
    bytes("mpsadbw", &IVV, Word, &[0x0F, 0x3A, 0x42], pair(1, 2), ImmSize::Ib),
    bytes("mpsadbw", &IMV, Word, &[0x0F, 0x3A, 0x42], pair(1, 2), ImmSize::Ib),
    bytes("pcmpestrm", &IVV, Word, &[0x0F, 0x3A, 0x60], pair(1, 2), ImmSize::Ib),
    bytes("pcmpestrm", &IMV, Word, &[0x0F, 0x3A, 0x60], pair(1, 2), ImmSize::Ib),
    bytes("pcmpestri", &IVV, Word, &[0x0F, 0x3A, 0x61], pair(1, 2), ImmSize::Ib),
    bytes("pcmpestri", &IMV, Word, &[0x0F, 0x3A, 0x61], pair(1, 2), ImmSize::Ib),
    bytes("pcmpistrm", &IVV, Word, &[0x0F, 0x3A, 0x62], pair(1, 2), ImmSize::Ib),
    bytes("pcmpistrm", &IMV, Word, &[0x0F, 0x3A, 0x62], pair(1, 2), ImmSize::Ib),
    bytes("pcmpistri", &IVV, Word, &[0x0F, 0x3A, 0x63], pair(1, 2), ImmSize::Ib),
    bytes("pcmpistri", &IMV, Word, &[0x0F, 0x3A, 0x63], pair(1, 2), ImmSize::Ib),
    bytes("extractps", &IVR, Word, &[0x0F, 0x3A, 0x17], pair(2, 1), ImmSize::Ib),
    bytes("extractps", &IVM, Word, &[0x0F, 0x3A, 0x17], pair(2, 1), ImmSize::Ib),
    // The SHA extensions, with no prefix. `sha256rnds2` also reads `xmm0`, which is not encoded,
    // so the reader drops it when a file names it.
    bytes("sha1rnds4", &IVV, Long, &[0x0F, 0x3A, 0xCC], pair(1, 2), ImmSize::Ib),
    bytes("sha1rnds4", &IMV, Long, &[0x0F, 0x3A, 0xCC], pair(1, 2), ImmSize::Ib),
    bytes("sha1nexte", &VV, Long, &[0x0F, 0x38, 0xC8], pair(0, 1), NO_IMM),
    bytes("sha1nexte", &MV, Long, &[0x0F, 0x38, 0xC8], pair(0, 1), NO_IMM),
    bytes("sha1msg1", &VV, Long, &[0x0F, 0x38, 0xC9], pair(0, 1), NO_IMM),
    bytes("sha1msg1", &MV, Long, &[0x0F, 0x38, 0xC9], pair(0, 1), NO_IMM),
    bytes("sha1msg2", &VV, Long, &[0x0F, 0x38, 0xCA], pair(0, 1), NO_IMM),
    bytes("sha1msg2", &MV, Long, &[0x0F, 0x38, 0xCA], pair(0, 1), NO_IMM),
    bytes("sha256rnds2", &VV, Long, &[0x0F, 0x38, 0xCB], pair(0, 1), NO_IMM),
    bytes("sha256rnds2", &MV, Long, &[0x0F, 0x38, 0xCB], pair(0, 1), NO_IMM),
    bytes("sha256msg1", &VV, Long, &[0x0F, 0x38, 0xCC], pair(0, 1), NO_IMM),
    bytes("sha256msg1", &MV, Long, &[0x0F, 0x38, 0xCC], pair(0, 1), NO_IMM),
    bytes("sha256msg2", &VV, Long, &[0x0F, 0x38, 0xCD], pair(0, 1), NO_IMM),
    bytes("sha256msg2", &MV, Long, &[0x0F, 0x38, 0xCD], pair(0, 1), NO_IMM),
    // Comparing two floats and writing all ones or all zeros for the answer, with the immediate
    // saying which of the eight comparisons it is. `cmpnlesd` and the other names are this with
    // the immediate in the name, and the reader turns them into this.
    bytes("cmpss", &IVV, Single, &[0x0F, 0xC2], pair(1, 2), ImmSize::Ib),
    bytes("cmpss", &IMV, Single, &[0x0F, 0xC2], pair(1, 2), ImmSize::Ib),
    bytes("cmpsd", &IVV, Double, &[0x0F, 0xC2], pair(1, 2), ImmSize::Ib),
    bytes("cmpsd", &IMV, Double, &[0x0F, 0xC2], pair(1, 2), ImmSize::Ib),
    bytes("cmpps", &IVV, Long, &[0x0F, 0xC2], pair(1, 2), ImmSize::Ib),
    bytes("cmpps", &IMV, Long, &[0x0F, 0xC2], pair(1, 2), ImmSize::Ib),
    bytes("cmppd", &IVV, Word, &[0x0F, 0xC2], pair(1, 2), ImmSize::Ib),
    bytes("cmppd", &IMV, Word, &[0x0F, 0xC2], pair(1, 2), ImmSize::Ib),
    // The interleaves below the quadword one above, the greater than comparisons, and the
    // unsigned multiply of the even lanes, which is how gcc multiplies two vectors of `long`.
    bytes("punpcklbw", &VV, Word, &[0x0F, 0x60], pair(0, 1), NO_IMM),
    bytes("punpcklbw", &MV, Word, &[0x0F, 0x60], pair(0, 1), NO_IMM),
    bytes("punpcklwd", &VV, Word, &[0x0F, 0x61], pair(0, 1), NO_IMM),
    bytes("punpcklwd", &MV, Word, &[0x0F, 0x61], pair(0, 1), NO_IMM),
    bytes("punpckldq", &VV, Word, &[0x0F, 0x62], pair(0, 1), NO_IMM),
    bytes("punpckldq", &MV, Word, &[0x0F, 0x62], pair(0, 1), NO_IMM),
    bytes("punpckhbw", &VV, Word, &[0x0F, 0x68], pair(0, 1), NO_IMM),
    bytes("punpckhbw", &MV, Word, &[0x0F, 0x68], pair(0, 1), NO_IMM),
    bytes("punpckhwd", &VV, Word, &[0x0F, 0x69], pair(0, 1), NO_IMM),
    bytes("punpckhwd", &MV, Word, &[0x0F, 0x69], pair(0, 1), NO_IMM),
    bytes("punpckhdq", &VV, Word, &[0x0F, 0x6A], pair(0, 1), NO_IMM),
    bytes("punpckhdq", &MV, Word, &[0x0F, 0x6A], pair(0, 1), NO_IMM),
    bytes("pcmpgtb", &VV, Word, &[0x0F, 0x64], pair(0, 1), NO_IMM),
    bytes("pcmpgtb", &MV, Word, &[0x0F, 0x64], pair(0, 1), NO_IMM),
    bytes("pcmpgtw", &VV, Word, &[0x0F, 0x65], pair(0, 1), NO_IMM),
    bytes("pcmpgtw", &MV, Word, &[0x0F, 0x65], pair(0, 1), NO_IMM),
    bytes("pcmpgtd", &VV, Word, &[0x0F, 0x66], pair(0, 1), NO_IMM),
    bytes("pcmpgtd", &MV, Word, &[0x0F, 0x66], pair(0, 1), NO_IMM),
    bytes("pmuludq", &VV, Word, &[0x0F, 0xF4], pair(0, 1), NO_IMM),
    bytes("pmuludq", &MV, Word, &[0x0F, 0xF4], pair(0, 1), NO_IMM),
    // The integer additions and subtractions with memory on the left.
    bytes("paddb", &MV, Word, &[0x0F, 0xFC], pair(0, 1), NO_IMM),
    bytes("paddw", &MV, Word, &[0x0F, 0xFD], pair(0, 1), NO_IMM),
    bytes("paddd", &MV, Word, &[0x0F, 0xFE], pair(0, 1), NO_IMM),
    bytes("paddq", &MV, Word, &[0x0F, 0xD4], pair(0, 1), NO_IMM),
    bytes("psubb", &MV, Word, &[0x0F, 0xF8], pair(0, 1), NO_IMM),
    bytes("psubw", &MV, Word, &[0x0F, 0xF9], pair(0, 1), NO_IMM),
    bytes("psubd", &MV, Word, &[0x0F, 0xFA], pair(0, 1), NO_IMM),
    bytes("psubq", &MV, Word, &[0x0F, 0xFB], pair(0, 1), NO_IMM),
    // The two x87 instructions, which are the same opcode with a different extension in the
    // addressing byte: `0xDB` with five is the load and with seven is the store. One argument
    // each, because the other end of the move is the top of the x87 stack and there is nothing in
    // the instruction that says so. No size at all, in the sense every other row here means it:
    // the operand is ten bytes and nothing about `0xDB` is variable, so there is no prefix and no
    // `REX.W`, and `Long` is written because that is what this table calls a row with neither.
    bytes("fldt", &M, Long, &[0xDB], ext(0, 5), NO_IMM),
    bytes("fstpt", &M, Long, &[0xDB], ext(0, 7), NO_IMM),
    // The conversions, which are the same instruction reading and writing another format. The
    // width of the operand is in the opcode byte, which is the arrangement this corner of the
    // machine has instead of a prefix: `0xD9` is four bytes, `0xDD` is eight bytes of float,
    // `0xDB` is four bytes of integer and `0xDF` is eight, and the extension in the addressing
    // byte says load or store within each. That is why these rows look unlike every other row
    // here, where a width is a prefix or a REX bit and the opcode is the operation.
    bytes("flds", &M, Long, &[0xD9], ext(0, 0), NO_IMM),
    bytes("fldl", &M, Long, &[0xDD], ext(0, 0), NO_IMM),
    bytes("fildl", &M, Long, &[0xDB], ext(0, 0), NO_IMM),
    bytes("fildll", &M, Long, &[0xDF], ext(0, 5), NO_IMM),
    bytes("fstps", &M, Long, &[0xD9], ext(0, 3), NO_IMM),
    bytes("fstpl", &M, Long, &[0xDD], ext(0, 3), NO_IMM),
    bytes("fistpl", &M, Long, &[0xDB], ext(0, 3), NO_IMM),
    bytes("fistpll", &M, Long, &[0xDF], ext(0, 7), NO_IMM),
    // The arithmetic with an operand in memory, on the top of the stack. `0xD8` reads four bytes
    // of float and `0xDC` eight, and the extension is the operation in the order the stack forms
    // number them: add, multiply, compare, compare and pop, subtract, subtract the other way,
    // divide, divide the other way. The kernel's test for the Pentium division bug is `fdivl` and
    // `fmull` on two doubles.
    bytes("fadds", &M, Long, &[0xD8], ext(0, 0), NO_IMM),
    bytes("faddl", &M, Long, &[0xDC], ext(0, 0), NO_IMM),
    bytes("fmuls", &M, Long, &[0xD8], ext(0, 1), NO_IMM),
    bytes("fmull", &M, Long, &[0xDC], ext(0, 1), NO_IMM),
    bytes("fcoms", &M, Long, &[0xD8], ext(0, 2), NO_IMM),
    bytes("fcoml", &M, Long, &[0xDC], ext(0, 2), NO_IMM),
    bytes("fcomps", &M, Long, &[0xD8], ext(0, 3), NO_IMM),
    bytes("fcompl", &M, Long, &[0xDC], ext(0, 3), NO_IMM),
    bytes("fsubs", &M, Long, &[0xD8], ext(0, 4), NO_IMM),
    bytes("fsubl", &M, Long, &[0xDC], ext(0, 4), NO_IMM),
    bytes("fsubrs", &M, Long, &[0xD8], ext(0, 5), NO_IMM),
    bytes("fsubrl", &M, Long, &[0xDC], ext(0, 5), NO_IMM),
    bytes("fdivs", &M, Long, &[0xD8], ext(0, 6), NO_IMM),
    bytes("fdivl", &M, Long, &[0xDC], ext(0, 6), NO_IMM),
    bytes("fdivrs", &M, Long, &[0xD8], ext(0, 7), NO_IMM),
    bytes("fdivrl", &M, Long, &[0xDC], ext(0, 7), NO_IMM),
    // The control word, which is two bytes and is the operand of two more extensions of `0xD9`.
    bytes("fnstcw", &M, Long, &[0xD9], ext(0, 7), NO_IMM),
    bytes("fldcw", &M, Long, &[0xD9], ext(0, 5), NO_IMM),
    // The three that are also written with `fwait` in front of them, under the name that says so.
    // A program that writes the waiting name is asking to see whatever the coprocessor has already
    // decided rather than whatever it had decided when the instruction was issued, which for a
    // store of the control word or of the whole environment is the difference between reading the
    // state and racing it. libgmp's `tests/amd64call.asm` writes all three, since what it is doing
    // is looking at the state a call left behind. `fldcw` has no second name because there is
    // nothing for it to wait on: it writes the control word rather than reading it.
    waits("fstcw", &M, Long, &[0xD9], ext(0, 7)),
    // The whole environment rather than the control word alone, which is the control word, the
    // status word, the tags and where the last instruction was.
    bytes("fnstenv", &M, Long, &[0xD9], ext(0, 6), NO_IMM),
    waits("fstenv", &M, Long, &[0xD9], ext(0, 6)),
    // Putting it all back the way it starts, which takes no operand and is two constant bytes.
    bytes("fninit", &NO_ARGS, Long, &[0xDB, 0xE3], NO_MODRM, NO_IMM),
    waits("finit", &NO_ARGS, Long, &[0xDB, 0xE3], NO_MODRM),
    // The arithmetic, which is the first group of rows here with no addressing byte and no
    // register number anywhere in it. Two opcode bytes each and both of them constant: `0xDE` says
    // the operation works on two values on the stack and pops, the low three bits of the second
    // byte are the depth of the second value, and the rest of it says which operation. So the
    // depth is not encoded from an argument the way a register number is, it is part of the
    // opcode, and the argument list is here to pick the row rather than to be written out.
    //
    // A subtraction and a division come in two, because the machine cannot swap two depths and a
    // rule that wanted the other order has nowhere to put it. `0xE1` against `0xE9` and `0xF1`
    // against `0xF9` are the same operation with the operands the other way round.
    bytes("faddp", &SS, Long, &[0xDE, 0xC1], NO_MODRM, NO_IMM),
    bytes("fsubp", &SS, Long, &[0xDE, 0xE1], NO_MODRM, NO_IMM),
    bytes("fsubrp", &SS, Long, &[0xDE, 0xE9], NO_MODRM, NO_IMM),
    bytes("fmulp", &SS, Long, &[0xDE, 0xC9], NO_MODRM, NO_IMM),
    bytes("fdivp", &SS, Long, &[0xDE, 0xF1], NO_MODRM, NO_IMM),
    bytes("fdivrp", &SS, Long, &[0xDE, 0xF9], NO_MODRM, NO_IMM),
    // The two that work on the top alone, which name nothing at all: there is one value they could
    // be talking about and the opcode is the whole instruction.
    bytes("fchs", &NO_ARGS, Long, &[0xD9, 0xE0], NO_MODRM, NO_IMM),
    bytes("fabs", &NO_ARGS, Long, &[0xD9, 0xE1], NO_MODRM, NO_IMM),
    // The comparison, which writes the flags this machine's conditional jumps and byte sets read
    // rather than the status word the x87 has of its own. That is what the `i` in the middle is,
    // and it is why the compiler never writes `fnstsw`: the older way of reading an x87 comparison
    // is to save the status word into `ax` and pick the bits out, and the way this uses has been in
    // the machine since the Pentium Pro and is in the baseline.
    //
    // The `u` says a quiet NaN is an answer rather than an exception, which is the same choice
    // `ucomisd` is here for and no choice at all: the ordered comparison is a rule with an extra
    // condition on it, not a second instruction.
    bytes("fucomip", &SS, Long, &[0xDF, 0xE9], NO_MODRM, NO_IMM),
    // The pop that throws its value away, which is how the second operand of a comparison comes
    // off the stack. `0xDD 0xD8` is a store to the top itself, which is a store to where the value
    // already is, so the whole of what it does is the pop on the end of it.
    bytes("fstp", &S, Long, &[0xDD, 0xD8], NO_MODRM, NO_IMM),
    // The partial remainder and the status word, which is what gcc writes for `fmod`: `fprem`
    // takes the top down by the one under it a piece at a time and says in the status word
    // whether it is done, so the loop around it reads the word into `ax` and tests a bit. The
    // register form only ever names `ax`, so its operand picks the row and is not written out.
    bytes("fprem", &NO_ARGS, Long, &[0xD9, 0xF8], NO_MODRM, NO_IMM),
    // The rest of the instructions that take no operand and work on the top of the stack, or on
    // the top two, or push a constant. The compiler writes none of them. They are here because an
    // `asm` statement over a `long double` names them, and glibc's old `<bits/mathinline.h>` is a
    // file of exactly that: `fpatan` for `atan2l`, `fsqrt` for `sqrtl`, `fyl2x` for `logl`, and the
    // constants loaded with the instruction that has each one inside it.
    bytes("f2xm1", &NO_ARGS, Long, &[0xD9, 0xF0], NO_MODRM, NO_IMM),
    bytes("fyl2x", &NO_ARGS, Long, &[0xD9, 0xF1], NO_MODRM, NO_IMM),
    bytes("fptan", &NO_ARGS, Long, &[0xD9, 0xF2], NO_MODRM, NO_IMM),
    bytes("fpatan", &NO_ARGS, Long, &[0xD9, 0xF3], NO_MODRM, NO_IMM),
    bytes("fxtract", &NO_ARGS, Long, &[0xD9, 0xF4], NO_MODRM, NO_IMM),
    bytes("fprem1", &NO_ARGS, Long, &[0xD9, 0xF5], NO_MODRM, NO_IMM),
    bytes("fyl2xp1", &NO_ARGS, Long, &[0xD9, 0xF9], NO_MODRM, NO_IMM),
    bytes("fsqrt", &NO_ARGS, Long, &[0xD9, 0xFA], NO_MODRM, NO_IMM),
    bytes("fsincos", &NO_ARGS, Long, &[0xD9, 0xFB], NO_MODRM, NO_IMM),
    bytes("frndint", &NO_ARGS, Long, &[0xD9, 0xFC], NO_MODRM, NO_IMM),
    bytes("fscale", &NO_ARGS, Long, &[0xD9, 0xFD], NO_MODRM, NO_IMM),
    bytes("fsin", &NO_ARGS, Long, &[0xD9, 0xFE], NO_MODRM, NO_IMM),
    bytes("fcos", &NO_ARGS, Long, &[0xD9, 0xFF], NO_MODRM, NO_IMM),
    bytes("ftst", &NO_ARGS, Long, &[0xD9, 0xE4], NO_MODRM, NO_IMM),
    bytes("fxam", &NO_ARGS, Long, &[0xD9, 0xE5], NO_MODRM, NO_IMM),
    bytes("fld1", &NO_ARGS, Long, &[0xD9, 0xE8], NO_MODRM, NO_IMM),
    bytes("fldl2t", &NO_ARGS, Long, &[0xD9, 0xE9], NO_MODRM, NO_IMM),
    bytes("fldl2e", &NO_ARGS, Long, &[0xD9, 0xEA], NO_MODRM, NO_IMM),
    bytes("fldpi", &NO_ARGS, Long, &[0xD9, 0xEB], NO_MODRM, NO_IMM),
    bytes("fldlg2", &NO_ARGS, Long, &[0xD9, 0xEC], NO_MODRM, NO_IMM),
    bytes("fldln2", &NO_ARGS, Long, &[0xD9, 0xED], NO_MODRM, NO_IMM),
    bytes("fldz", &NO_ARGS, Long, &[0xD9, 0xEE], NO_MODRM, NO_IMM),
    bytes("fnstsw", &R, Long, &[0xDF, 0xE0], NO_MODRM, NO_IMM),
    bytes("fnstsw", &M, Long, &[0xDD], ext(0, 7), NO_IMM),
    // AVX-512, which is only what the intrinsics in the runtime headers write. Each row's size is
    // the mandatory prefix and the wide bit is on the `Evex`, since the two are separate bits in
    // the prefix and the element size is what the wide bit says here. A row that also has a VEX
    // form says so, and is written that way when nothing about the operands needs EVEX, which is
    // what gas does.
    evex("vmovdqu64", &VV, Single, &[0x6F], pair(0, 1), Evex::new(Map::Escape, true)),
    evex("vmovdqu64", &MV, Single, &[0x6F], pair(0, 1), Evex::new(Map::Escape, true)),
    evex("vmovdqu64", &VM, Single, &[0x7F], pair(1, 0), Evex::new(Map::Escape, true)),
    evex("vmovdqa64", &VV, Word, &[0x6F], pair(0, 1), Evex::new(Map::Escape, true)),
    evex("vmovdqa64", &MV, Word, &[0x6F], pair(0, 1), Evex::new(Map::Escape, true)),
    evex("vmovdqa64", &VM, Word, &[0x7F], pair(1, 0), Evex::new(Map::Escape, true)),
    // A store that goes around the cache, which is VEX encoded for an `xmm` or a `ymm` below the
    // sixteenth and EVEX otherwise.
    evex("vmovntdq", &VM, Word, &[0xE7], pair(1, 0), Evex::new(Map::Escape, false).or_vex(false)),
    evex("vmovdqu8", &VV, Double, &[0x6F], pair(0, 1), Evex::new(Map::Escape, false)),
    evex("vmovdqu8", &MV, Double, &[0x6F], pair(0, 1), Evex::new(Map::Escape, false)),
    evex("vmovdqu8", &VM, Double, &[0x7F], pair(1, 0), Evex::new(Map::Escape, false)),
    evex(
        "vpaddq",
        &VVV,
        Word,
        &[0xD4],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).or_vex(false),
    ),
    evex(
        "vpaddq",
        &MVV,
        Word,
        &[0xD4],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).or_vex(false),
    ),
    evex("vpandq", &VVV, Word, &[0xDB], pair(0, 2), Evex::new(Map::Escape, true).third(1)),
    evex("vpandq", &MVV, Word, &[0xDB], pair(0, 2), Evex::new(Map::Escape, true).third(1)),
    evex("vpxorq", &VVV, Word, &[0xEF], pair(0, 2), Evex::new(Map::Escape, true).third(1)),
    evex("vpxorq", &MVV, Word, &[0xEF], pair(0, 2), Evex::new(Map::Escape, true).third(1)),
    evex("vpternlogq", &IVVV, Word, &[0x25], pair(1, 3), Evex::new(Map::Escape3A, true).third(2)),
    evex("vpternlogq", &IMVV, Word, &[0x25], pair(1, 3), Evex::new(Map::Escape3A, true).third(2)),
    evex("vpopcntq", &VV, Word, &[0x55], pair(0, 1), Evex::new(Map::Escape38, true)),
    evex("vpopcntq", &MV, Word, &[0x55], pair(0, 1), Evex::new(Map::Escape38, true)),
    evex(
        "vpclmulqdq",
        &IVVV,
        Word,
        &[0x44],
        pair(1, 3),
        Evex::new(Map::Escape3A, false).third(2).or_vex(false),
    ),
    evex(
        "vpclmulqdq",
        &IMVV,
        Word,
        &[0x44],
        pair(1, 3),
        Evex::new(Map::Escape3A, false).third(2).or_vex(false),
    ),
    evex(
        "vextracti32x4",
        &IVV,
        Word,
        &[0x39],
        pair(2, 1),
        Evex::new(Map::Escape3A, false).fixed(16),
    ),
    evex(
        "vextracti32x4",
        &IVM,
        Word,
        &[0x39],
        pair(2, 1),
        Evex::new(Map::Escape3A, false).fixed(16),
    ),
    evex(
        "vextracti64x4",
        &IVV,
        Word,
        &[0x3B],
        pair(2, 1),
        Evex::new(Map::Escape3A, true).fixed(32),
    ),
    evex(
        "vextracti64x4",
        &IVM,
        Word,
        &[0x3B],
        pair(2, 1),
        Evex::new(Map::Escape3A, true).fixed(32),
    ),
    evex(
        "vbroadcasti32x4",
        &MV,
        Word,
        &[0x5A],
        pair(0, 1),
        Evex::new(Map::Escape38, false).fixed(16),
    ),
    evex("vpbroadcastb", &RV, Word, &[0x7A], pair(0, 1), Evex::new(Map::Escape38, false)),
    evex("vshufi64x2", &IVVV, Word, &[0x43], pair(1, 3), Evex::new(Map::Escape3A, true).third(2)),
    evex("vshufi64x2", &IMVV, Word, &[0x43], pair(1, 3), Evex::new(Map::Escape3A, true).third(2)),
    evex("vpshufd", &IVV, Word, &[0x70], pair(1, 2), Evex::new(Map::Escape, false).or_vex(false)),
    evex("vpshufd", &IMV, Word, &[0x70], pair(1, 2), Evex::new(Map::Escape, false).or_vex(false)),
    evex(
        "vmovq",
        &VR,
        Word,
        &[0x7E],
        pair(1, 0),
        Evex::new(Map::Escape, true).fixed(8).or_vex(true),
    ),
    evex(
        "vmovq",
        &RV,
        Word,
        &[0x6E],
        pair(0, 1),
        Evex::new(Map::Escape, true).fixed(8).or_vex(true),
    ),
    evex("vpxord", &VVV, Word, &[0xEF], pair(0, 2), Evex::new(Map::Escape, false).third(1)),
    evex("vpxord", &MVV, Word, &[0xEF], pair(0, 2), Evex::new(Map::Escape, false).third(1)),
    evex("vpternlogd", &IVVV, Word, &[0x25], pair(1, 3), Evex::new(Map::Escape3A, false).third(2)),
    evex("vpternlogd", &IMVV, Word, &[0x25], pair(1, 3), Evex::new(Map::Escape3A, false).third(2)),
    evex("vprold", &IVV, Word, &[0x72], ext(1, 1), Evex::new(Map::Escape, false).third(2)),
    evex("vprold", &IMV, Word, &[0x72], ext(1, 1), Evex::new(Map::Escape, false).third(2)),
    evex("vprord", &IVV, Word, &[0x72], ext(1, 0), Evex::new(Map::Escape, false).third(2)),
    evex("vprord", &IMV, Word, &[0x72], ext(1, 0), Evex::new(Map::Escape, false).third(2)),
    evex("vpermi2d", &VVV, Word, &[0x76], pair(0, 2), Evex::new(Map::Escape38, false).third(1)),
    evex("vpermi2d", &MVV, Word, &[0x76], pair(0, 2), Evex::new(Map::Escape38, false).third(1)),
    evex(
        "vinserti32x4",
        &IVVV,
        Word,
        &[0x38],
        pair(1, 3),
        Evex::new(Map::Escape3A, false).third(2).fixed(16),
    ),
    evex(
        "vinserti32x4",
        &IMVV,
        Word,
        &[0x38],
        pair(1, 3),
        Evex::new(Map::Escape3A, false).third(2).fixed(16),
    ),
    evex(
        "vinserti64x4",
        &IVVV,
        Word,
        &[0x3A],
        pair(1, 3),
        Evex::new(Map::Escape3A, true).third(2).fixed(32),
    ),
    evex(
        "vinserti64x4",
        &IMVV,
        Word,
        &[0x3A],
        pair(1, 3),
        Evex::new(Map::Escape3A, true).third(2).fixed(32),
    ),
    evex(
        "vbroadcasti64x2",
        &MV,
        Word,
        &[0x5A],
        pair(0, 1),
        Evex::new(Map::Escape38, true).fixed(16),
    ),
    // An unsigned compare of eight byte lanes, whose result is a mask rather than a vector.
    evex("vpcmpuq", &IVVK, Word, &[0x1E], pair(1, 3), Evex::new(Map::Escape3A, true).third(2)),
    evex("vpcmpuq", &IMVK, Word, &[0x1E], pair(1, 3), Evex::new(Map::Escape3A, true).third(2)),
    // A signed compare of byte lanes into a mask, and the mask turned back into a vector whose
    // bytes are all ones where its bits were set. lib/raid6 multiplies by two in GF(2^8) with the
    // pair of them.
    evex("vpcmpgtb", &VVK, Word, &[0x64], pair(0, 2), Evex::new(Map::Escape, false).third(1)),
    evex("vpcmpgtb", &MVK, Word, &[0x64], pair(0, 2), Evex::new(Map::Escape, false).third(1)),
    evex("vpmovm2b", &KV, Single, &[0x28], pair(0, 1), Evex::new(Map::Escape38, false)),
    // GFNI, which has a VEX form and an EVEX form and writes the wide bit in both.
    evex(
        "vgf2p8affineqb",
        &IVVV,
        Word,
        &[0xCE],
        pair(1, 3),
        Evex::new(Map::Escape3A, true).third(2).or_vex(true),
    ),
    evex(
        "vgf2p8affineqb",
        &IMVV,
        Word,
        &[0xCE],
        pair(1, 3),
        Evex::new(Map::Escape3A, true).third(2).or_vex(true),
    ),
    evex(
        "vgf2p8affineinvqb",
        &IVVV,
        Word,
        &[0xCF],
        pair(1, 3),
        Evex::new(Map::Escape3A, true).third(2).or_vex(true),
    ),
    evex(
        "vgf2p8affineinvqb",
        &IMVV,
        Word,
        &[0xCF],
        pair(1, 3),
        Evex::new(Map::Escape3A, true).third(2).or_vex(true),
    ),
    // The mask registers are VEX encoded, since moving one needs nothing EVEX adds.
    vexed("kmovq", &RK, DoubleQuad, &[0x92], pair(0, 1)),
    vexed("kmovq", &KR, DoubleQuad, &[0x93], pair(0, 1)),
    vexed("kmovd", &RK, Double, &[0x92], pair(0, 1)),
    vexed("kmovd", &KR, Double, &[0x93], pair(0, 1)),
    // Adding two masks, which is the whole length of the prefix whatever the width of the mask.
    Encoding {
        vex: Some(Vex { map: Map::Escape, vvvv: Some(1), long: true }),
        ..vexed("kaddb", &KKK, Word, &[0x4A], pair(0, 2))
    },
    // The exclusive or of two masks, which is how a mask is cleared: the zeroing in front of a
    // `ret` that `-fzero-call-used-regs=all` asks for writes `kxorw %kN, %kN, %kN` for each of the
    // eight, as gcc does. The same prefix as the add, with no mandatory prefix for the word width.
    Encoding {
        vex: Some(Vex { map: Map::Escape, vvvv: Some(1), long: true }),
        ..vexed("kxorw", &KKK, Long, &[0x47], pair(0, 2))
    },
    // AVX and AVX2, which have no EVEX form and are written with a VEX prefix whose one length
    // bit the registers named decide. Each size is the mandatory prefix, and the ones with a wide
    // bit say so the way a legacy row does.
    // The bitwise operations on packed floats, which the kernel's xor_avx.h writes on `ymm`
    // registers. They only have an EVEX form under AVX-512DQ, which nothing here asks for yet.
    avx("vandps", &VVV, Long, Map::Escape, &[0x54], Some(1), pair(0, 2)),
    avx("vandps", &MVV, Long, Map::Escape, &[0x54], Some(1), pair(0, 2)),
    avx("vandpd", &VVV, Word, Map::Escape, &[0x54], Some(1), pair(0, 2)),
    avx("vandpd", &MVV, Word, Map::Escape, &[0x54], Some(1), pair(0, 2)),
    avx("vandnps", &VVV, Long, Map::Escape, &[0x55], Some(1), pair(0, 2)),
    avx("vandnps", &MVV, Long, Map::Escape, &[0x55], Some(1), pair(0, 2)),
    avx("vandnpd", &VVV, Word, Map::Escape, &[0x55], Some(1), pair(0, 2)),
    avx("vandnpd", &MVV, Word, Map::Escape, &[0x55], Some(1), pair(0, 2)),
    avx("vorps", &VVV, Long, Map::Escape, &[0x56], Some(1), pair(0, 2)),
    avx("vorps", &MVV, Long, Map::Escape, &[0x56], Some(1), pair(0, 2)),
    avx("vorpd", &VVV, Word, Map::Escape, &[0x56], Some(1), pair(0, 2)),
    avx("vorpd", &MVV, Word, Map::Escape, &[0x56], Some(1), pair(0, 2)),
    // AVX-512 has a form of its own, which `-fzero-call-used-regs=all` writes to clear `xmm16` to
    // `xmm31` as gcc does. The VEX form is still the one written whenever it can be, as gas does.
    evex(
        "vxorps",
        &VVV,
        Long,
        &[0x57],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).or_vex(false),
    ),
    avx("vxorps", &MVV, Long, Map::Escape, &[0x57], Some(1), pair(0, 2)),
    avx("vxorpd", &VVV, Word, Map::Escape, &[0x57], Some(1), pair(0, 2)),
    avx("vxorpd", &MVV, Word, Map::Escape, &[0x57], Some(1), pair(0, 2)),
    avx("vpxor", &VVV, Word, Map::Escape, &[0xEF], Some(1), pair(0, 2)),
    avx("vpxor", &MVV, Word, Map::Escape, &[0xEF], Some(1), pair(0, 2)),
    avx("vpor", &VVV, Word, Map::Escape, &[0xEB], Some(1), pair(0, 2)),
    avx("vpor", &MVV, Word, Map::Escape, &[0xEB], Some(1), pair(0, 2)),
    avx("vpand", &VVV, Word, Map::Escape, &[0xDB], Some(1), pair(0, 2)),
    avx("vpand", &MVV, Word, Map::Escape, &[0xDB], Some(1), pair(0, 2)),
    avx("vpandn", &VVV, Word, Map::Escape, &[0xDF], Some(1), pair(0, 2)),
    avx("vpandn", &MVV, Word, Map::Escape, &[0xDF], Some(1), pair(0, 2)),
    evex(
        "vpaddb",
        &VVV,
        Word,
        &[0xFC],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).or_vex(false),
    ),
    evex(
        "vpaddb",
        &MVV,
        Word,
        &[0xFC],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).or_vex(false),
    ),
    evex(
        "vpaddd",
        &VVV,
        Word,
        &[0xFE],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).or_vex(false),
    ),
    evex(
        "vpaddd",
        &MVV,
        Word,
        &[0xFE],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).or_vex(false),
    ),
    evex(
        "vpsubd",
        &VVV,
        Word,
        &[0xFA],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).or_vex(false),
    ),
    evex(
        "vpsubd",
        &MVV,
        Word,
        &[0xFA],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).or_vex(false),
    ),
    evex(
        "vpsubq",
        &VVV,
        Word,
        &[0xFB],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).or_vex(false),
    ),
    evex(
        "vpsubq",
        &MVV,
        Word,
        &[0xFB],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).or_vex(false),
    ),
    evex(
        "vpmuludq",
        &VVV,
        Word,
        &[0xF4],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).or_vex(false),
    ),
    evex(
        "vpmuludq",
        &MVV,
        Word,
        &[0xF4],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).or_vex(false),
    ),
    avx("vpcmpeqd", &VVV, Word, Map::Escape, &[0x76], Some(1), pair(0, 2)),
    avx("vpcmpeqd", &MVV, Word, Map::Escape, &[0x76], Some(1), pair(0, 2)),
    avx("vpcmpgtb", &VVV, Word, Map::Escape, &[0x64], Some(1), pair(0, 2)),
    avx("vpcmpgtb", &MVV, Word, Map::Escape, &[0x64], Some(1), pair(0, 2)),
    evex(
        "vpunpckhdq",
        &VVV,
        Word,
        &[0x6A],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).or_vex(false),
    ),
    evex(
        "vpunpckhdq",
        &MVV,
        Word,
        &[0x6A],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).or_vex(false),
    ),
    evex(
        "vpunpckldq",
        &VVV,
        Word,
        &[0x62],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).or_vex(false),
    ),
    evex(
        "vpunpckldq",
        &MVV,
        Word,
        &[0x62],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).or_vex(false),
    ),
    evex(
        "vpunpckhqdq",
        &VVV,
        Word,
        &[0x6D],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).or_vex(false),
    ),
    evex(
        "vpunpckhqdq",
        &MVV,
        Word,
        &[0x6D],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).or_vex(false),
    ),
    evex(
        "vpunpcklqdq",
        &VVV,
        Word,
        &[0x6C],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).or_vex(false),
    ),
    evex(
        "vpunpcklqdq",
        &MVV,
        Word,
        &[0x6C],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).or_vex(false),
    ),
    evex(
        "vpslld",
        &VVV,
        Word,
        &[0xF2],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).fixed(16).or_vex(false),
    ),
    evex(
        "vpslld",
        &MVV,
        Word,
        &[0xF2],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).fixed(16).or_vex(false),
    ),
    evex(
        "vpsrld",
        &VVV,
        Word,
        &[0xD2],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).fixed(16).or_vex(false),
    ),
    evex(
        "vpsrld",
        &MVV,
        Word,
        &[0xD2],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).fixed(16).or_vex(false),
    ),
    evex(
        "vpsrad",
        &VVV,
        Word,
        &[0xE2],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).fixed(16).or_vex(false),
    ),
    evex(
        "vpsrad",
        &MVV,
        Word,
        &[0xE2],
        pair(0, 2),
        Evex::new(Map::Escape, false).third(1).fixed(16).or_vex(false),
    ),
    evex(
        "vpsllq",
        &VVV,
        Word,
        &[0xF3],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).fixed(16).or_vex(false),
    ),
    evex(
        "vpsllq",
        &MVV,
        Word,
        &[0xF3],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).fixed(16).or_vex(false),
    ),
    evex(
        "vpsrlq",
        &VVV,
        Word,
        &[0xD3],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).fixed(16).or_vex(false),
    ),
    evex(
        "vpsrlq",
        &MVV,
        Word,
        &[0xD3],
        pair(0, 2),
        Evex::new(Map::Escape, true).third(1).fixed(16).or_vex(false),
    ),
    evex(
        "vpshufb",
        &VVV,
        Word,
        &[0x00],
        pair(0, 2),
        Evex::new(Map::Escape38, false).third(1).or_vex(false),
    ),
    evex(
        "vpshufb",
        &MVV,
        Word,
        &[0x00],
        pair(0, 2),
        Evex::new(Map::Escape38, false).third(1).or_vex(false),
    ),
    avx("vpcmpeqq", &VVV, Word, Map::Escape38, &[0x29], Some(1), pair(0, 2)),
    avx("vpcmpeqq", &MVV, Word, Map::Escape38, &[0x29], Some(1), pair(0, 2)),
    evex(
        "vaesenc",
        &VVV,
        Word,
        &[0xDC],
        pair(0, 2),
        Evex::new(Map::Escape38, false).third(1).or_vex(false),
    ),
    evex(
        "vaesenc",
        &MVV,
        Word,
        &[0xDC],
        pair(0, 2),
        Evex::new(Map::Escape38, false).third(1).or_vex(false),
    ),
    evex(
        "vaesenclast",
        &VVV,
        Word,
        &[0xDD],
        pair(0, 2),
        Evex::new(Map::Escape38, false).third(1).or_vex(false),
    ),
    evex(
        "vaesenclast",
        &MVV,
        Word,
        &[0xDD],
        pair(0, 2),
        Evex::new(Map::Escape38, false).third(1).or_vex(false),
    ),
    evex(
        "vaesdec",
        &VVV,
        Word,
        &[0xDE],
        pair(0, 2),
        Evex::new(Map::Escape38, false).third(1).or_vex(false),
    ),
    evex(
        "vaesdec",
        &MVV,
        Word,
        &[0xDE],
        pair(0, 2),
        Evex::new(Map::Escape38, false).third(1).or_vex(false),
    ),
    evex(
        "vaesdeclast",
        &VVV,
        Word,
        &[0xDF],
        pair(0, 2),
        Evex::new(Map::Escape38, false).third(1).or_vex(false),
    ),
    evex(
        "vaesdeclast",
        &MVV,
        Word,
        &[0xDF],
        pair(0, 2),
        Evex::new(Map::Escape38, false).third(1).or_vex(false),
    ),
    evex("vpabsb", &VV, Word, &[0x1C], pair(0, 1), Evex::new(Map::Escape38, false).or_vex(false)),
    evex("vpabsb", &MV, Word, &[0x1C], pair(0, 1), Evex::new(Map::Escape38, false).or_vex(false)),
    avx("vptest", &VV, Word, Map::Escape38, &[0x17], None, pair(0, 1)),
    avx("vptest", &MV, Word, Map::Escape38, &[0x17], None, pair(0, 1)),
    // The widening moves, zero extended and sign extended, from the low part of a register or
    // from memory. The kernel's BLAKE2s widens message bytes with `vpmovzxbd`.
    avx("vpmovsxbw", &VV, Word, Map::Escape38, &[0x20], None, pair(0, 1)),
    avx("vpmovsxbw", &MV, Word, Map::Escape38, &[0x20], None, pair(0, 1)),
    avx("vpmovsxbd", &VV, Word, Map::Escape38, &[0x21], None, pair(0, 1)),
    avx("vpmovsxbd", &MV, Word, Map::Escape38, &[0x21], None, pair(0, 1)),
    avx("vpmovsxbq", &VV, Word, Map::Escape38, &[0x22], None, pair(0, 1)),
    avx("vpmovsxbq", &MV, Word, Map::Escape38, &[0x22], None, pair(0, 1)),
    avx("vpmovsxwd", &VV, Word, Map::Escape38, &[0x23], None, pair(0, 1)),
    avx("vpmovsxwd", &MV, Word, Map::Escape38, &[0x23], None, pair(0, 1)),
    avx("vpmovsxwq", &VV, Word, Map::Escape38, &[0x24], None, pair(0, 1)),
    avx("vpmovsxwq", &MV, Word, Map::Escape38, &[0x24], None, pair(0, 1)),
    avx("vpmovsxdq", &VV, Word, Map::Escape38, &[0x25], None, pair(0, 1)),
    avx("vpmovsxdq", &MV, Word, Map::Escape38, &[0x25], None, pair(0, 1)),
    avx("vpmovzxbw", &VV, Word, Map::Escape38, &[0x30], None, pair(0, 1)),
    avx("vpmovzxbw", &MV, Word, Map::Escape38, &[0x30], None, pair(0, 1)),
    avx("vpmovzxbd", &VV, Word, Map::Escape38, &[0x31], None, pair(0, 1)),
    avx("vpmovzxbd", &MV, Word, Map::Escape38, &[0x31], None, pair(0, 1)),
    avx("vpmovzxbq", &VV, Word, Map::Escape38, &[0x32], None, pair(0, 1)),
    avx("vpmovzxbq", &MV, Word, Map::Escape38, &[0x32], None, pair(0, 1)),
    avx("vpmovzxwd", &VV, Word, Map::Escape38, &[0x33], None, pair(0, 1)),
    avx("vpmovzxwd", &MV, Word, Map::Escape38, &[0x33], None, pair(0, 1)),
    avx("vpmovzxwq", &VV, Word, Map::Escape38, &[0x34], None, pair(0, 1)),
    avx("vpmovzxwq", &MV, Word, Map::Escape38, &[0x34], None, pair(0, 1)),
    avx("vpmovzxdq", &VV, Word, Map::Escape38, &[0x35], None, pair(0, 1)),
    avx("vpmovzxdq", &MV, Word, Map::Escape38, &[0x35], None, pair(0, 1)),
    evex(
        "vpbroadcastd",
        &VV,
        Word,
        &[0x58],
        pair(0, 1),
        Evex::new(Map::Escape38, false).fixed(4).or_vex(false),
    ),
    evex(
        "vpbroadcastd",
        &MV,
        Word,
        &[0x58],
        pair(0, 1),
        Evex::new(Map::Escape38, false).fixed(4).or_vex(false),
    ),
    evex(
        "vpbroadcastq",
        &VV,
        Word,
        &[0x59],
        pair(0, 1),
        Evex::new(Map::Escape38, true).fixed(8).or_vex(false),
    ),
    evex(
        "vpbroadcastq",
        &MV,
        Word,
        &[0x59],
        pair(0, 1),
        Evex::new(Map::Escape38, true).fixed(8).or_vex(false),
    ),
    evex(
        "vbroadcastss",
        &VV,
        Word,
        &[0x18],
        pair(0, 1),
        Evex::new(Map::Escape38, false).fixed(4).or_vex(false),
    ),
    evex(
        "vbroadcastss",
        &MV,
        Word,
        &[0x18],
        pair(0, 1),
        Evex::new(Map::Escape38, false).fixed(4).or_vex(false),
    ),
    avx("vaesimc", &VV, Word, Map::Escape38, &[0xDB], None, pair(0, 1)),
    avx("vaesimc", &MV, Word, Map::Escape38, &[0xDB], None, pair(0, 1)),
    avx("vbroadcasti128", &MV, Word, Map::Escape38, &[0x5A], None, pair(0, 1)),
    evex(
        "vpbroadcastb",
        &VV,
        Word,
        &[0x78],
        pair(0, 1),
        Evex::new(Map::Escape38, false).fixed(1).or_vex(false),
    ),
    evex(
        "vpbroadcastb",
        &MV,
        Word,
        &[0x78],
        pair(0, 1),
        Evex::new(Map::Escape38, false).fixed(1).or_vex(false),
    ),
    // The low eight bytes of a vector, which reads one way and stores another.
    avx("vmovq", &VV, Single, Map::Escape, &[0x7E], None, pair(0, 1)),
    avx("vmovq", &MV, Single, Map::Escape, &[0x7E], None, pair(0, 1)),
    avx("vmovq", &VM, Word, Map::Escape, &[0xD6], None, pair(1, 0)),
    avx("vmovdqu", &VV, Single, Map::Escape, &[0x6F], None, pair(0, 1)),
    avx("vmovdqu", &MV, Single, Map::Escape, &[0x6F], None, pair(0, 1)),
    avx("vmovdqu", &VM, Single, Map::Escape, &[0x7F], None, pair(1, 0)),
    avx("vmovdqa", &VV, Word, Map::Escape, &[0x6F], None, pair(0, 1)),
    avx("vmovdqa", &MV, Word, Map::Escape, &[0x6F], None, pair(0, 1)),
    avx("vmovdqa", &VM, Word, Map::Escape, &[0x7F], None, pair(1, 0)),
    avx("vmovups", &VV, Long, Map::Escape, &[0x10], None, pair(0, 1)),
    avx("vmovups", &MV, Long, Map::Escape, &[0x10], None, pair(0, 1)),
    avx("vmovups", &VM, Long, Map::Escape, &[0x11], None, pair(1, 0)),
    avx("vmovapd", &VV, Word, Map::Escape, &[0x28], None, pair(0, 1)),
    avx("vmovapd", &MV, Word, Map::Escape, &[0x28], None, pair(0, 1)),
    avx("vmovapd", &VM, Word, Map::Escape, &[0x29], None, pair(1, 0)),
    avx("vmovaps", &VV, Long, Map::Escape, &[0x28], None, pair(0, 1)),
    avx("vmovaps", &MV, Long, Map::Escape, &[0x28], None, pair(0, 1)),
    avx("vmovaps", &VM, Long, Map::Escape, &[0x29], None, pair(1, 0)),
    avx("vmovupd", &VV, Word, Map::Escape, &[0x10], None, pair(0, 1)),
    avx("vmovupd", &MV, Word, Map::Escape, &[0x10], None, pair(0, 1)),
    avx("vmovupd", &VM, Word, Map::Escape, &[0x11], None, pair(1, 0)),
    // The same four moves EVEX encoded, which is only taken when the operands need it, a `zmm` or
    // a register numbered sixteen or above, or a mask. They sit after the VEX rows so those win
    // otherwise, and the VEX rows keep the store form swap gas does between two registers.
    evex("vmovups", &VV, Long, &[0x10], pair(0, 1), Evex::new(Map::Escape, false)),
    evex("vmovups", &MV, Long, &[0x10], pair(0, 1), Evex::new(Map::Escape, false)),
    evex("vmovups", &VM, Long, &[0x11], pair(1, 0), Evex::new(Map::Escape, false)),
    evex("vmovapd", &VV, Word, &[0x28], pair(0, 1), Evex::new(Map::Escape, true)),
    evex("vmovapd", &MV, Word, &[0x28], pair(0, 1), Evex::new(Map::Escape, true)),
    evex("vmovapd", &VM, Word, &[0x29], pair(1, 0), Evex::new(Map::Escape, true)),
    evex("vmovaps", &VV, Long, &[0x28], pair(0, 1), Evex::new(Map::Escape, false)),
    evex("vmovaps", &MV, Long, &[0x28], pair(0, 1), Evex::new(Map::Escape, false)),
    evex("vmovaps", &VM, Long, &[0x29], pair(1, 0), Evex::new(Map::Escape, false)),
    evex("vmovupd", &VV, Word, &[0x10], pair(0, 1), Evex::new(Map::Escape, true)),
    evex("vmovupd", &MV, Word, &[0x10], pair(0, 1), Evex::new(Map::Escape, true)),
    evex("vmovupd", &VM, Word, &[0x11], pair(1, 0), Evex::new(Map::Escape, true)),
    avx("vmovd", &RV, Word, Map::Escape, &[0x6E], None, pair(0, 1)),
    avx("vmovd", &MV, Word, Map::Escape, &[0x6E], None, pair(0, 1)),
    avx("vmovd", &VR, Word, Map::Escape, &[0x7E], None, pair(1, 0)),
    avx("vmovd", &VM, Word, Map::Escape, &[0x7E], None, pair(1, 0)),
    evex(
        "vpalignr",
        &IVVV,
        Word,
        &[0x0F],
        pair(1, 3),
        Evex::new(Map::Escape3A, false).third(2).or_vex(false),
    ),
    evex(
        "vpalignr",
        &IMVV,
        Word,
        &[0x0F],
        pair(1, 3),
        Evex::new(Map::Escape3A, false).third(2).or_vex(false),
    ),
    // A blend whose selector is a fourth register, named in the top half of the immediate byte.
    Encoding {
        imm: ImmSize::Is4,
        ..avx("vpblendvb", &VVVV, Word, Map::Escape3A, &[0x4C], Some(2), pair(1, 3))
    },
    Encoding {
        imm: ImmSize::Is4,
        ..avx("vpblendvb", &VMVV, Word, Map::Escape3A, &[0x4C], Some(2), pair(1, 3))
    },
    avx("vpblendd", &IVVV, Word, Map::Escape3A, &[0x02], Some(2), pair(1, 3)),
    avx("vpblendd", &IMVV, Word, Map::Escape3A, &[0x02], Some(2), pair(1, 3)),
    avx("vinserti128", &IVVV, Word, Map::Escape3A, &[0x38], Some(2), pair(1, 3)),
    avx("vinserti128", &IMVV, Word, Map::Escape3A, &[0x38], Some(2), pair(1, 3)),
    avx("vinsertf128", &IVVV, Word, Map::Escape3A, &[0x18], Some(2), pair(1, 3)),
    avx("vinsertf128", &IMVV, Word, Map::Escape3A, &[0x18], Some(2), pair(1, 3)),
    avx("vperm2i128", &IVVV, Word, Map::Escape3A, &[0x46], Some(2), pair(1, 3)),
    avx("vperm2i128", &IMVV, Word, Map::Escape3A, &[0x46], Some(2), pair(1, 3)),
    avx("vperm2f128", &IVVV, Word, Map::Escape3A, &[0x06], Some(2), pair(1, 3)),
    avx("vperm2f128", &IMVV, Word, Map::Escape3A, &[0x06], Some(2), pair(1, 3)),
    evex(
        "vpslld",
        &IVV,
        Word,
        &[0x72],
        ext(1, 6),
        Evex::new(Map::Escape, false).third(2).or_vex(false),
    ),
    evex(
        "vpsrld",
        &IVV,
        Word,
        &[0x72],
        ext(1, 2),
        Evex::new(Map::Escape, false).third(2).or_vex(false),
    ),
    evex(
        "vpsrad",
        &IVV,
        Word,
        &[0x72],
        ext(1, 4),
        Evex::new(Map::Escape, false).third(2).or_vex(false),
    ),
    evex(
        "vpsraw",
        &IVV,
        Word,
        &[0x71],
        ext(1, 4),
        Evex::new(Map::Escape, false).third(2).or_vex(false),
    ),
    evex(
        "vpsllq",
        &IVV,
        Word,
        &[0x73],
        ext(1, 6),
        Evex::new(Map::Escape, true).third(2).or_vex(false),
    ),
    evex(
        "vpsrlq",
        &IVV,
        Word,
        &[0x73],
        ext(1, 2),
        Evex::new(Map::Escape, true).third(2).or_vex(false),
    ),
    evex(
        "vpslldq",
        &IVV,
        Word,
        &[0x73],
        ext(1, 7),
        Evex::new(Map::Escape, false).third(2).or_vex(false),
    ),
    evex(
        "vpsrldq",
        &IVV,
        Word,
        &[0x73],
        ext(1, 3),
        Evex::new(Map::Escape, false).third(2).or_vex(false),
    ),
    avx("vextracti128", &IVV, Word, Map::Escape3A, &[0x39], None, pair(2, 1)),
    avx("vextracti128", &IVM, Word, Map::Escape3A, &[0x39], None, pair(2, 1)),
    avx("vpextrq", &IVR, WordQuad, Map::Escape3A, &[0x16], None, pair(2, 1)),
    avx("vpextrq", &IVM, WordQuad, Map::Escape3A, &[0x16], None, pair(2, 1)),
    avx("vpinsrq", &IRVV, WordQuad, Map::Escape3A, &[0x22], Some(2), pair(1, 3)),
    avx("vpinsrq", &IMVV, WordQuad, Map::Escape3A, &[0x22], Some(2), pair(1, 3)),
    // The narrower lanes of the same two, which the kernel's CRC code writes through a macro that
    // puts a `v` in front of the SSE name when it is built for AVX.
    avx("vpextrb", &IVR, Word, Map::Escape3A, &[0x14], None, pair(2, 1)),
    avx("vpextrb", &IVM, Word, Map::Escape3A, &[0x14], None, pair(2, 1)),
    avx("vpextrw", &IVR, Word, Map::Escape, &[0xC5], None, pair(1, 2)),
    avx("vpextrw", &IVM, Word, Map::Escape3A, &[0x15], None, pair(2, 1)),
    avx("vpextrd", &IVR, Word, Map::Escape3A, &[0x16], None, pair(2, 1)),
    avx("vpextrd", &IVM, Word, Map::Escape3A, &[0x16], None, pair(2, 1)),
    avx("vpinsrb", &IRVV, Word, Map::Escape3A, &[0x20], Some(2), pair(1, 3)),
    avx("vpinsrb", &IMVV, Word, Map::Escape3A, &[0x20], Some(2), pair(1, 3)),
    avx("vpinsrw", &IRVV, Word, Map::Escape, &[0xC4], Some(2), pair(1, 3)),
    avx("vpinsrw", &IMVV, Word, Map::Escape, &[0xC4], Some(2), pair(1, 3)),
    avx("vpinsrd", &IRVV, Word, Map::Escape3A, &[0x22], Some(2), pair(1, 3)),
    avx("vpinsrd", &IMVV, Word, Map::Escape3A, &[0x22], Some(2), pair(1, 3)),
    avx("vzeroupper", &NO_ARGS, Long, Map::Escape, &[0x77], None, NO_MODRM),
    Encoding {
        vex: Some(Vex { map: Map::Escape, vvvv: None, long: true }),
        ..avx("vzeroall", &NO_ARGS, Long, Map::Escape, &[0x77], None, NO_MODRM)
    },
    // BMI2's rotate that leaves the flags alone, and BMI's and-not, both VEX encoded.
    avx("rorxl", &IRR, Double, Map::Escape3A, &[0xF0], None, pair(1, 2)),
    avx("rorxl", &IMR, Double, Map::Escape3A, &[0xF0], None, pair(1, 2)),
    avx("rorxq", &IRR, DoubleQuad, Map::Escape3A, &[0xF0], None, pair(1, 2)),
    avx("rorxq", &IMR, DoubleQuad, Map::Escape3A, &[0xF0], None, pair(1, 2)),
    avx("andnl", &RRR, Long, Map::Escape38, &[0xF2], Some(1), pair(0, 2)),
    avx("andnl", &MRR, Long, Map::Escape38, &[0xF2], Some(1), pair(0, 2)),
    avx("andnq", &RRR, Quad, Map::Escape38, &[0xF2], Some(1), pair(0, 2)),
    avx("andnq", &MRR, Quad, Map::Escape38, &[0xF2], Some(1), pair(0, 2)),
    // BMI2's clear of the bits above an index, which is the first argument and goes in `vvvv`.
    avx("bzhil", &RRR, Long, Map::Escape38, &[0xF5], Some(0), pair(1, 2)),
    avx("bzhil", &RMR, Long, Map::Escape38, &[0xF5], Some(0), pair(1, 2)),
    avx("bzhiq", &RRR, Quad, Map::Escape38, &[0xF5], Some(0), pair(1, 2)),
    avx("bzhiq", &RMR, Quad, Map::Escape38, &[0xF5], Some(0), pair(1, 2)),
];

/// The rows only thirty two bit mode has, which are looked at in front of the shared table there
/// and not at all in sixty four bit mode.
///
/// Two kinds. `inc` and `dec` of a sixteen or thirty two bit register have a one byte form,
/// `0x40` plus the register and `0x48` plus the register, which sixty four bit mode gave up to make
/// room for the REX byte, and gas writes it wherever it can. And a push or a pop of four bytes,
/// which is what `pushl` and `popl` are: the same opcodes as `pushq` and `popq`, since each mode
/// pushes its own width without being told, under the name that says the width they push here.
static ONLY32: &[Encoding] = &[
    bytes("incw", &R, Word, &[0x40], plus(0), NO_IMM),
    bytes("incl", &R, Long, &[0x40], plus(0), NO_IMM),
    bytes("decw", &R, Word, &[0x48], plus(0), NO_IMM),
    bytes("decl", &R, Long, &[0x48], plus(0), NO_IMM),
    bytes("pushl", &R, Long, &[0x50], plus(0), NO_IMM),
    bytes("popl", &R, Long, &[0x58], plus(0), NO_IMM),
    bytes("pushl", &M, Long, &[0xFF], ext(0, 6), NO_IMM),
    bytes("popl", &M, Long, &[0x8F], ext(0, 0), NO_IMM),
    takes("pushl", &I, Signed8, Long, &[0x6A], NO_MODRM, ImmSize::Ib),
    takes("pushl", &I, Fits::Long, Long, &[0x68], NO_MODRM, ImmSize::Id),
    bytes("pushfl", &NO_ARGS, Long, &[0x9C], NO_MODRM, NO_IMM),
    bytes("popfl", &NO_ARGS, Long, &[0x9D], NO_MODRM, NO_IMM),
    // The descriptor table loads and stores with the suffix that says six bytes, which is what
    // they move in this mode. The EFI mixed mode entry in the kernel saves the firmware's table
    // with `sgdtl`.
    bytes("sgdtl", &M, Long, &[0x0F, 0x01], ext(0, 0), NO_IMM),
    bytes("sidtl", &M, Long, &[0x0F, 0x01], ext(0, 1), NO_IMM),
    bytes("lgdtl", &M, Long, &[0x0F, 0x01], ext(0, 2), NO_IMM),
    bytes("lidtl", &M, Long, &[0x0F, 0x01], ext(0, 3), NO_IMM),
];

/// The mnemonics of the shared table that move eight bytes in sixty four bit mode without a size
/// that says so, and so are not in thirty two bit mode at all. Their rows are [`Size::Long`]
/// because nothing in front of the opcode says sixty four bits, which is why they are named here
/// rather than caught by [`Size::wide`]; the thirty two bit instructions with the same bytes are
/// the rows of [`ONLY32`].
const ONLY64: [&str; 4] = ["pushq", "popq", "pushfq", "popfq"];

/// The encoding of the instruction of that mnemonic, given those arguments and that immediate.
///
/// `None` for a mnemonic this target does not encode, for one it does encode with arguments that
/// are not the ones it takes, and for an immediate no form of it can carry.
///
/// The immediate is asked for because it is part of which instruction this is: two families here
/// have a shorter encoding for a small number, and every one of them has a largest number it can
/// hold. Pass zero for an instruction that carries none, which is what the first row of every
/// such mnemonic accepts anyway.
#[must_use]
pub fn encoding(mnemonic: &str, args: &[Kind], imm: i64) -> Option<&'static Encoding> {
    encoding_in(Mode::Bits64, mnemonic, args, imm)
}

/// [`encoding`] in that mode.
///
/// In thirty two bit mode the rows only it has come first, so `incl %eax` is the one byte form, and
/// the push and pop that move eight bytes are not found. A row that is found may still be one the
/// mode cannot write, a sixty four bit operand size or a register it has no name for, and that is
/// [`encode_in`]'s to refuse, since it is the one that sees the registers.
#[must_use]
pub fn encoding_in(
    mode: Mode,
    mnemonic: &str,
    args: &[Kind],
    imm: i64,
) -> Option<&'static Encoding> {
    rows_in(mode, mnemonic, args).find(|row| row.fits.holds(seen(row, imm)))
}

/// The immediate as a row that sign extends a byte sees it.
///
/// A thirty two bit instruction only has thirty two bits of immediate, so `andl $0xffffffff` and
/// `andl $-1` are the same instruction and gas writes both with the one byte form. The number is
/// read at the width of the row before asking whether a byte holds it, and the byte written is
/// its low eight bits either way. The same goes for sixteen bits.
fn seen(row: &Encoding, imm: i64) -> i64 {
    match (row.fits, row.size) {
        (Signed8, Long) => u32::try_from(imm).map_or(imm, |bits| i64::from(bits as i32)),
        (Signed8, Word) => u16::try_from(imm).map_or(imm, |bits| i64::from(bits as i16)),
        _ => imm,
    }
}

/// Every row of that mnemonic with those arguments in that mode, in the order they are tried.
fn rows_in<'a>(
    mode: Mode,
    mnemonic: &'a str,
    args: &'a [Kind],
) -> impl Iterator<Item = &'static Encoding> + 'a {
    let (only, shared): (&'static [Encoding], bool) = match mode {
        Mode::Bits64 => (&[], true),
        Mode::Bits32 => (ONLY32, !ONLY64.contains(&mnemonic)),
    };
    only.iter()
        .filter(move |row| row.mnemonic == mnemonic && row.args == args)
        .chain(rows(mnemonic, args).filter(move |_| shared))
}

/// Every row of that mnemonic with those arguments, in the order they are written.
fn rows<'a>(mnemonic: &'a str, args: &'a [Kind]) -> impl Iterator<Item = &'static Encoding> + 'a {
    static AT: LazyLock<named::Names<Vec<usize>>> =
        LazyLock::new(|| named::every(ENCODINGS, |row| row.mnemonic));
    AT.get(mnemonic)
        .into_iter()
        .flatten()
        .map(|&at| &ENCODINGS[at])
        .filter(move |row| row.args == args)
}

/// An address, with everything about it already decided.
///
/// The machine IR's addressing mode names its registers by where they are in the operand vector
/// and this names them outright, because by here the allocator has run and there is an answer.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
pub struct Addr {
    /// The register the address starts from, if there is one.
    pub base: Option<PhysReg>,
    /// The register added to it, if there is one. It may not be the stack pointer, which is the
    /// number the encoding uses to say there is no index at all.
    pub index: Option<PhysReg>,
    /// What the index is multiplied by, which is one, two, four or eight. Ignored when there is
    /// no index.
    pub scale: u8,
    /// The constant added to the rest of it.
    pub disp: i32,
    /// Whether the address is counted from the end of the instruction rather than from a
    /// register, which is how a global is reached in position independent code and is the only
    /// way this compiler reaches one. It names no register, so it has neither base nor index.
    pub rip: bool,
    /// Which storage the address is in, when it is not the flat one. See [`Segment`].
    pub segment: Option<Segment>,
    /// Whether the displacement is a number the linker writes, which makes it four bytes however
    /// small it is now. A section relative offset added to a register is one case, and the address
    /// of a name with or without registers added to it, which code that is not position
    /// independent writes, is the other. The rip relative one is four bytes anyway.
    pub linked: bool,
}

/// What one argument of an instruction turned out to be.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Value {
    /// A register, and how much of it the instruction reads or writes.
    ///
    /// The width is here because it is what decides whether a REX byte is needed at all: the four
    /// registers numbered four to seven are `ah`, `ch`, `dh` and `bh` as bytes without one and
    /// `spl`, `bpl`, `sil` and `dil` with one, so a byte instruction naming one of the second set
    /// carries a REX byte that says nothing else.
    Reg(PhysReg, Width),
    /// A vector register, all of which every instruction here that names one reads or writes.
    ///
    /// [`Value::Reg`] in the other file, and separate for the reason [`Kind::Vec`] gives. There is
    /// no width, because there is nothing narrower than the whole of one to name: an instruction
    /// that works on the low four bytes of a vector register is a different opcode rather than the
    /// same opcode at another width, which is what `movss` and `movsd` are.
    Xmm(PhysReg),
    /// A vector register by number and by the length it is named at, which is what an AVX-512
    /// instruction names.
    ///
    /// Separate from [`Value::Xmm`] because the register allocator only hands out the sixteen
    /// registers SSE has, and these reach the thirty two AVX-512 has, at three lengths. Only the
    /// EVEX rows take one, and `xmm0` to `xmm15` written as [`Value::Xmm`] mean the same there.
    Vector(u8, Length),
    /// One of the mask registers, `k0` to `k7`.
    Mask(u8),
    /// The byte above the low byte of one of the first four registers, which on this machine is
    /// only ever `ah`.
    ///
    /// It is numbered like `spl` and told apart from it by the instruction having no REX byte,
    /// which is why an instruction with one of these may name no register that needs one.
    High(PhysReg),
    /// An address.
    Mem(Addr),
    /// The number an immediate carries.
    Imm(i64),
    /// Somewhere else in the program, whose distance from here is not known yet.
    Dest,
    /// A position on the x87 stack, which carries no number because nothing is written from it.
    ///
    /// [`Kind::Stack`] says the rest. The depth the instruction works at is in the opcode, and
    /// which depth that is comes from the text table, so what is left here is the fact that an
    /// argument was there at all, which is what the lookup needs.
    Stack,
    /// A control register, `cr0` to `cr15`, by number.
    Control(u8),
    /// A debug register, `dr0` to `dr15`, by number.
    Debug(u8),
    /// A segment register.
    Seg(Segment),
}

impl Value {
    /// What kind of argument this is, which is half of what picks an encoding.
    #[must_use]
    pub fn kind(self) -> Kind {
        match self {
            Value::Control(_) => Kind::Control,
            Value::Debug(_) => Kind::Debug,
            Value::Seg(_) => Kind::Seg,
            Value::Reg(_, _) | Value::High(_) => Kind::Reg,
            Value::Xmm(_) | Value::Vector(_, _) => Kind::Vec,
            Value::Mask(_) => Kind::Mask,
            Value::Mem(_) => Kind::Mem,
            Value::Imm(_) => Kind::Imm,
            Value::Dest => Kind::Dest,
            Value::Stack => Kind::Stack,
        }
    }
}

/// Where in an instruction something the encoder could not know goes.
///
/// All three are offsets into the buffer the instruction was written to rather than into the
/// instruction, since what the caller has to do with either is patch the buffer or record a
/// relocation against it.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
pub struct Holes {
    /// Where the four bytes a jump or a call leaves for the distance to its target begin.
    pub dest: Option<usize>,
    /// Where the four bytes an address counted from the end of the instruction leaves for its
    /// displacement begin.
    pub rip: Option<usize>,
    /// Where the four bytes of displacement of an address counted from a register begin, when
    /// the linker is the one to fill them in. See [`Addr::linked`].
    pub disp: Option<usize>,
}

/// Why an instruction could not be encoded.
///
/// Every one of these is a bug in the compiler rather than anything a program could ask for, so
/// they carry enough to say which instruction it was and nothing more.
#[derive(Debug, Clone, PartialEq, Eq)]
pub enum Error {
    /// Nothing here encodes that mnemonic with those arguments.
    Unwritten {
        /// The mnemonic that was asked for.
        mnemonic: String,
        /// What its arguments were.
        args: Vec<Kind>,
    },
    /// An immediate no form of that instruction can carry, which the machine cannot write and
    /// which would be a different number if it were cut down to fit.
    Immediate {
        /// The mnemonic that was asked for.
        mnemonic: String,
        /// The number that would not fit.
        imm: i64,
    },
    /// An instruction naming `ah` and also a register that cannot be named without a REX byte,
    /// which is a pair the encoding has no way to write.
    Crowded {
        /// The mnemonic that was asked for.
        mnemonic: String,
    },
    /// A scale that is not one of the four the machine has.
    Scale {
        /// What was asked for.
        scale: u8,
    },
    /// The stack pointer as an index, which is the one register that cannot be one, because its
    /// number is what the encoding uses to say there is no index.
    Index,
    /// An argument that is not the kind the row said it was, which cannot happen through
    /// [`encode`] and can through a row that disagrees with itself.
    Argument {
        /// The mnemonic that was asked for.
        mnemonic: String,
        /// Which argument it was.
        at: u8,
    },
    /// A mask on an instruction that is not EVEX encoded, which has nowhere to put one.
    Mask {
        /// The mnemonic that was asked for.
        mnemonic: String,
    },
    /// A register thirty two bit mode has no name for: one numbered eight or above, or `spl`,
    /// `bpl`, `sil` or `dil`, which only a REX byte can name. See [`Mode`].
    Register {
        /// The mnemonic that was asked for.
        mnemonic: String,
        /// The number of the register, which for a byte register is the one `spl` to `dil` share
        /// with `ah` to `bh`.
        number: u8,
    },
    /// A sixty four bit operand in thirty two bit mode, which has no REX byte to say so with and
    /// no sixty four bit push or pop.
    Wide {
        /// The mnemonic that was asked for.
        mnemonic: String,
    },
    /// An address counted from the end of the instruction in thirty two bit mode, where the
    /// encoding that says so in sixty four bit mode is an absolute address instead.
    Relative {
        /// The mnemonic that was asked for.
        mnemonic: String,
    },
    /// A `zmm` register, or a vector register numbered sixteen or above, on an instruction this
    /// encoder only has a VEX form of. Only an EVEX prefix has the bits to name either.
    Vex {
        /// The mnemonic that was asked for.
        mnemonic: String,
    },
}

impl fmt::Display for Error {
    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
        match self {
            Error::Unwritten { mnemonic, args } => {
                write!(f, "no encoding for {mnemonic} with {} arguments {args:?}", args.len())
            }
            Error::Immediate { mnemonic, imm } => {
                write!(f, "no form of {mnemonic} can carry the immediate {imm}")
            }
            Error::Crowded { mnemonic } => {
                write!(f, "{mnemonic} names ah and a register that needs a rex byte")
            }
            Error::Scale { scale } => write!(f, "{scale} is not a scale this machine has"),
            Error::Index => write!(f, "the stack pointer cannot be an index"),
            Error::Argument { mnemonic, at } => {
                write!(f, "argument {at} of {mnemonic} is not what its encoding expects")
            }
            Error::Mask { mnemonic } => write!(f, "{mnemonic} cannot take a mask"),
            Error::Register { mnemonic, number } => {
                write!(f, "{mnemonic} names register {number}, which 32 bit mode cannot name")
            }
            Error::Wide { mnemonic } => {
                write!(f, "{mnemonic} has a 64 bit operand, which 32 bit mode cannot write")
            }
            Error::Relative { mnemonic } => write!(
                f,
                "{mnemonic} has an address counted from the instruction, which 32 bit mode lacks"
            ),
            Error::Vex { mnemonic } => write!(
                f,
                "{mnemonic} is only written here with a VEX prefix, which cannot name a zmm \
                 register or one numbered 16 or above"
            ),
        }
    }
}

impl std::error::Error for Error {}

/// The bit of a REX byte that says the operands are sixty four bits.
const REX_W: u8 = 0b1000;
/// The bit that carries the top of the register beside the addressing byte.
const REX_R: u8 = 0b0100;
/// The bit that carries the top of an index register.
const REX_X: u8 = 0b0010;
/// The bit that carries the top of the register the addressing byte addresses, which is also the
/// top of a base register and of a register in the opcode.
const REX_B: u8 = 0b0001;

/// Writes one instruction of the machine onto the end of `out`.
///
/// The values are the arguments in the order they are written, which is the order
/// [`Written::args`](crate::x86_64::Written::args) holds them in, so a caller resolves each of
/// those and hands the results here.
///
/// # Errors
///
/// [`Error::Unwritten`] for an instruction this does not encode, and the rest for an instruction
/// it does encode that was handed something the machine cannot express. All of them are bugs
/// rather than anything a program could ask for. See [`Error`].
pub fn encode(mnemonic: &str, values: &[Value], out: &mut Vec<u8>) -> Result<Holes, Error> {
    encode_masked(mnemonic, values, Opmask::default(), out)
}

/// [`encode`] in that mode.
///
/// # Errors
///
/// What [`encode`] returns, and in thirty two bit mode [`Error::Register`], [`Error::Wide`] and
/// [`Error::Relative`] for what that mode has no way to write. See [`Mode`].
pub fn encode_in(
    mode: Mode,
    mnemonic: &str,
    values: &[Value],
    out: &mut Vec<u8>,
) -> Result<Holes, Error> {
    encode_masked_in(mode, mnemonic, values, Opmask::default(), out)
}

/// The mask an AVX-512 instruction writes its result under, which is what `{%k1}{z}` after its
/// destination says.
///
/// `k0` is no mask at all, which is why the default is it: an instruction written without one has
/// zero in the field, and no instruction can be masked by `k0`.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
pub struct Opmask {
    /// Which mask register, `k1` to `k7`, or zero for none.
    pub k: u8,
    /// Whether the elements the mask leaves out are zeroed rather than left as they were, which
    /// is `{z}`.
    pub zero: bool,
}

/// [`encode`] with a mask on the instruction.
///
/// # Errors
///
/// What [`encode`] returns, and [`Error::Mask`] for a mask on an instruction that is not EVEX
/// encoded.
pub fn encode_masked(
    mnemonic: &str,
    values: &[Value],
    mask: Opmask,
    out: &mut Vec<u8>,
) -> Result<Holes, Error> {
    encode_masked_in(Mode::Bits64, mnemonic, values, mask, out)
}

/// [`encode_masked`] in that mode.
///
/// # Errors
///
/// What [`encode_masked`] and [`encode_in`] return.
pub fn encode_masked_in(
    mode: Mode,
    mnemonic: &str,
    values: &[Value],
    mask: Opmask,
    out: &mut Vec<u8>,
) -> Result<Holes, Error> {
    if mode == Mode::Bits32 && ONLY64.contains(&mnemonic) {
        return Err(Error::Wide { mnemonic: mnemonic.to_owned() });
    }
    // On the stack, since this is asked once for every instruction written and almost none has
    // more than four arguments. A list is made only for one that does, and for the error.
    let mut few = [Kind::Imm; 4];
    let many: Vec<Kind>;
    let args: &[Kind] = if values.len() <= few.len() {
        for (kind, value) in few.iter_mut().zip(values) {
            *kind = value.kind();
        }
        &few[..values.len()]
    } else {
        many = values.iter().map(|value| value.kind()).collect();
        &many
    };
    let imm = values
        .iter()
        .find_map(|value| match value {
            Value::Imm(number) => Some(*number),
            _ => None,
        })
        .unwrap_or(0);
    let Some(row) = encoding_in(mode, mnemonic, args, imm) else {
        // Which of the two it is says something different to whoever reads it. An instruction
        // with no row at all is a hole in this description, and one whose rows are all too narrow
        // is a lowering that produced a constant the instruction it chose cannot hold.
        return Err(if rows_in(mode, mnemonic, args).next().is_some() {
            Error::Immediate { mnemonic: mnemonic.to_owned(), imm }
        } else {
            Error::Unwritten { mnemonic: mnemonic.to_owned(), args: args.to_vec() }
        });
    };
    let row = widened(mode, row, values, mask).unwrap_or(row);
    let row = flipped(mode, row, values).unwrap_or(row);
    if mask != Opmask::default() && row.evex.is_none() {
        return Err(Error::Mask { mnemonic: mnemonic.to_owned() });
    }
    if mode == Mode::Bits32 && row.size.wide() {
        return Err(Error::Wide { mnemonic: mnemonic.to_owned() });
    }
    let mut writer = Writer {
        row,
        values,
        mode,
        rex: 0,
        high: 0,
        forced: false,
        banned: false,
        evex: None,
        scale: 1,
        length: Length::Xmm,
    };
    if let Some(evex) = row.evex {
        writer.choose(evex, mask);
    } else if row.vex.is_some() {
        writer.measure()?;
    }
    writer.write(out, imm, mask)
}

/// The EVEX row of an instruction whose VEX row was found first, when the operands need EVEX.
///
/// A `zmm`, a register numbered sixteen or above, or a mask can only be said with an EVEX prefix,
/// and an instruction that has both forms lists the VEX one first so it is taken otherwise.
fn widened(
    mode: Mode,
    row: &Encoding,
    values: &[Value],
    mask: Opmask,
) -> Option<&'static Encoding> {
    if row.evex.is_some() || row.vex.is_none() {
        return None;
    }
    let wide = values.iter().any(|value| {
        matches!(*value, Value::Vector(number, length) if number >= 16 || length == Length::Zmm)
    });
    if !wide && mask == Opmask::default() {
        return None;
    }
    let args: Vec<Kind> = values.iter().map(|value| value.kind()).collect();
    rows_in(mode, row.mnemonic, &args).find(|other| other.evex.is_some())
}

/// The store form of a VEX move between two vector registers, when gas would write that one.
///
/// A move between two registers can be written with either opcode, the load with the source
/// beside the addressing byte or the store with it in the addressing byte. gas takes the store
/// when the source is numbered eight or above and the destination is not, since then the high
/// register is the one beside the addressing byte, and the two byte prefix has a bit for that one
/// and not for the other. The bytes have to match what gas writes.
fn flipped(mode: Mode, row: &Encoding, values: &[Value]) -> Option<&'static Encoding> {
    let number = |value: &Value| match *value {
        Value::Xmm(reg) => Some(reg.number()),
        Value::Vector(number, _) => Some(number),
        _ => None,
    };
    let [from, to] = values else { return None };
    let high = number(from)? >= 8 && number(to)? < 8;
    if !high || row.evex.is_some() || row.vex.is_none_or(|vex| vex.map != Map::Escape) {
        return None;
    }
    rows_in(mode, row.mnemonic, &VM).find(|store| store.vex.is_some())
}

/// One instruction being written out.
struct Writer<'a> {
    row: &'a Encoding,
    values: &'a [Value],
    /// Which machine the bytes are for.
    mode: Mode,
    /// The low four bits of the REX byte, which are the tops of the register numbers.
    rex: u8,
    /// Whether a REX byte has to be written even when it would say nothing, which is what naming
    /// one of the four registers that are only bytes with one asks for.
    forced: bool,
    /// Whether one may not be written at all, which is what naming `ah` asks for.
    banned: bool,
    /// The fifth bits of the register numbers, which only an EVEX prefix has room for. `REX_R` is
    /// the register beside the addressing byte and `REX_B` the one it addresses.
    high: u8,
    /// What the prefix says, when the instruction is being written EVEX encoded rather than in its
    /// VEX form.
    evex: Option<Evex>,
    /// What a one byte displacement is counted in, which is one except under EVEX.
    scale: i32,
    /// The widest vector the instruction names, which is the length it works at.
    length: Length,
}

impl Writer<'_> {
    /// The length a VEX row works at, which is the widest vector register it names.
    ///
    /// The prefix has one bit for it, so an `xmm` and a `ymm` are all it can say, and it has no
    /// fifth bit for a register number either. Either of those needs EVEX, which this row is not.
    fn measure(&mut self) -> Result<(), Error> {
        for value in self.values {
            if let Value::Vector(number, length) = *value {
                if number >= 16 || length == Length::Zmm {
                    return Err(Error::Vex { mnemonic: self.row.mnemonic.to_owned() });
                }
                self.length = self.length.max(length);
            }
        }
        Ok(())
    }

    /// Whether a row that is EVEX encoded is written that way or in its VEX form.
    ///
    /// The VEX form is what gas writes whenever the row has one and nothing needs EVEX, which is a
    /// mask, a whole `zmm`, or a register numbered sixteen or above.
    fn choose(&mut self, evex: Evex, mask: Opmask) {
        let mut high = false;
        for value in self.values {
            if let Value::Vector(number, length) = *value {
                self.length = self.length.max(length);
                high |= number >= 16;
            }
        }
        let plain = mask == Opmask::default() && !high && self.length != Length::Zmm;
        if evex.vex.is_some() && plain {
            return;
        }
        self.evex = Some(evex);
        self.scale = i32::from(match evex.tuple {
            Tuple::Full => self.length.bytes(),
            Tuple::Fixed(bytes) => bytes,
        });
    }

    /// The whole instruction: what the arguments come to, then the bytes in the order they go in.
    ///
    /// The addressing byte and everything behind it are worked out before anything is written,
    /// because they are what says whether there is a REX byte and the REX byte goes in front.
    fn write(mut self, out: &mut Vec<u8>, imm: i64, mask: Opmask) -> Result<Holes, Error> {
        let mut tail = Vec::new();
        let mut holes = Holes::default();
        let mut plus = 0;
        match self.row.fields {
            Fields::None => {}
            Fields::Ext { rm, ext } => self.address(rm, ext, &mut tail, &mut holes)?,
            Fields::Pair { rm, reg } => {
                let reg = self.number(reg, REX_R)?;
                self.address(rm, reg, &mut tail, &mut holes)?;
            }
            Fields::Plus { reg } => plus = self.number(reg, REX_B)?,
        }
        if self.banned && (self.forced || self.rex != 0) {
            return Err(Error::Crowded { mnemonic: self.row.mnemonic.to_owned() });
        }

        // A VEX encoded instruction takes an early exit from here, because what it writes in front
        // of the opcode is not a shortening of what a legacy one writes but a different thing in the
        // same place: the prefix, the REX byte and the escape bytes are all folded into two or three
        // bytes that also carry an operand. Everything from the opcode onwards is the same, so the
        // segment override is written first, the prefix goes where the REX byte would have, and the
        // tail and the immediate fall through to the shared code below.
        // An EVEX row written in its VEX form is a VEX row with the wide bit the row says that form
        // has, and the length its registers are named at.
        let vex = match self.row.evex {
            Some(evex) if self.evex.is_none() => evex.vex.map(|wide| {
                (Vex { map: evex.map, vvvv: evex.vvvv, long: self.length == Length::Ymm }, wide)
            }),
            _ => self.row.vex.map(|vex| {
                (Vex { long: vex.long || self.length == Length::Ymm, ..vex }, self.row.size.wide())
            }),
        };
        if let Some(evex) = self.evex {
            if let Some(prefix) = self.segment() {
                out.push(prefix);
            }
            let vvvv = match evex.vvvv {
                Some(at) => self.vvvv(at)?,
                None => 0,
            };
            self.evex_prefix(evex, vvvv, mask, out);
        } else if let Some((vex, wide)) = vex {
            if let Some(prefix) = self.segment() {
                out.push(prefix);
            }
            let vvvv = match vex.vvvv {
                Some(at) => self.vvvv(at)?,
                None => 0,
            };
            self.prefix(vex, wide, vvvv, out);
        } else {
            self.legacy(out);
        }
        let (last, front) = self.row.opcode.split_last().expect("an opcode is at least one byte");
        out.extend_from_slice(front);
        out.push(last + plus);
        // The offsets were taken against an empty buffer, so they move by however much is in
        // front of the addressing byte by the time it is really written.
        let at = out.len();
        for hole in [&mut holes.dest, &mut holes.rip, &mut holes.disp].into_iter().flatten() {
            *hole += at;
        }
        out.extend_from_slice(&tail);

        match self.row.imm {
            ImmSize::None => {}
            ImmSize::Ib => out.push(imm as u8),
            ImmSize::Iw => out.extend_from_slice(&(imm as u16).to_le_bytes()),
            ImmSize::Id => out.extend_from_slice(&(imm as u32).to_le_bytes()),
            ImmSize::Io => out.extend_from_slice(&imm.to_le_bytes()),
            ImmSize::Cd => {
                holes.dest = Some(out.len());
                out.extend_from_slice(&0i32.to_le_bytes());
            }
            ImmSize::Cb => {
                holes.dest = Some(out.len());
                out.push(0);
            }
            ImmSize::Is4 => out.push(self.vvvv(0)? << 4),
        }
        Ok(holes)
    }

    /// The two or three bytes a VEX encoded instruction carries where a legacy one carries its
    /// prefixes and its REX byte.
    ///
    /// The three register extension bits and the wide bit are the ones REX held, and they are
    /// written inverted, which is what makes the first byte of either form impossible to confuse
    /// with the one byte instruction that used to live at `0xC4` and `0xC5` in 32 bit mode. So is
    /// `vvvv`, which is why a row with no third operand writes fifteen there rather than zero.
    ///
    /// The short form is chosen whenever it says the same thing, which is what every assembler does
    /// and therefore what the bytes have to match. It can only say `0F` for the map and can only
    /// say zero for the wide bit and for the two extension bits other than `R`, so a row outside
    /// the first table, or one on a wide operand, or one naming a register numbered eight or above
    /// in the addressing byte's base or index, is three bytes and there is nothing to choose.
    fn prefix(&self, vex: Vex, wide: bool, vvvv: u8, out: &mut Vec<u8>) {
        let pp = self.pp();
        let tail = ((!vvvv & 0xF) << 3) | (u8::from(vex.long) << 2) | pp;
        let short = !wide && vex.map == Map::Escape && self.rex & (REX_X | REX_B) == 0;
        if short {
            out.push(0xC5);
            out.push((u8::from(self.rex & REX_R == 0) << 7) | tail);
            return;
        }
        out.push(0xC4);
        out.push(
            (u8::from(self.rex & REX_R == 0) << 7)
                | (u8::from(self.rex & REX_X == 0) << 6)
                | (u8::from(self.rex & REX_B == 0) << 5)
                | vex.map.bits(),
        );
        out.push((u8::from(wide) << 7) | tail);
    }

    /// `pp`, which is the mandatory prefix as a number rather than as a byte. The same three bytes
    /// a legacy row would have written, in the order the manual numbers them.
    fn pp(&self) -> u8 {
        match self.row.size.prefix() {
            None => 0,
            Some(0x66) => 1,
            Some(0xF3) => 2,
            Some(0xF2) => 3,
            Some(_) => unreachable!("a size writes one of those three bytes or none"),
        }
    }

    /// The four bytes an EVEX encoded instruction carries in front of its opcode.
    ///
    /// `62`, then three bytes. The first is the VEX three byte form's second byte with the fifth
    /// bit of the register beside the addressing byte squeezed in, the second is the VEX form's
    /// third byte with a bit that is always set, and the third is new: zeroing, the length, the
    /// fifth bit of `vvvv` and the mask. Everything that names a register is written inverted, as
    /// in VEX. The fifth bit of a register the addressing byte addresses goes where the top of an
    /// index would, since a register has no index.
    fn evex_prefix(&self, evex: Evex, vvvv: u8, mask: Opmask, out: &mut Vec<u8>) {
        let x = self.rex & REX_X != 0 || self.high & REX_B != 0;
        out.push(0x62);
        out.push(
            (u8::from(self.rex & REX_R == 0) << 7)
                | (u8::from(!x) << 6)
                | (u8::from(self.rex & REX_B == 0) << 5)
                | (u8::from(self.high & REX_R == 0) << 4)
                | evex.map.bits(),
        );
        out.push((u8::from(evex.w) << 7) | ((!vvvv & 0xF) << 3) | 0b100 | self.pp());
        out.push(
            (u8::from(mask.zero) << 7)
                | (self.length.bits() << 5)
                | (u8::from(vvvv & 0x10 == 0) << 3)
                | (mask.k & 7),
        );
    }

    /// The prefixes and the REX byte a legacy encoded instruction carries in front of its opcode.
    fn legacy(&self, out: &mut Vec<u8>) {
        // `fwait` in front of the three x87 instructions that are written with one, which is in
        // front of everything because it is an instruction and not a prefix. A prefix reaches the
        // instruction after it, so a REX byte written here would be about `fwait` rather than
        // about what follows it.
        if self.row.wait {
            out.push(0x9B);
        }
        // Group two of the legacy prefixes, in front of everything else because that is where a
        // segment override goes. It says which storage the address is in, which is a fact about
        // the address rather than about how wide the operands are, so it is read off the address
        // rather than off the row.
        if let Some(prefix) = self.segment() {
            out.push(prefix);
        }
        // The operand size byte in front of the mandatory one, for the one size that is both. See
        // `Size::WordDouble`.
        if self.row.size == WordDouble {
            out.push(0x66);
        }
        if let Some(prefix) = self.row.size.prefix() {
            out.push(prefix);
        }
        let rex = if self.row.size.wide() { self.rex | REX_W } else { self.rex };
        if rex != 0 || (self.forced && !self.banned) {
            out.push(0x40 | rex);
        }
    }

    /// The prefix that says the address is counted from a segment, when one of the arguments is
    /// such an address. At most one argument of an instruction is an address at all.
    fn segment(&self) -> Option<u8> {
        self.values.iter().find_map(|value| match value {
            Value::Mem(addr) => addr.segment.map(Segment::prefix),
            _ => None,
        })
    }

    /// The number of the register at that index, with its top bit put in the REX byte.
    fn number(&mut self, at: u8, bit: u8) -> Result<u8, Error> {
        match self.values.get(usize::from(at)) {
            Some(&Value::Reg(reg, width)) => {
                let number = reg.number();
                if self.mode == Mode::Bits32
                    && (number >= 8 || (width == Width::Byte && (4..8).contains(&number)))
                {
                    return Err(self.unnamed(number));
                }
                if number >= 8 {
                    self.rex |= bit;
                }
                // The one thing a width decides about the bytes. Every other difference between
                // an eight, a sixteen, a thirty two and a sixty four bit instruction is in the
                // opcode or in the prefixes, and those are on the row.
                if width == Width::Byte && (4..8).contains(&number) {
                    self.forced = true;
                }
                Ok(number & 7)
            }
            // A vector register is numbered the way a general purpose one is and there is no
            // width to look at, since the whole of it is what the instruction works on.
            Some(&Value::Xmm(reg)) => {
                let number = reg.number();
                if self.mode == Mode::Bits32 && number >= 8 {
                    return Err(self.unnamed(number));
                }
                if number >= 8 {
                    self.rex |= bit;
                }
                Ok(number & 7)
            }
            // The same on a row that is EVEX encoded, with a fifth bit that only the EVEX prefix
            // has room for, and on a VEX row, which says the length in its own bit and has been
            // through `measure`. A legacy row has nowhere to say a length at all.
            Some(&Value::Vector(number, _))
                if (self.row.evex.is_some() && (number < 16 || self.evex.is_some()))
                    || (self.row.vex.is_some() && number < 16) =>
            {
                if self.mode == Mode::Bits32 && number >= 8 {
                    return Err(self.unnamed(number));
                }
                if number & 8 != 0 {
                    self.rex |= bit;
                }
                if number & 16 != 0 {
                    self.high |= bit;
                }
                Ok(number & 7)
            }
            Some(&Value::Mask(number)) if number < 8 => Ok(number),
            // A control or debug register is numbered to fifteen the way a general purpose one is,
            // with the top bit in the REX byte, which is how `%cr8` is reached at all.
            Some(&(Value::Control(number) | Value::Debug(number))) if number < 16 => {
                if number >= 8 {
                    self.rex |= bit;
                }
                Ok(number & 7)
            }
            Some(&Value::Seg(segment)) => Ok(segment.number()),
            // `ah` is `al` plus four, and so are the other three, which is also why only the
            // first four registers have one.
            Some(&Value::High(reg)) if reg.number() < 4 => {
                self.banned = true;
                Ok(reg.number() + 4)
            }
            _ => Err(Error::Argument { mnemonic: self.row.mnemonic.to_owned(), at }),
        }
    }

    /// The whole number of the register at that index, for the `vvvv` field of a VEX prefix.
    ///
    /// Four bits rather than three, and nothing goes in the REX byte, which is the whole difference
    /// between this and [`Self::number`]. Every other operand's extension bit is in a byte beside
    /// the one that holds the low three, so the two have to be worked out separately and put in two
    /// places. This operand's four bits are all in the prefix, which is the only place it appears.
    fn vvvv(&self, at: u8) -> Result<u8, Error> {
        let number = match self.values.get(usize::from(at)) {
            Some(&Value::Reg(reg, _)) | Some(&Value::Xmm(reg)) => reg.number(),
            Some(&Value::Vector(number, _)) if number < 32 => number,
            Some(&Value::Mask(number)) if number < 8 => number,
            _ => return Err(Error::Argument { mnemonic: self.row.mnemonic.to_owned(), at }),
        };
        if self.mode == Mode::Bits32 && number >= 8 {
            return Err(self.unnamed(number));
        }
        Ok(number)
    }

    /// The refusal of a register thirty two bit mode has no name for.
    fn unnamed(&self, number: u8) -> Error {
        Error::Register { mnemonic: self.row.mnemonic.to_owned(), number }
    }

    /// The addressing byte and whatever follows it, which is a register or a whole address.
    ///
    /// `reg` is the three bits beside the addressed one, which is either a register that has
    /// already been worked out or the rest of the opcode.
    fn address(
        &mut self,
        at: u8,
        reg: u8,
        out: &mut Vec<u8>,
        holes: &mut Holes,
    ) -> Result<(), Error> {
        match self.values.get(usize::from(at)) {
            Some(Value::Mem(addr)) => self.mem(*addr, reg, out, holes),
            Some(_) => {
                let rm = self.number(at, REX_B)?;
                out.push(0b1100_0000 | (reg << 3) | rm);
                Ok(())
            }
            None => Err(Error::Argument { mnemonic: self.row.mnemonic.to_owned(), at }),
        }
    }

    /// One address, as the addressing byte and the two things that can follow it.
    fn mem(
        &mut self,
        addr: Addr,
        reg: u8,
        out: &mut Vec<u8>,
        holes: &mut Holes,
    ) -> Result<(), Error> {
        // Counted from the end of the instruction, which is the one mode with no register in it
        // and is said by naming the base the encoding would otherwise use for no base at all.
        if addr.rip {
            // Thirty two bit mode has the same bits, and they say an absolute address there.
            if self.mode == Mode::Bits32 {
                return Err(Error::Relative { mnemonic: self.row.mnemonic.to_owned() });
            }
            out.push((reg << 3) | 0b101);
            holes.rip = Some(out.len());
            out.extend_from_slice(&addr.disp.to_le_bytes());
            return Ok(());
        }

        let index = match addr.index {
            Some(index) if index.number() == 4 => return Err(Error::Index),
            Some(index) if self.mode == Mode::Bits32 && index.number() >= 8 => {
                return Err(self.unnamed(index.number()));
            }
            Some(index) => {
                if index.number() >= 8 {
                    self.rex |= REX_X;
                }
                Some(index.number() & 7)
            }
            None => None,
        };
        let scale = match addr.scale {
            _ if index.is_none() => 0,
            1 => 0,
            2 => 1,
            4 => 2,
            8 => 3,
            scale => return Err(Error::Scale { scale }),
        };
        let far = addr.base.map(PhysReg::number).filter(|&number| number >= 8);
        if let Some(number) = far.filter(|_| self.mode == Mode::Bits32) {
            return Err(self.unnamed(number));
        }
        let base = addr.base.map(|base| {
            if base.number() >= 8 {
                self.rex |= REX_B;
            }
            base.number() & 7
        });

        // Nothing but a number, which in thirty two bit mode is the one mode with no register in
        // it said directly, where sixty four bit mode spent those bits on counting from the end of
        // the instruction and has to say it through a SIB byte that names neither.
        if self.mode == Mode::Bits32 && base.is_none() && index.is_none() {
            out.push((reg << 3) | 0b101);
            if addr.linked {
                holes.disp = Some(out.len());
            }
            out.extend_from_slice(&addr.disp.to_le_bytes());
            return Ok(());
        }

        // The stack pointer's number in the addressed field means there is a second byte instead
        // of a register, so an address whose base really is the stack pointer needs that byte
        // even when it has no index. The frame pointer's number with no displacement means the
        // address is counted from the end of the instruction, so an address based on it always
        // carries a displacement, and a byte of zero is the cheapest one.
        let second = index.is_some() || base == Some(4) || base.is_none();
        let mode = match base {
            None => 0,
            Some(base) => {
                if addr.linked {
                    2
                } else if addr.disp == 0 && base != 5 {
                    0
                } else if addr.disp % self.scale == 0
                    && i8::try_from(addr.disp / self.scale).is_ok()
                {
                    1
                } else {
                    2
                }
            }
        };
        out.push((mode << 6) | (reg << 3) | if second { 0b100 } else { base.unwrap_or(0) });
        if second {
            // Four in the index field is no index, and five in the base field with a mode of zero
            // is no base, which is how an address that is nothing but a number is written.
            out.push((scale << 6) | (index.unwrap_or(4) << 3) | base.unwrap_or(5));
        }
        match mode {
            0 if base.is_none() => {
                if addr.linked {
                    holes.disp = Some(out.len());
                }
                out.extend_from_slice(&addr.disp.to_le_bytes());
            }
            0 => {}
            // Counted in accesses under EVEX, and `scale` is one otherwise.
            1 => out.push((addr.disp / self.scale) as u8),
            _ => {
                if addr.linked {
                    holes.disp = Some(out.len());
                }
                out.extend_from_slice(&addr.disp.to_le_bytes());
            }
        }
        Ok(())
    }
}

/// The instructions that do nothing, one for each length from one byte to eleven.
///
/// The lengths the manuals recommend, which is what gas writes in front of a loop as well: one
/// `nop` for a byte, `nopw` with an operand size prefix for two, and past that the `nopl` and
/// `nopw` forms that take an address they never read, grown by a displacement and then by prefixes
/// until the ten byte one is `cs nopw 0(%rax,%rax,1)`. The eleven byte one is that with a second
/// operand size prefix, which is where gas stops, and stopping at the same length is what makes a
/// run of padding come out as the same instructions gas writes. One instruction rather than a run
/// of single bytes because the processor may walk into the padding, and ten one byte nops are ten
/// instructions to decode where this is one.
const NOPS: [&[u8]; 11] = [
    &[0x90],
    &[0x66, 0x90],
    &[0x0f, 0x1f, 0x00],
    &[0x0f, 0x1f, 0x40, 0x00],
    &[0x0f, 0x1f, 0x44, 0x00, 0x00],
    &[0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00],
    &[0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00],
    &[0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00],
    &[0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00],
    &[0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00],
    &[0x66, 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00],
];

/// That many bytes of instructions that do nothing, as few instructions as they can be.
///
/// Padding the processor may run through, which is the space in front of a loop that the block
/// before it falls into. The longest is eleven bytes, and a longer run is as many of those as fit
/// and then one for what is left, which is the order gas writes them in.
pub fn nops(count: usize, out: &mut Vec<u8>) {
    let mut left = count;
    while left > 0 {
        let take = left.min(NOPS.len());
        out.extend_from_slice(NOPS[take - 1]);
        left -= take;
    }
}

#[cfg(test)]
mod tests {
    use super::*;
    use crate::x86_64::text::written;
    use crate::x86_64::{
        INSTS, R8, R9, R10, R11, R12, R13, R15, RAX, RBP, RBX, RCX, RDI, RDX, RSI, RSP, xmm,
    };

    /// The bytes of that instruction, as a string a person can compare with a disassembler's.
    fn hex(mnemonic: &str, values: &[Value]) -> String {
        let mut out = Vec::new();
        encode(mnemonic, values, &mut out).expect("an instruction this target encodes");
        out.iter().map(|byte| format!("{byte:02x}")).collect::<Vec<_>>().join(" ")
    }

    /// A whole register, which is what most arguments are.
    fn quad(reg: PhysReg) -> Value {
        Value::Reg(reg, Width::Quad)
    }

    /// Thirty two bits of one.
    fn long(reg: PhysReg) -> Value {
        Value::Reg(reg, Width::Long)
    }

    /// Sixteen bits of one.
    fn word(reg: PhysReg) -> Value {
        Value::Reg(reg, Width::Word)
    }

    /// Eight bits of one.
    fn byte(reg: PhysReg) -> Value {
        Value::Reg(reg, Width::Byte)
    }

    #[test]
    fn every_instruction_the_listing_writes_is_one_this_encodes() {
        // The claim `spec/11-asm-objects-debug.md` section 11.1 makes about the two paths sharing
        // a description. An instruction the text path writes and this cannot encode would be an
        // opcode that compiles under `-S` and fails to produce an object file. The few that only
        // i386 writes, `pushl` and `popl`, are asked about in the mode they belong to.
        for &(opcode, _) in INSTS {
            let insts = written(opcode).expect("every described opcode is a written opcode");
            for inst in insts {
                let args: Vec<Kind> = inst.args.iter().map(|&arg| Kind::of(arg)).collect();
                assert!(
                    encoding(inst.mnemonic, &args, 0).is_some()
                        || encoding_in(Mode::Bits32, inst.mnemonic, &args, 0).is_some(),
                    "{opcode} writes {} with {args:?} and nothing encodes it",
                    inst.mnemonic
                );
            }
        }
    }

    /// Numbers on both sides of every boundary any row here has.
    const PROBES: [i64; 11] =
        [0, 1, -1, 127, 128, -128, -129, 0xffff, 0x1_0000, 0x7fff_ffff, 0x1_0000_0000];

    #[test]
    fn the_rows_of_one_instruction_go_from_the_smallest_immediate_to_the_largest() {
        // A lookup takes the first row that fits, so the order is the whole of what makes the
        // short forms reachable. A general row in front of a short one would leave the short one
        // dead, which nothing that encodes a single instruction would ever notice, and a row that
        // held nothing the one in front of it did not would be dead outright.
        for (at, row) in ENCODINGS.iter().enumerate() {
            for other in &ENCODINGS[at + 1..] {
                if other.mnemonic != row.mnemonic || other.args != row.args {
                    continue;
                }
                // An EVEX row behind a VEX one is reached by what the operands are, not by the
                // immediate, so it is not dead.
                if row.evex.is_none() && other.evex.is_some() {
                    continue;
                }
                for imm in PROBES {
                    assert!(
                        !row.fits.holds(imm) || other.fits.holds(imm),
                        "{} takes {imm} in front of a row that does not",
                        row.mnemonic
                    );
                }
                assert!(
                    PROBES.iter().any(|&imm| other.fits.holds(imm) && !row.fits.holds(imm)),
                    "{} has a row behind another that holds no more than it",
                    row.mnemonic
                );
            }
        }
    }

    #[test]
    fn an_immediate_no_form_of_an_instruction_can_hold_is_refused_rather_than_cut_down() {
        // The bug this is here for writes a program that adds a different number from the one it
        // was given, which nothing downstream could notice and no test of the text path could
        // either, since the text path writes the number out in full.
        let mut out = Vec::new();
        let big = 0x1_2345_6789;
        let error = encode("addq", &[Value::Imm(big), quad(RAX)], &mut out)
            .expect_err("more than four bytes of immediate");
        assert_eq!(error, Error::Immediate { mnemonic: "addq".to_owned(), imm: big });
        assert_eq!(out, Vec::<u8>::new());
        // The sixty four bit move is the one instruction that can hold it.
        assert!(encode("movq", &[Value::Imm(big), quad(RAX)], &mut out).is_ok());
        // And an immediate that fits either way round is one the machine can hold, since what it
        // carries is that many bits and not that many values.
        assert_eq!(hex("movl", &[Value::Imm(0xffff_ffff), long(RAX)]), "b8 ff ff ff ff");
        assert_eq!(hex("addb", &[Value::Imm(200), byte(RAX)]), "80 c0 c8");
        assert_eq!(hex("shlq", &[Value::Imm(63), quad(RAX)]), "48 c1 e0 3f");
    }

    /// gcc prints `(u8)~0x80`, promoted to an `int`, as `$-129` under `%b`, which is the kernel's
    /// `clear_bit`, and gas writes its low eight bits without a word. Down to -255 is what gas
    /// takes quietly, and -256 is where it starts warning that it cut the number down, so that is
    /// where this starts refusing.
    #[test]
    fn a_negative_number_is_cut_to_the_width_as_far_as_gas_does_it_quietly() {
        assert_eq!(hex("andb", &[Value::Imm(-129), byte(RAX)]), "80 e0 7f");
        assert_eq!(hex("andb", &[Value::Imm(-255), byte(RCX)]), "80 e1 01");
        assert_eq!(
            hex("andw", &[Value::Imm(-32769), Value::Reg(RCX, Width::Word)]),
            "66 81 e1 ff 7f"
        );
        assert_eq!(hex("andl", &[Value::Imm(-0xffff_ffff), long(RCX)]), "81 e1 01 00 00 00");
        let mut out = Vec::new();
        assert!(encode("andb", &[Value::Imm(-256), byte(RCX)], &mut out).is_err());
        assert!(encode("andb", &[Value::Imm(256), byte(RCX)], &mut out).is_err());
        assert!(
            encode("andw", &[Value::Imm(-65536), Value::Reg(RCX, Width::Word)], &mut out).is_err()
        );
    }

    #[test]
    fn an_instruction_with_two_registers_is_the_opcode_and_one_byte_that_names_both() {
        // The direction that is easy to get backwards. AT&T writes the source first and the byte
        // that names the two puts the destination in the half the manual calls `r/m`.
        assert_eq!(hex("addl", &[long(RCX), long(RAX)]), "01 c8");
        assert_eq!(hex("addl", &[long(RAX), long(RCX)]), "01 c1");
        // Sixty four bits is the same instruction with a byte in front saying so.
        assert_eq!(hex("addq", &[quad(RCX), quad(RAX)]), "48 01 c8");
        // Sixteen is the same instruction with a different byte in front.
        let word = [Value::Reg(RCX, Width::Word), Value::Reg(RAX, Width::Word)];
        assert_eq!(hex("addw", &word), "66 01 c8");
        // And a multiply is the other way round, because it is not one of the eight that share
        // an opcode column.
        assert_eq!(hex("imull", &[long(RCX), long(RAX)]), "0f af c1");
    }

    #[test]
    fn a_register_the_second_half_of_the_machine_added_is_named_in_the_byte_in_front() {
        assert_eq!(hex("addl", &[long(R8), long(RAX)]), "44 01 c0");
        assert_eq!(hex("addl", &[long(RAX), long(R8)]), "41 01 c0");
        assert_eq!(hex("addq", &[quad(R8), quad(R8)]), "4d 01 c0");
        assert_eq!(hex("pushq", &[quad(R12)]), "41 54");
        assert_eq!(hex("popq", &[quad(RAX)]), "58");
    }

    /// The conditional move, whose two operands are the other way round from the text.
    ///
    /// AT&T writes the source first and the destination second, and the byte after the opcode
    /// names the destination in the register field and the source in the other one, which is the
    /// reverse of the arithmetic. Checked against what the assembler produces for the same three
    /// lines, which is the only way to be sure a direction is right.
    #[test]
    fn a_conditional_move_names_its_destination_in_the_register_field() {
        assert_eq!(hex("cmovnel", &[long(RSI), long(RAX)]), "0f 45 c6");
        assert_eq!(hex("cmovneq", &[quad(RSI), quad(RAX)]), "48 0f 45 c6");
        assert_eq!(hex("cmovnew", &[word(RSI), word(RAX)]), "66 0f 45 c6");
        // And the half of the register file that needs a byte in front to be named at all.
        assert_eq!(hex("cmovnel", &[long(R8), long(RAX)]), "41 0f 45 c0");
        assert_eq!(hex("cmovnel", &[long(RAX), long(R8)]), "44 0f 45 c0");
    }

    #[test]
    fn a_byte_register_the_machine_could_not_reach_before_forces_a_byte_that_says_nothing_else() {
        // Without the `40` these are `%dh` and `%bh`, which is the encoding bug that produces a
        // program reading a register nothing was ever put in.
        assert_eq!(hex("movb", &[byte(RSI), byte(RAX)]), "40 88 f0");
        assert_eq!(hex("sete", &[byte(RSI)]), "40 0f 94 c6");
        assert_eq!(hex("sete", &[byte(RAX)]), "0f 94 c0");
        // And the one instruction that names the high byte, which may have no such byte at all.
        assert_eq!(hex("movb", &[Value::High(RAX), byte(RDX)]), "88 e2");
        let mut out = Vec::new();
        let error = encode("movb", &[Value::High(RAX), byte(RSI)], &mut out)
            .expect_err("ah and sil in one instruction");
        assert_eq!(error, Error::Crowded { mnemonic: "movb".to_owned() });
    }

    #[test]
    fn an_immediate_is_written_in_as_few_bytes_as_it_fits_in() {
        assert_eq!(hex("addl", &[Value::Imm(1), long(RCX)]), "83 c1 01");
        assert_eq!(hex("addl", &[Value::Imm(-1), long(RCX)]), "83 c1 ff");
        assert_eq!(hex("addl", &[Value::Imm(1000), long(RCX)]), "81 c1 e8 03 00 00");
        assert_eq!(hex("addq", &[Value::Imm(8), quad(RSP)]), "48 83 c4 08");
        // The move is the one instruction with an eight byte immediate, and it is ten bytes long
        // when it needs one and seven when it does not.
        assert_eq!(hex("movq", &[Value::Imm(1), quad(RAX)]), "48 c7 c0 01 00 00 00");
        assert_eq!(
            hex("movq", &[Value::Imm(0x1_2345_6789), quad(RAX)]),
            "48 b8 89 67 45 23 01 00 00 00"
        );
        // A thirty two bit move of a constant is never the ten byte form, because there is no
        // thirty two bit register that could hold a number too big for four bytes. It is also the
        // one place the destination is in the opcode rather than in a byte of its own, which is
        // what makes it five bytes where the sixty four bit form is seven.
        assert_eq!(hex("movl", &[Value::Imm(1), long(RAX)]), "b8 01 00 00 00");
        assert_eq!(hex("movl", &[Value::Imm(1), long(RCX)]), "b9 01 00 00 00");
        assert_eq!(hex("movw", &[Value::Imm(1), word(RAX)]), "66 b8 01 00");
        assert_eq!(hex("movb", &[Value::Imm(1), byte(RCX)]), "b1 01");
        // A byte register the opcode has no number for without a prefix still gets the prefix,
        // because the register is counted the same way whichever field it lands in.
        assert_eq!(hex("movb", &[Value::Imm(1), byte(RSI)]), "40 b6 01");
    }

    /// The eighth of the eight that share an opcode column, which is the one that keeps none of
    /// the answer and only the flags. Its `/digit` is seven, so the byte naming the register is
    /// `0xf8` plus its number rather than `0xc0` plus it, and getting that column wrong is the
    /// failure that writes a subtraction where a comparison was meant.
    #[test]
    fn a_comparison_against_an_immediate_is_the_eighth_column_of_the_shared_opcode() {
        assert_eq!(hex("cmpl", &[Value::Imm(1), long(RCX)]), "83 f9 01");
        assert_eq!(hex("cmpl", &[Value::Imm(-1), long(RCX)]), "83 f9 ff");
        assert_eq!(hex("cmpl", &[Value::Imm(1000), long(RCX)]), "81 f9 e8 03 00 00");
        assert_eq!(hex("cmpq", &[Value::Imm(8), quad(RSP)]), "48 83 fc 08");
        assert_eq!(hex("cmpq", &[Value::Imm(100_000), quad(RAX)]), "48 81 f8 a0 86 01 00");
        assert_eq!(hex("cmpw", &[Value::Imm(1), word(RAX)]), "66 83 f8 01");
        assert_eq!(hex("cmpw", &[Value::Imm(1000), word(RAX)]), "66 81 f8 e8 03");
        assert_eq!(hex("cmpb", &[Value::Imm(200), byte(RAX)]), "80 f8 c8");
        // Sixty four bits carries four bytes of immediate at the most, and a number needing more
        // is refused here the way it is refused for the arithmetic, rather than cut down.
        let mut out = Vec::new();
        let big = 0x1_2345_6789;
        let error = encode("cmpq", &[Value::Imm(big), quad(RAX)], &mut out)
            .expect_err("more than four bytes of immediate");
        assert_eq!(error, Error::Immediate { mnemonic: "cmpq".to_owned(), imm: big });
    }

    #[test]
    fn an_address_is_the_registers_it_names_and_whatever_is_added_to_them() {
        // A base on its own, which is the shortest.
        let base = Addr { base: Some(RCX), ..Addr::default() };
        assert_eq!(hex("movq", &[Value::Mem(base), quad(RAX)]), "48 8b 01");
        // A base and a displacement, in one byte where it fits and four where it does not.
        let near = Addr { base: Some(RCX), disp: -16, ..Addr::default() };
        assert_eq!(hex("movq", &[Value::Mem(near), quad(RAX)]), "48 8b 41 f0");
        let far = Addr { base: Some(RCX), disp: 1000, ..Addr::default() };
        assert_eq!(hex("movq", &[Value::Mem(far), quad(RAX)]), "48 8b 81 e8 03 00 00");
        // A base, an index and a scale, which needs the second byte.
        let indexed =
            Addr { base: Some(RCX), index: Some(RDX), scale: 4, disp: -16, ..Addr::default() };
        assert_eq!(hex("leaq", &[Value::Mem(indexed), quad(RAX)]), "48 8d 44 91 f0");
        // A store is the same address with the two ends the other way round.
        assert_eq!(hex("movl", &[long(RAX), Value::Mem(near)]), "89 41 f0");
    }

    #[test]
    fn a_bit_in_memory_is_set_where_it_lives() {
        // What a template writes to set a bit of a signal set without reading the set first, with
        // the bit number in a register and then written into the instruction.
        let base = Addr { base: Some(RCX), ..Addr::default() };
        assert_eq!(hex("btsl", &[long(RAX), Value::Mem(base)]), "0f ab 01");
        assert_eq!(hex("btrq", &[quad(RAX), Value::Mem(base)]), "48 0f b3 01");
        assert_eq!(hex("btsl", &[Value::Imm(5), Value::Mem(base)]), "0f ba 29 05");
        assert_eq!(hex("btcw", &[Value::Imm(3), Value::Mem(base)]), "66 0f ba 39 03");
    }

    #[test]
    fn a_repeat_prefix_is_in_front_of_everything_but_the_operand_size() {
        // The prefix has to come before the `REX` a quadword carries, since a prefix after one
        // makes the processor ignore it, and it may come either side of the operand size prefix.
        assert_eq!(hex("rep movsl", &[]), "f3 a5");
        assert_eq!(hex("rep movsq", &[]), "f3 48 a5");
        assert_eq!(hex("rep movsw", &[]), "66 f3 a5");
        assert_eq!(hex("repne scasb", &[]), "f2 ae");
        assert_eq!(hex("repe cmpsq", &[]), "f3 48 a7");
        assert_eq!(hex("lodsb", &[]), "ac");
        assert_eq!(hex("stosw", &[]), "66 ab");
    }

    #[test]
    fn the_two_registers_an_address_cannot_be_written_with_plainly_are_written_around() {
        // The stack pointer's number means there is a second byte rather than a register, so an
        // address really based on it needs that byte even with nothing to put in it.
        let stack = Addr { base: Some(RSP), disp: 8, ..Addr::default() };
        assert_eq!(hex("movq", &[Value::Mem(stack), quad(RAX)]), "48 8b 44 24 08");
        // And the frame pointer's number with no displacement means the address is counted from
        // the end of the instruction, so one based on it always carries one.
        let frame = Addr { base: Some(RBP), ..Addr::default() };
        assert_eq!(hex("movq", &[Value::Mem(frame), quad(RAX)]), "48 8b 45 00");
        // The same two facts hold of the registers whose low three bits are theirs.
        let twelve = Addr { base: Some(R12), disp: 8, ..Addr::default() };
        assert_eq!(hex("movq", &[Value::Mem(twelve), quad(RAX)]), "49 8b 44 24 08");
        let thirteen = Addr { base: Some(R13), ..Addr::default() };
        assert_eq!(hex("movq", &[Value::Mem(thirteen), quad(RAX)]), "49 8b 45 00");
        // The stack pointer is the one register that cannot be an index at all.
        let mut out = Vec::new();
        let bad = Addr { base: Some(RCX), index: Some(RSP), scale: 1, ..Addr::default() };
        let error = encode("leaq", &[Value::Mem(bad), quad(RAX)], &mut out)
            .expect_err("the stack pointer as an index");
        assert_eq!(error, Error::Index);
    }

    #[test]
    fn an_address_in_a_thread_s_own_block_is_a_prefix_and_a_constant_and_no_register() {
        // What every protected function on this platform starts with. The prefix comes first of
        // everything, in front of the one that says the operands are sixty-four bits wide, and the
        // address itself names no register at all: `04 25` is the byte pair that means a second
        // addressing byte with no base and no index in it, and then four bytes of constant.
        let guard = Addr { segment: Some(Segment::Fs), disp: 40, ..Addr::default() };
        assert_eq!(hex("movq", &[Value::Mem(guard), quad(RAX)]), "64 48 8b 04 25 28 00 00 00");
        // The other segment, which is the same instruction with the other prefix byte.
        let other = Addr { segment: Some(Segment::Gs), disp: 40, ..Addr::default() };
        assert_eq!(hex("movq", &[Value::Mem(other), quad(RAX)]), "65 48 8b 04 25 28 00 00 00");
        // A register the upper eight, so that the prefix that says so is in the picture too: it
        // goes behind the segment and in front of nothing else, which is the order the machine
        // reads them in.
        let guard = Addr { segment: Some(Segment::Fs), disp: 40, ..Addr::default() };
        assert_eq!(hex("movq", &[Value::Mem(guard), quad(R12)]), "64 4c 8b 24 25 28 00 00 00");
    }

    /// The one instruction here that writes a number to an address, which is a probing prologue
    /// touching the page it has just reached.
    ///
    /// Four bytes, and the middle two are the same pair the stack pointer always needs: its number
    /// in an addressing byte means there is a second byte rather than a register, and the second
    /// byte then says the base is the stack pointer and there is no index. The extension in the
    /// first of them is the one that says this is an inclusive or rather than any of the other
    /// seven instructions that share the opcode, and the last byte is the zero that makes it leave
    /// the page alone.
    #[test]
    fn the_probe_a_prologue_touches_a_page_with_is_the_shortest_write_the_machine_has() {
        let top = Addr { base: Some(RSP), ..Addr::default() };
        assert_eq!(hex("orb", &[Value::Imm(0), Value::Mem(top)]), "80 0c 24 00");
        // Where the loop below a large frame looks, which is the same instruction reaching further
        // down and carrying the displacement it needs.
        let down = Addr { base: Some(RSP), disp: -4096, ..Addr::default() };
        assert_eq!(hex("orb", &[Value::Imm(0), Value::Mem(down)]), "80 8c 24 00 f0 ff ff 00");
    }

    /// The landing pad a prologue writes under `-fcf-protection=branch`.
    ///
    /// Four bytes and none of them chosen, since it has no operands: the whole of it including the
    /// addressing byte at the end is the opcode. The bytes matter because a machine with no check
    /// in it reads the same four as a wider `nop`, which is what lets one object run on a machine
    /// that enforces this and on one that has never heard of it.
    #[test]
    fn the_landing_pad_is_four_bytes_and_none_of_them_are_worked_out() {
        assert_eq!(hex("endbr64", &[]), "f3 0f 1e fa");
        assert_eq!(hex("ud2", &[]), "0f 0b");
    }

    /// The two bytes the speculation hardening flags write, each on its own: the breakpoint that
    /// stops speculation past a return and the segment override that pads a thunk call.
    #[test]
    fn the_breakpoint_and_the_segment_override_are_one_byte_each() {
        assert_eq!(hex("int3", &[]), "cc");
        assert_eq!(hex("cs", &[]), "2e");
    }

    /// The two x87 instructions, whose bytes are checked against what the assembler writes for the
    /// same lines rather than against the manual, the way every other group here is.
    ///
    /// They are the only instructions on this machine with one argument that is an address and no
    /// register argument at all, so the addressing byte carries the extension where every other
    /// memory instruction carries a register, and the two of them differ in nothing else.
    #[test]
    fn the_x87_load_and_store_are_one_opcode_with_two_extensions() {
        let base = Addr { base: Some(RCX), ..Addr::default() };
        assert_eq!(hex("fldt", &[Value::Mem(base)]), "db 29");
        assert_eq!(hex("fstpt", &[Value::Mem(base)]), "db 39");
        // A displacement, which is where a `long double` in a frame really is.
        let near = Addr { base: Some(RCX), disp: -16, ..Addr::default() };
        assert_eq!(hex("fldt", &[Value::Mem(near)]), "db 69 f0");
        let stack = Addr { base: Some(RSP), disp: 8, ..Addr::default() };
        assert_eq!(hex("fstpt", &[Value::Mem(stack)]), "db 7c 24 08");
        // The two registers an address is written around, and the one that needs a REX byte, which
        // is the only byte an x87 instruction has that says anything about a register at all.
        let frame = Addr { base: Some(RBP), ..Addr::default() };
        assert_eq!(hex("fldt", &[Value::Mem(frame)]), "db 6d 00");
        let thirteen = Addr { base: Some(R13), disp: -16, ..Addr::default() };
        assert_eq!(hex("fstpt", &[Value::Mem(thirteen)]), "41 db 7d f0");
        let indexed = Addr { base: Some(RCX), index: Some(RDX), scale: 4, ..Addr::default() };
        assert_eq!(hex("fldt", &[Value::Mem(indexed)]), "db 2c 91");
    }

    /// The conversions, whose bytes are the part of this corner of the machine worth checking
    /// against the assembler rather than reading off a page.
    ///
    /// The width of the operand is in the opcode byte rather than in a prefix, which is the
    /// opposite of every other group here, and load and store are two extensions of the same
    /// byte. So a mistake in one of these is a mistake that encodes to a real instruction doing
    /// something else at another width, which is exactly the mistake nothing downstream catches.
    #[test]
    fn the_x87_conversions_put_the_width_in_the_opcode_and_the_direction_in_the_extension() {
        let base = Addr { base: Some(RCX), ..Addr::default() };
        let at = |mnemonic| hex(mnemonic, &[Value::Mem(base)]);
        // Up: four bytes of float, eight bytes of float, four of integer, eight of integer.
        assert_eq!(at("flds"), "d9 01");
        assert_eq!(at("fldl"), "dd 01");
        assert_eq!(at("fildl"), "db 01");
        assert_eq!(at("fildll"), "df 29");
        // Down: the same four opcodes with the extension that stores and pops.
        assert_eq!(at("fstps"), "d9 19");
        assert_eq!(at("fstpl"), "dd 19");
        assert_eq!(at("fistpl"), "db 19");
        assert_eq!(at("fistpll"), "df 39");
        // The control word, which is two more extensions of the byte the four byte float uses.
        assert_eq!(at("fnstcw"), "d9 39");
        assert_eq!(at("fldcw"), "d9 29");
        // And an address that is not the shortest one, since a frame is where all of these really
        // point and nothing in a frame is at the address a register holds.
        let frame = Addr { base: Some(RBP), disp: -16, ..Addr::default() };
        assert_eq!(hex("fildl", &[Value::Mem(frame)]), "db 45 f0");
        let stack = Addr { base: Some(RSP), disp: 8, ..Addr::default() };
        assert_eq!(hex("fistpll", &[Value::Mem(stack)]), "df 7c 24 08");
    }

    /// The x87 arithmetic, which is two constant bytes each and nothing worked out from anything.
    ///
    /// Worth checking one by one all the same, because the second byte is where the operation and
    /// the depth both live and a row with the wrong one in it would assemble to a different
    /// instruction rather than to nothing. The bytes are what the system assembler produces for
    /// the same lines.
    #[test]
    fn the_x87_arithmetic_is_two_constant_bytes_with_the_operation_in_the_second() {
        let pair = [Value::Stack, Value::Stack];
        let op = |mnemonic| hex(mnemonic, &pair);
        assert_eq!(op("faddp"), "de c1");
        assert_eq!(op("fmulp"), "de c9");
        // The two directions, which differ in one bit of the second byte and are the whole reason
        // a subtraction and a division are two opcodes here and an addition is one.
        assert_eq!(op("fsubp"), "de e1");
        assert_eq!(op("fsubrp"), "de e9");
        assert_eq!(op("fdivp"), "de f1");
        assert_eq!(op("fdivrp"), "de f9");
        // The two that name nothing at all, not even a depth, because there is one value they
        // could be talking about.
        assert_eq!(hex("fchs", &[]), "d9 e0");
        assert_eq!(hex("fabs", &[]), "d9 e1");
        // The comparison and the pop that gets the operand it did not take off the stack.
        assert_eq!(op("fucomip"), "df e9");
        assert_eq!(hex("fstp", &[Value::Stack]), "dd d8");
        assert_eq!(hex("fprem", &[]), "d9 f8");
        assert_eq!(hex("fpatan", &[]), "d9 f3");
        assert_eq!(hex("fsqrt", &[]), "d9 fa");
        assert_eq!(hex("fldpi", &[]), "d9 eb");
        assert_eq!(hex("fldz", &[]), "d9 ee");
        assert_eq!(hex("fnstsw", &[Value::Reg(RAX, Width::Word)]), "df e0");
    }

    #[test]
    fn an_address_counted_from_the_end_of_the_instruction_leaves_its_displacement_open() {
        let global = Addr { rip: true, ..Addr::default() };
        let mut out = vec![0xcc];
        let holes = encode("movq", &[Value::Mem(global), quad(RAX)], &mut out).expect("a global");
        assert_eq!(out, [0xcc, 0x48, 0x8b, 0x05, 0, 0, 0, 0]);
        // Where the four bytes are, counted in the buffer rather than in the instruction, because
        // what the caller does with it is record a relocation against the buffer.
        assert_eq!(holes.rip, Some(4));
        assert_eq!(holes.dest, None);
    }

    #[test]
    fn a_jump_leaves_the_distance_to_where_it_goes_open() {
        let mut out = Vec::new();
        let holes = encode("jmp", &[Value::Dest], &mut out).expect("a jump");
        assert_eq!(out, [0xe9, 0, 0, 0, 0]);
        assert_eq!(holes.dest, Some(1));
        out.clear();
        let holes = encode("je", &[Value::Dest], &mut out).expect("a conditional jump");
        assert_eq!(out, [0x0f, 0x84, 0, 0, 0, 0]);
        assert_eq!(holes.dest, Some(2));
    }

    #[test]
    fn an_instruction_with_no_arguments_is_the_opcode_and_whatever_says_how_wide_it_is() {
        assert_eq!(hex("ret", &[]), "c3");
        assert_eq!(hex("cltd", &[]), "99");
        assert_eq!(hex("cqto", &[]), "48 99");
        assert_eq!(hex("cwtd", &[]), "66 99");
        assert_eq!(hex("cbtw", &[]), "66 98");
        assert_eq!(hex("cwtl", &[]), "98");
        assert_eq!(hex("cltq", &[]), "48 98");
        assert_eq!(hex("leave", &[]), "c9");
    }

    /// Every bit of a thirty two bit immediate set is minus one, which a byte holds.
    #[test]
    fn a_long_immediate_with_every_bit_set_takes_the_byte_form() {
        assert_eq!(hex("andl", &[Value::Imm(0xFFFF_FFFF), long(RAX)]), "83 e0 ff");
        assert_eq!(hex("andw", &[Value::Imm(0xFFFF), Value::Reg(RAX, Width::Word)]), "66 83 e0 ff");
        assert_eq!(hex("andl", &[Value::Imm(0x8000_0000), long(RAX)]), "81 e0 00 00 00 80");
    }

    /// `notrack` is a prefix like the operand size one and goes where that one does, in front of
    /// the REX byte a register past the first eight needs, so the REX byte stays next to the opcode.
    #[test]
    fn notrack_goes_in_front_of_the_rex_byte() {
        assert_eq!(hex("notrack jmp", &[quad(RAX)]), "3e ff e0");
        assert_eq!(hex("notrack jmp", &[quad(R8)]), "3e 41 ff e0");
        assert_eq!(hex("notrack call", &[quad(RDX)]), "3e ff d2");
    }

    #[test]
    fn a_shift_by_a_count_does_not_encode_the_count_because_the_machine_knows_where_it_is() {
        // Two arguments written and one encoded, which is the case that says why an argument
        // names an operand rather than being one.
        assert_eq!(hex("shlq", &[byte(RCX), quad(RAX)]), "48 d3 e0");
        assert_eq!(hex("sarl", &[byte(RCX), long(RCX)]), "d3 f9");
        assert_eq!(hex("shll", &[Value::Imm(3), long(RAX)]), "c1 e0 03");
    }

    #[test]
    fn a_division_is_the_widening_and_then_the_instruction_that_names_only_its_divisor() {
        assert_eq!(hex("idivl", &[long(RCX)]), "f7 f9");
        assert_eq!(hex("idivq", &[quad(RSI)]), "48 f7 fe");
        assert_eq!(hex("divl", &[long(RCX)]), "f7 f1");
        assert_eq!(hex("negl", &[long(RAX)]), "f7 d8");
        assert_eq!(hex("notq", &[quad(RAX)]), "48 f7 d0");
    }

    /// A compare and exchange, and the prefix that makes it indivisible.
    ///
    /// The prefix is a row with no arguments because that is what it is in the encoding, one byte
    /// in front of whatever follows it, and the instruction it applies to encodes the same either
    /// way. The instruction itself names the address in the r/m field and the value it would put
    /// there in the register field, which is the direction a store has and the reverse of the one a
    /// conditional move has. Checked against what the assembler makes of the same six lines.
    #[test]
    fn a_compare_and_exchange_is_the_prefix_and_then_a_store_shaped_instruction() {
        let at = Addr { base: Some(RAX), ..Addr::default() };
        assert_eq!(hex("lock", &[]), "f0");
        assert_eq!(hex("cmpxchgb", &[byte(RCX), Value::Mem(at)]), "0f b0 08");
        assert_eq!(hex("cmpxchgw", &[word(RCX), Value::Mem(at)]), "66 0f b1 08");
        assert_eq!(hex("cmpxchgl", &[long(RCX), Value::Mem(at)]), "0f b1 08");
        assert_eq!(hex("cmpxchgq", &[quad(RCX), Value::Mem(at)]), "48 0f b1 08");
        // The byte form reaches the second half of the register file the same way every other byte
        // form does, which is worth a line because the register it names is one the allocator picks
        // and the other one is always `rax`.
        assert_eq!(hex("cmpxchgb", &[byte(RSI), Value::Mem(at)]), "40 0f b0 30");
    }

    /// The two read modify writes, which name their operands the way a compare and exchange does
    /// and are two different opcodes rather than two spellings of one. The exchange has no prefix in
    /// front of it, which is the machine and not an omission: an exchange with memory is indivisible
    /// whether the prefix is written or not. Checked against what the assembler makes of the same
    /// eight lines.
    #[test]
    fn a_read_modify_write_names_the_address_the_way_a_compare_and_exchange_does() {
        let at = Addr { base: Some(RAX), ..Addr::default() };
        assert_eq!(hex("xchgb", &[byte(RCX), Value::Mem(at)]), "86 08");
        assert_eq!(hex("xchgw", &[word(RCX), Value::Mem(at)]), "66 87 08");
        assert_eq!(hex("xchgl", &[long(RCX), Value::Mem(at)]), "87 08");
        assert_eq!(hex("xchgq", &[quad(RCX), Value::Mem(at)]), "48 87 08");
        assert_eq!(hex("xaddb", &[byte(RCX), Value::Mem(at)]), "0f c0 08");
        assert_eq!(hex("xaddw", &[word(RCX), Value::Mem(at)]), "66 0f c1 08");
        assert_eq!(hex("xaddl", &[long(RCX), Value::Mem(at)]), "0f c1 08");
        assert_eq!(hex("xaddq", &[quad(RCX), Value::Mem(at)]), "48 0f c1 08");
        // The byte form reaching the second half of the register file, for the reason above.
        assert_eq!(hex("xchgb", &[byte(RSI), Value::Mem(at)]), "40 86 30");
    }

    /// The two bytes of a word exchanged with each other, which is the same instruction with both
    /// of its arguments in one register and is the only way this machine says a sixteen bit byte
    /// swap. The high byte is numbered as the low one plus four, which is the whole of the
    /// difference between them in the bytes and is also why only the first four registers have one.
    #[test]
    fn the_high_byte_of_a_register_is_the_low_one_four_places_along() {
        assert_eq!(hex("xchgb", &[byte(RAX), Value::High(RAX)]), "86 c4");
        assert_eq!(hex("xchgb", &[byte(RCX), Value::High(RCX)]), "86 cd");
        assert_eq!(hex("xchgb", &[byte(RDX), Value::High(RDX)]), "86 d6");
        assert_eq!(hex("xchgb", &[byte(RBX), Value::High(RBX)]), "86 df");
    }

    #[test]
    fn a_conversion_puts_its_destination_where_the_arithmetic_puts_its_source() {
        assert_eq!(hex("movzbl", &[byte(RAX), long(RCX)]), "0f b6 c8");
        assert_eq!(hex("movsbq", &[byte(RAX), quad(RCX)]), "48 0f be c8");
        assert_eq!(hex("movslq", &[long(RSI), quad(RAX)]), "48 63 c6");
        assert_eq!(hex("movzwl", &[Value::Reg(RSI, Width::Word), long(RAX)]), "0f b7 c6");
    }

    /// The rows the listing never names, whose bytes are what gas writes for the same lines.
    ///
    /// Every other group here is checked against the manual because the compiler emits it and a
    /// mistake would show up as a program that runs wrong. These are only ever reached by reading
    /// somebody else's file, so the thing worth pinning is that this compiler and gas agree about
    /// what the line means, and the way to get that is to assemble the same lines with gas and
    /// write down what came out. That is what these strings are.
    ///
    /// The accumulator and the shift by one have shorter forms that gas picks and this does not,
    /// so the cases below are written around them: `adcb $200, %cl` rather than `%al`, `rorl $5`
    /// rather than `$1`. Choosing a shorter encoding of the same instruction is a separate job
    /// from having the instruction at all, and it belongs with branch relaxation.
    #[test]
    fn the_instructions_a_hand_written_file_uses_and_a_compiler_never_emits() {
        // The two of the eight that carry the flag, in all three shapes the other six have.
        assert_eq!(hex("adcb", &[byte(RCX), byte(RAX)]), "10 c8");
        assert_eq!(hex("adcw", &[word(RCX), word(RAX)]), "66 11 c8");
        assert_eq!(hex("adcl", &[long(RCX), long(RAX)]), "11 c8");
        assert_eq!(hex("adcq", &[quad(RCX), quad(RAX)]), "48 11 c8");
        assert_eq!(hex("sbbq", &[quad(RCX), quad(RAX)]), "48 19 c8");
        let at = Addr { base: Some(RDX), ..Addr::default() };
        assert_eq!(hex("adcq", &[Value::Mem(at), quad(R8)]), "4c 13 02");
        assert_eq!(hex("sbbb", &[Value::Mem(at), byte(RAX)]), "1a 02");
        assert_eq!(hex("adcq", &[Value::Imm(1), quad(RAX)]), "48 83 d0 01");
        assert_eq!(hex("adcl", &[Value::Imm(1000), long(RCX)]), "81 d1 e8 03 00 00");
        assert_eq!(hex("sbbq", &[Value::Imm(-1), quad(R8)]), "49 83 d8 ff");
        assert_eq!(hex("adcb", &[Value::Imm(200), byte(RCX)]), "80 d1 c8");
        // Adding one and taking one away, which are not an addition of one.
        assert_eq!(hex("incl", &[long(RAX)]), "ff c0");
        assert_eq!(hex("incq", &[quad(RCX)]), "48 ff c1");
        assert_eq!(hex("incw", &[word(RAX)]), "66 ff c0");
        assert_eq!(hex("incb", &[byte(RSI)]), "40 fe c6");
        assert_eq!(hex("decq", &[quad(RCX)]), "48 ff c9");
        // The one operand multiplies, which write two registers and name one.
        assert_eq!(hex("mulq", &[quad(RDX)]), "48 f7 e2");
        assert_eq!(hex("mulb", &[byte(RCX)]), "f6 e1");
        assert_eq!(hex("imulq", &[quad(RDX)]), "48 f7 ea");
        // The rotates, in both shapes the shifts beside them have.
        assert_eq!(hex("rolq", &[Value::Imm(3), quad(RAX)]), "48 c1 c0 03");
        assert_eq!(hex("rorl", &[Value::Imm(5), long(RCX)]), "c1 c9 05");
        assert_eq!(hex("rolb", &[byte(RCX), byte(RDX)]), "d2 c2");
        assert_eq!(hex("rorq", &[byte(RCX), quad(RAX)]), "48 d3 c8");
        // The bit tests, whose immediate form is one opcode and four extensions and whose register
        // form is four opcodes, written the way the arithmetic is.
        assert_eq!(hex("btq", &[Value::Imm(0), quad(R8)]), "49 0f ba e0 00");
        assert_eq!(hex("btsq", &[Value::Imm(63), quad(RAX)]), "48 0f ba e8 3f");
        assert_eq!(hex("btrl", &[Value::Imm(2), long(RCX)]), "0f ba f1 02");
        assert_eq!(hex("btcw", &[Value::Imm(1), word(RDX)]), "66 0f ba fa 01");
        assert_eq!(hex("btq", &[quad(RDX), quad(RAX)]), "48 0f a3 d0");
        assert_eq!(hex("btsl", &[long(RCX), long(RAX)]), "0f ab c8");
        // The bit scans, written the way the conversions are, and the counts behind them, which
        // are the same two opcodes with the prefix that makes them different instructions.
        assert_eq!(hex("bsfq", &[quad(RAX), quad(RDX)]), "48 0f bc d0");
        assert_eq!(hex("bsrl", &[long(RAX), long(RCX)]), "0f bd c8");
        assert_eq!(hex("lzcntl", &[long(RDX), long(RAX)]), "f3 0f bd c2");
        assert_eq!(hex("lzcntq", &[quad(RDX), quad(RAX)]), "f3 48 0f bd c2");
        assert_eq!(hex("tzcntl", &[long(RDX), long(RAX)]), "f3 0f bc c2");
        assert_eq!(hex("tzcntq", &[quad(RDX), quad(RAX)]), "f3 48 0f bc c2");
        let counted = Addr { base: Some(RBX), ..Addr::default() };
        assert_eq!(hex("lzcntq", &[Value::Mem(counted), quad(RAX)]), "f3 48 0f bd 03");
        assert_eq!(hex("tzcntl", &[Value::Mem(counted), long(RAX)]), "f3 0f bc 03");
        // The population count beside them, and the checksum step, whose sixteen bit form is the
        // one row here with two prefix bytes. Every expected string is what GNU as 2.46 writes
        // for the same line.
        assert_eq!(hex("popcntl", &[long(RDX), long(RAX)]), "f3 0f b8 c2");
        assert_eq!(hex("popcntq", &[quad(RDX), quad(RAX)]), "f3 48 0f b8 c2");
        assert_eq!(hex("popcntq", &[quad(R8), quad(RAX)]), "f3 49 0f b8 c0");
        assert_eq!(hex("popcntl", &[Value::Mem(counted), long(RAX)]), "f3 0f b8 03");
        assert_eq!(hex("crc32b", &[byte(RCX), long(RAX)]), "f2 0f 38 f0 c1");
        assert_eq!(hex("crc32b", &[byte(RSI), long(RAX)]), "f2 40 0f 38 f0 c6");
        assert_eq!(hex("crc32w", &[word(RCX), long(RAX)]), "66 f2 0f 38 f1 c1");
        assert_eq!(hex("crc32w", &[word(R9), long(R10)]), "66 f2 45 0f 38 f1 d1");
        assert_eq!(hex("crc32l", &[long(RCX), long(RAX)]), "f2 0f 38 f1 c1");
        assert_eq!(hex("crc32l", &[long(R8), long(RDX)]), "f2 41 0f 38 f1 d0");
        assert_eq!(hex("crc32q", &[quad(RCX), quad(RAX)]), "f2 48 0f 38 f1 c1");
        assert_eq!(hex("crc32q", &[quad(R12), quad(R13)]), "f2 4d 0f 38 f1 ec");
        assert_eq!(hex("crc32b", &[Value::Mem(counted), long(RAX)]), "f2 0f 38 f0 03");
        assert_eq!(hex("crc32q", &[Value::Mem(counted), quad(RAX)]), "f2 48 0f 38 f1 03");
        // Reversing the bytes of a register, whose register is in the opcode and not beside it, so
        // the high half of the register file moves the prefix rather than a bit of an addressing
        // byte. `bswapq` on `r12` is the one that shows both at once.
        assert_eq!(hex("bswapl", &[long(RAX)]), "0f c8");
        assert_eq!(hex("bswapq", &[quad(RAX)]), "48 0f c8");
        assert_eq!(hex("bswapl", &[long(RDX)]), "0f ca");
        assert_eq!(hex("bswapq", &[quad(R12)]), "49 0f cc");
        // The widenings reading memory, which is the shape only `movzbl` had.
        let from = Addr { base: Some(RSI), ..Addr::default() };
        assert_eq!(hex("movzbq", &[Value::Mem(from), quad(RAX)]), "48 0f b6 06");
        assert_eq!(hex("movzwl", &[Value::Mem(from), long(RAX)]), "0f b7 06");
        assert_eq!(hex("movsbl", &[Value::Mem(from), long(RAX)]), "0f be 06");
        assert_eq!(hex("movslq", &[Value::Mem(from), quad(RAX)]), "48 63 06");
        let along = Addr { base: Some(RSI), disp: 4, ..Addr::default() };
        assert_eq!(hex("movswq", &[Value::Mem(along), quad(RDX)]), "48 0f bf 56 04");
        // The address computation that keeps thirty two bits, which is an addition that leaves the
        // flags alone and is why a hand written file reaches for it.
        let sum = Addr { base: Some(RSI), index: Some(RDX), scale: 2, ..Addr::default() };
        assert_eq!(hex("leal", &[Value::Mem(sum), long(RAX)]), "8d 04 56");
        // The long move under the name a file gives it when it wants the long one.
        assert_eq!(hex("movabsq", &[Value::Imm(-1), quad(RAX)]), "48 b8 ff ff ff ff ff ff ff ff");
        // A push and a pop of memory, which are not the short forms above them.
        let deep = Addr { base: Some(RAX), ..Addr::default() };
        assert_eq!(hex("pushq", &[Value::Mem(deep)]), "ff 30");
        assert_eq!(hex("popq", &[Value::Mem(deep)]), "8f 00");
        // The exchange between two registers, which needs no lock.
        assert_eq!(hex("xchgl", &[long(RCX), long(RDX)]), "87 ca");
        // The scalar move between two vector registers, which this compiler writes as `movaps`.
        assert_eq!(hex("movss", &[Value::Xmm(xmm(0)), Value::Xmm(xmm(1))]), "f3 0f 10 c8");
        assert_eq!(hex("movsd", &[Value::Xmm(xmm(2)), Value::Xmm(xmm(3))]), "f2 0f 10 da");
    }

    /// The rows a loop in GMP needs, whose bytes are again what gas writes for the same lines.
    ///
    /// Same rule as the group above and for the same reason. Every string here came out of
    /// `objdump` on an object gas made, so a disagreement means this compiler reads a line
    /// differently from the assembler every one of these files was written against.
    ///
    /// The accumulator form of the test is the one thing here gas writes shorter, `a9` against
    /// `f7 c0`, and it is the same deferral the group above describes: the table cannot say a row
    /// applies only when the destination is `rax`, so having that form at all needs a way to
    /// constrain a row by register and that goes in with relaxation.
    #[test]
    fn the_instructions_a_hand_written_loop_writes_into_memory() {
        // The eight with a register read and an address written, which is the opcode the register
        // form uses with the addressing byte naming memory instead.
        let at = Addr { base: Some(RDI), ..Addr::default() };
        assert_eq!(hex("addq", &[quad(RAX), Value::Mem(at)]), "48 01 07");
        assert_eq!(hex("addb", &[byte(RAX), Value::Mem(at)]), "00 07");
        assert_eq!(hex("addw", &[word(RAX), Value::Mem(at)]), "66 01 07");
        assert_eq!(hex("orq", &[quad(R8), Value::Mem(at)]), "4c 09 07");
        assert_eq!(hex("sbbq", &[quad(RAX), Value::Mem(at)]), "48 19 07");
        assert_eq!(hex("andq", &[quad(RAX), Value::Mem(at)]), "48 21 07");
        assert_eq!(hex("subq", &[quad(RAX), Value::Mem(at)]), "48 29 07");
        assert_eq!(hex("xorq", &[quad(RAX), Value::Mem(at)]), "48 31 07");
        assert_eq!(hex("cmpq", &[quad(RAX), Value::Mem(at)]), "48 39 07");
        assert_eq!(hex("cmpq", &[Value::Mem(at), quad(RAX)]), "48 3b 07");
        let indexed = Addr { base: Some(RDI), index: Some(R8), scale: 8, disp: 8, ..at };
        assert_eq!(hex("adcq", &[quad(R15), Value::Mem(indexed)]), "4e 11 7c c7 08");
        // The same eight with a number written instead of a register, which narrows the way the
        // register with immediate rows above it do.
        assert_eq!(hex("addq", &[Value::Imm(1), Value::Mem(at)]), "48 83 07 01");
        assert_eq!(hex("addq", &[Value::Imm(1000), Value::Mem(at)]), "48 81 07 e8 03 00 00");
        assert_eq!(hex("addl", &[Value::Imm(1), Value::Mem(at)]), "83 07 01");
        assert_eq!(hex("addw", &[Value::Imm(1), Value::Mem(at)]), "66 83 07 01");
        assert_eq!(hex("addb", &[Value::Imm(1), Value::Mem(at)]), "80 07 01");
        assert_eq!(hex("subq", &[Value::Imm(8), Value::Mem(at)]), "48 83 2f 08");
        assert_eq!(hex("cmpq", &[Value::Imm(0), Value::Mem(at)]), "48 83 3f 00");
        assert_eq!(hex("andl", &[Value::Imm(255), Value::Mem(at)]), "81 27 ff 00 00 00");
        // The test at the widths the compiler never asks for and against a number, whose immediate
        // is the full width however small it is.
        assert_eq!(hex("testq", &[quad(RAX), quad(RAX)]), "48 85 c0");
        assert_eq!(hex("testl", &[long(RAX), long(RAX)]), "85 c0");
        assert_eq!(hex("testw", &[word(RAX), word(RAX)]), "66 85 c0");
        assert_eq!(hex("testq", &[quad(RAX), Value::Mem(at)]), "48 85 07");
        assert_eq!(hex("testq", &[Value::Mem(at), quad(RAX)]), "48 85 07");
        assert_eq!(hex("testq", &[Value::Imm(1), quad(R10)]), "49 f7 c2 01 00 00 00");
        assert_eq!(hex("testq", &[Value::Imm(1), Value::Mem(at)]), "48 f7 07 01 00 00 00");
        assert_eq!(hex("testb", &[Value::Imm(1), byte(RCX)]), "f6 c1 01");
        // The one operand group naming an address, which is the same digit column again.
        let sixteen = Addr { base: Some(R8), disp: 16, ..Addr::default() };
        assert_eq!(hex("mulq", &[Value::Mem(sixteen)]), "49 f7 60 10");
        assert_eq!(hex("mull", &[Value::Mem(at)]), "f7 27");
        assert_eq!(hex("imulq", &[Value::Mem(at)]), "48 f7 2f");
        assert_eq!(hex("divq", &[Value::Mem(at)]), "48 f7 37");
        assert_eq!(hex("idivq", &[Value::Mem(at)]), "48 f7 3f");
        assert_eq!(hex("negq", &[Value::Mem(at)]), "48 f7 1f");
        assert_eq!(hex("notq", &[Value::Mem(at)]), "48 f7 17");
        assert_eq!(hex("incq", &[Value::Mem(at)]), "48 ff 07");
        assert_eq!(hex("decq", &[Value::Mem(at)]), "48 ff 0f");
        assert_eq!(hex("incb", &[Value::Mem(at)]), "fe 07");
        let four = Addr { base: Some(RSI), disp: 4, ..Addr::default() };
        assert_eq!(hex("decl", &[Value::Mem(four)]), "ff 4e 04");
    }

    /// The shifts and rotates a multiple precision loop is built out of.
    #[test]
    fn the_shifts_a_number_wider_than_a_register_needs() {
        // The two that go through the carry, which is what halving a wide number is done with.
        assert_eq!(hex("rclq", &[Value::Imm(3), quad(RAX)]), "48 c1 d0 03");
        assert_eq!(hex("rcrq", &[Value::Imm(3), quad(RAX)]), "48 c1 d8 03");
        assert_eq!(hex("rclq", &[byte(RCX), quad(RAX)]), "48 d3 d0");
        assert_eq!(hex("rcrq", &[byte(RCX), quad(RAX)]), "48 d3 d8");
        // All eight by one place, which is a third opcode and not the constant one written short.
        assert_eq!(hex("rolq", &[quad(RAX)]), "48 d1 c0");
        assert_eq!(hex("rorq", &[quad(RAX)]), "48 d1 c8");
        assert_eq!(hex("rclq", &[quad(RAX)]), "48 d1 d0");
        assert_eq!(hex("rcrq", &[quad(RAX)]), "48 d1 d8");
        assert_eq!(hex("shlq", &[quad(RAX)]), "48 d1 e0");
        assert_eq!(hex("shrq", &[quad(RAX)]), "48 d1 e8");
        assert_eq!(hex("sarq", &[quad(RAX)]), "48 d1 f8");
        assert_eq!(hex("shrl", &[long(RAX)]), "d1 e8");
        assert_eq!(hex("shrb", &[byte(RAX)]), "d0 e8");
        assert_eq!(hex("shrw", &[word(RAX)]), "66 d1 e8");
        // The two that name a register to shift in from, whose addressing byte names the argument
        // at the end and holds the middle one beside it.
        let five = Value::Imm(5);
        assert_eq!(hex("shldq", &[five, quad(RSI), quad(RDI)]), "48 0f a4 f7 05");
        assert_eq!(hex("shrdq", &[five, quad(RSI), quad(RDI)]), "48 0f ac f7 05");
        assert_eq!(hex("shldl", &[five, long(RSI), long(RDI)]), "0f a4 f7 05");
        assert_eq!(hex("shldq", &[byte(RCX), quad(RSI), quad(RDI)]), "48 0f a5 f7");
        assert_eq!(hex("shrdq", &[byte(RCX), quad(RSI), quad(RDI)]), "48 0f ad f7");
        assert_eq!(hex("shldw", &[byte(RCX), word(RSI), word(RDI)]), "66 0f a5 f7");
    }

    /// The three shifts that take their count anywhere, which are the only VEX encoded rows here.
    ///
    /// Every string is what `objdump` printed for an object gas made from the same lines, the same
    /// rule the groups above follow. There is more to check here than usual because the prefix is
    /// where five separate things are written and four of them are written inverted, so a bit put
    /// in the wrong place comes out as a different register or a different instruction rather than
    /// as bytes that decode to nothing.
    #[test]
    fn the_shifts_that_take_their_count_in_any_register() {
        // The three instructions at both widths, with the same three registers throughout, so that
        // the only thing moving between these six lines is the two bits of the mandatory prefix and
        // the wide bit. `c4 e2` is the same in all of them: the map is `0F 38` and none of the three
        // registers is one of the second eight.
        assert_eq!(hex("shlxq", &[quad(RCX), quad(RSI), quad(RDI)]), "c4 e2 f1 f7 fe");
        assert_eq!(hex("shlxl", &[long(RCX), long(RSI), long(RDI)]), "c4 e2 71 f7 fe");
        assert_eq!(hex("sarxq", &[quad(RCX), quad(RSI), quad(RDI)]), "c4 e2 f2 f7 fe");
        assert_eq!(hex("sarxl", &[long(RCX), long(RSI), long(RDI)]), "c4 e2 72 f7 fe");
        assert_eq!(hex("shrxq", &[quad(RCX), quad(RSI), quad(RDI)]), "c4 e2 f3 f7 fe");
        assert_eq!(hex("shrxl", &[long(RCX), long(RSI), long(RDI)]), "c4 e2 73 f7 fe");
        // The count in the last register the machine has, which is the one that says `vvvv` is four
        // bits wide. Fifteen inverted is zero, so the whole field goes to zero and the byte reads
        // `81` where the line above it reads `f9`. Getting this wrong loses the top bit silently and
        // encodes `r15` as `rdi`, and zstd's decoder shifts by `r15`.
        assert_eq!(hex("shlxq", &[quad(R15), quad(RAX), quad(RAX)]), "c4 e2 81 f7 c0");
        assert_eq!(hex("shlxq", &[quad(RAX), quad(RAX), quad(RAX)]), "c4 e2 f9 f7 c0");
        // The other two operands in the second eight, which are the bits REX held and are inverted
        // here as well, so the byte that is `e2` everywhere above is `42` when both are set.
        assert_eq!(hex("shlxq", &[quad(RAX), quad(R8), quad(R8)]), "c4 42 f9 f7 c0");
        assert_eq!(hex("shrxq", &[quad(R15), quad(R15), quad(R15)]), "c4 42 83 f7 ff");
        // Nothing here reaches the two byte form, and that is the point of the pair. The short form
        // can say `0F` for the map and nothing else, and all six rows are in the `0F 38` table, so
        // the prefix is three bytes however small the registers are.
        assert_eq!(hex("shlxl", &[long(RAX), long(RAX), long(RAX)]), "c4 e2 79 f7 c0");
        assert_eq!(hex("sarxl", &[long(RAX), long(RAX), long(RAX)]), "c4 e2 7a f7 c0");
    }

    /// The six conditions a C expression has no way to ask about, and the move that reads memory.
    #[test]
    fn the_conditions_a_compiler_never_reaches_and_the_move_that_reads_memory() {
        assert_eq!(hex("cmovsq", &[quad(RAX), quad(RBX)]), "48 0f 48 d8");
        assert_eq!(hex("cmovnsq", &[quad(RAX), quad(RBX)]), "48 0f 49 d8");
        assert_eq!(hex("cmovoq", &[quad(RAX), quad(RBX)]), "48 0f 40 d8");
        assert_eq!(hex("cmovnoq", &[quad(RAX), quad(RBX)]), "48 0f 41 d8");
        assert_eq!(hex("cmovpq", &[quad(RAX), quad(RBX)]), "48 0f 4a d8");
        assert_eq!(hex("cmovnpq", &[quad(RAX), quad(RBX)]), "48 0f 4b d8");
        assert_eq!(hex("cmovsl", &[long(RAX), long(RBX)]), "0f 48 d8");
        let at = Addr { base: Some(R8), disp: 16, ..Addr::default() };
        assert_eq!(hex("cmovbq", &[Value::Mem(at), quad(RBX)]), "49 0f 42 58 10");
        let plain = Addr { base: Some(RDI), ..Addr::default() };
        assert_eq!(hex("cmoveq", &[Value::Mem(plain), quad(RAX)]), "48 0f 44 07");
        assert_eq!(hex("cmovnsw", &[Value::Mem(plain), word(RAX)]), "66 0f 49 07");
        let four = Addr { base: Some(RSI), disp: 4, ..Addr::default() };
        assert_eq!(hex("cmovgl", &[Value::Mem(four), long(RDX)]), "0f 4f 56 04");
        assert_eq!(hex("seto", &[byte(RAX)]), "0f 90 c0");
        assert_eq!(hex("setno", &[byte(RAX)]), "0f 91 c0");
        assert_eq!(hex("sets", &[byte(RAX)]), "0f 98 c0");
        assert_eq!(hex("setns", &[byte(RBX)]), "0f 99 c3");
        // The six branches that complete the sixteen, whose four bytes of distance are a hole.
        for (mnemonic, opcode) in
            [("jo", 0x80), ("jno", 0x81), ("js", 0x88), ("jns", 0x89), ("jp", 0x8A), ("jnp", 0x8B)]
        {
            let mut out = Vec::new();
            let holes = encode(mnemonic, &[Value::Dest], &mut out).expect(mnemonic);
            assert_eq!(out, vec![0x0F, opcode, 0, 0, 0, 0], "{mnemonic}");
            assert_eq!(holes.dest, Some(2), "{mnemonic}");
        }
    }

    /// The three instructions that touch nothing but the carry, and the copy that steps two
    /// registers, which is one instruction until a repeat prefix makes it a whole loop.
    #[test]
    fn the_flag_and_the_string_instructions_a_compiler_has_no_use_for() {
        assert_eq!(hex("clc", &[]), "f8");
        assert_eq!(hex("stc", &[]), "f9");
        assert_eq!(hex("cmc", &[]), "f5");
        assert_eq!(hex("movsb", &[]), "a4");
        assert_eq!(hex("movsw", &[]), "66 a5");
        assert_eq!(hex("movsl", &[]), "a5");
        assert_eq!(hex("movsq", &[]), "48 a5");
        // And the prefix that makes the loop, which is one byte with three spellings and a second
        // byte with two, because the condition the name carries is read by the instruction behind
        // it rather than by the prefix.
        assert_eq!(hex("rep", &[]), "f3");
        assert_eq!(hex("repe", &[]), "f3");
        assert_eq!(hex("repz", &[]), "f3");
        assert_eq!(hex("repne", &[]), "f2");
        assert_eq!(hex("repnz", &[]), "f2");
    }

    /// The integer half of the vector unit, which is what a library moving two limbs at a time uses
    /// and what nothing this compiler emits ever reaches.
    ///
    /// Same rule as every group before it: each string came out of `objdump` on an object gas made
    /// from the same line. The one to read carefully is the quadword move, whose load and store are
    /// not a pair of consecutive opcodes the way every other move here is.
    #[test]
    fn the_vector_instructions_that_treat_a_register_as_whole_numbers() {
        let from = Addr { base: Some(RSI), ..Addr::default() };
        let to = Addr { base: Some(RDI), ..Addr::default() };
        // One word each way, which is two opcodes behind two different prefixes.
        assert_eq!(hex("movq", &[Value::Mem(from), Value::Xmm(xmm(1))]), "f3 0f 7e 0e");
        assert_eq!(hex("movq", &[Value::Xmm(xmm(0)), Value::Mem(to)]), "66 0f d6 07");
        // The whole register, aligned and not, which is `movaps` behind a prefix.
        assert_eq!(hex("movdqu", &[Value::Mem(from), Value::Xmm(xmm(0))]), "f3 0f 6f 06");
        assert_eq!(hex("movdqa", &[Value::Xmm(xmm(0)), Value::Mem(to)]), "66 0f 7f 07");
        assert_eq!(hex("movdqa", &[Value::Xmm(xmm(1)), Value::Xmm(xmm(0))]), "66 0f 6f c1");
        assert_eq!(hex("movdqu", &[Value::Xmm(xmm(9)), Value::Xmm(xmm(8))]), "f3 45 0f 6f c1");
        // An address with everything in it, which is where a copying loop actually reads from.
        let along =
            Addr { base: Some(RSI), index: Some(RDX), scale: 8, disp: -16, ..Addr::default() };
        assert_eq!(hex("movdqu", &[Value::Mem(along), Value::Xmm(xmm(7))]), "f3 0f 6f 7c d6 f0");
        // A register compared against itself, which is how a file fills one with ones.
        assert_eq!(hex("pcmpeqb", &[Value::Xmm(xmm(3)), Value::Xmm(xmm(3))]), "66 0f 74 db");
        assert_eq!(hex("pcmpeqd", &[Value::Xmm(xmm(0)), Value::Xmm(xmm(1))]), "66 0f 76 c8");
        // The logicals, and the one of the four whose operands are not interchangeable.
        assert_eq!(hex("pxor", &[Value::Xmm(xmm(7)), Value::Xmm(xmm(0))]), "66 0f ef c7");
        assert_eq!(hex("por", &[Value::Xmm(xmm(1)), Value::Xmm(xmm(0))]), "66 0f eb c1");
        assert_eq!(hex("pand", &[Value::Xmm(xmm(2)), Value::Xmm(xmm(5))]), "66 0f db ea");
        assert_eq!(hex("pandn", &[Value::Xmm(xmm(2)), Value::Xmm(xmm(5))]), "66 0f df ea");
        // The shifts, by a count in a register and by a count written down, which are different
        // opcodes and not one opcode with the count somewhere else.
        assert_eq!(hex("psllq", &[Value::Xmm(xmm(4)), Value::Xmm(xmm(0))]), "66 0f f3 c4");
        assert_eq!(hex("psrlq", &[Value::Xmm(xmm(5)), Value::Xmm(xmm(1))]), "66 0f d3 cd");
        assert_eq!(hex("psrad", &[Value::Xmm(xmm(1)), Value::Xmm(xmm(2))]), "66 0f e2 d1");
        assert_eq!(hex("psllq", &[Value::Imm(3), Value::Xmm(xmm(0))]), "66 0f 73 f0 03");
        assert_eq!(hex("psrlw", &[Value::Imm(1), Value::Xmm(xmm(6))]), "66 0f 71 d6 01");
        assert_eq!(hex("psrldq", &[Value::Imm(8), Value::Xmm(xmm(2))]), "66 0f 73 da 08");
        assert_eq!(hex("pslldq", &[Value::Imm(8), Value::Xmm(xmm(2))]), "66 0f 73 fa 08");
        // Putting two low words together, which is a pair of limbs becoming one vector.
        assert_eq!(hex("punpcklqdq", &[Value::Xmm(xmm(1)), Value::Xmm(xmm(0))]), "66 0f 6c c1");
        assert_eq!(hex("punpckhqdq", &[Value::Xmm(xmm(1)), Value::Xmm(xmm(0))]), "66 0f 6d c1");
        // And adding each piece without carrying between them.
        assert_eq!(hex("paddq", &[Value::Xmm(xmm(1)), Value::Xmm(xmm(0))]), "66 0f d4 c1");
        assert_eq!(hex("psubb", &[Value::Xmm(xmm(1)), Value::Xmm(xmm(0))]), "66 0f f8 c1");
    }

    /// The SSE forms a file gcc wrote needs and this compiler does not write, checked against the
    /// bytes gas writes for the same lines.
    #[test]
    fn the_vector_forms_gcc_writes_read_as_gas_reads_them() {
        let from = Addr { base: Some(RSI), ..Addr::default() };
        let to = Addr { base: Some(RDI), disp: 16, ..Addr::default() };
        let x = |n| Value::Xmm(xmm(n));
        assert_eq!(hex("movups", &[x(0), Value::Mem(to)]), "0f 11 47 10");
        assert_eq!(hex("mulsd", &[Value::Mem(from), x(0)]), "f2 0f 59 06");
        let at = Addr { base: Some(RDI), ..Addr::default() };
        assert_eq!(hex("cvtsi2sdq", &[Value::Mem(at), x(0)]), "f2 48 0f 2a 07");
        assert_eq!(hex("comisd", &[x(1), x(0)]), "66 0f 2f c1");
        assert_eq!(hex("pshufd", &[Value::Imm(78), x(0), x(10)]), "66 44 0f 70 d0 4e");
        // A byte holds the order of the four lanes, so a number no byte holds is refused rather
        // than cut down to its low eight bits.
        let mut out = Vec::new();
        assert!(encode("pshufd", &[Value::Imm(1000), x(1), x(0)], &mut out).is_err());
        assert!(encode("shufps", &[Value::Imm(0x1_2345_6789), x(1), x(0)], &mut out).is_err());
        assert_eq!(hex("pshufd", &[Value::Imm(-1), x(1), x(0)]), "66 0f 70 c1 ff");
        assert_eq!(hex("punpckldq", &[x(1), x(0)]), "66 0f 62 c1");
        assert_eq!(hex("xorpd", &[x(1), x(1)]), "66 0f 57 c9");
        assert_eq!(hex("movhps", &[Value::Mem(from), x(1)]), "0f 16 0e");
        assert_eq!(hex("movd", &[Value::Mem(from), x(0)]), "66 0f 6e 06");
        assert_eq!(hex("sqrtsd", &[x(1), x(0)]), "f2 0f 51 c1");
        assert_eq!(hex("cvttsd2siq", &[Value::Mem(from), quad(RAX)]), "f2 48 0f 2c 06");
    }

    #[test]
    fn the_one_branch_with_nowhere_but_a_byte_to_say_where_it_goes() {
        // `jrcxz` has no long form, so the byte it leaves is the whole of its reach and a caller
        // that assumed four would write over the instruction behind it. The hole says where, and
        // how wide it is is the row's business rather than the caller's.
        let mut out = Vec::new();
        let holes = encode("jrcxz", &[Value::Dest], &mut out).expect("a jump on a register");
        assert_eq!(out, vec![0xE3, 0x00], "the opcode and the room for the distance");
        assert_eq!(holes.dest, Some(1), "the distance goes in the byte behind the opcode");
        let row = encoding("jrcxz", &[Kind::Dest], 0).expect("the row it was encoded from");
        assert_eq!(row.imm, ImmSize::Cb, "the row is what says how much room there is");
    }

    #[test]
    fn a_mnemonic_with_arguments_it_does_not_take_is_refused_rather_than_encoded() {
        let mut out = Vec::new();
        let error = encode("ret", &[quad(RAX)], &mut out).expect_err("a return of a register");
        assert_eq!(error, Error::Unwritten { mnemonic: "ret".to_owned(), args: vec![Kind::Reg] });
        assert_eq!(out, Vec::<u8>::new(), "nothing is written for an instruction that is refused");
        let error = encode("frobnicate", &[], &mut out).expect_err("no such instruction");
        assert!(matches!(error, Error::Unwritten { .. }), "{error}");
        assert_eq!(encoding("addl", &[Kind::Reg], 0), None);
    }

    /// Every length of padding is exactly that many bytes, and it is one instruction up to eleven.
    #[test]
    fn padding_is_as_long_as_asked_and_one_instruction_while_it_can_be() {
        for count in 0..=25 {
            let mut out = Vec::new();
            nops(count, &mut out);
            assert_eq!(out.len(), count, "{count} bytes of padding");
        }
        let mut out = Vec::new();
        nops(10, &mut out);
        assert_eq!(out, [0x66, 0x2e, 0x0f, 0x1f, 0x84, 0, 0, 0, 0, 0], "cs nopw 0(%rax,%rax,1)");
        let mut out = Vec::new();
        nops(3, &mut out);
        assert_eq!(out, [0x0f, 0x1f, 0x00], "nopl (%rax)");
        let mut out = Vec::new();
        nops(11, &mut out);
        assert_eq!(out, [0x66, 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0, 0, 0, 0, 0], "data16 cs nopw");
        // What gas 2.42 writes for thirteen bytes in front of a `ret`.
        let mut out = Vec::new();
        nops(13, &mut out);
        assert_eq!(out[11..], [0x66, 0x90], "eleven bytes and then two");
    }

    /// A vector register named at a length, which is what the AVX-512 rows take.
    fn z(number: u8) -> Value {
        Value::Vector(number, Length::Zmm)
    }

    fn y(number: u8) -> Value {
        Value::Vector(number, Length::Ymm)
    }

    fn x(number: u8) -> Value {
        Value::Vector(number, Length::Xmm)
    }

    /// An address that is a register and a displacement.
    fn at(base: PhysReg, disp: i32) -> Value {
        Value::Mem(Addr { base: Some(base), scale: 1, disp, ..Addr::default() })
    }

    // Every expected string in the tests below is what GNU as writes for the instruction in
    // the message beside it.

    #[test]
    fn an_avx512_instruction_is_the_four_byte_prefix_and_then_what_a_vex_one_would_be() {
        assert_eq!(hex("vmovdqu64", &[at(RDI, 0), z(16)]), "62 e1 fe 48 6f 07");
        assert_eq!(hex("vmovdqu64", &[z(16), at(RAX, 0)]), "62 e1 fe 48 7f 00");
        assert_eq!(hex("vmovdqu64", &[z(16), z(17)]), "62 a1 fe 48 6f c8");
        assert_eq!(hex("vmovdqu64", &[z(0), z(1)]), "62 f1 fe 48 6f c8");
        assert_eq!(hex("vmovdqu64", &[z(8), z(25)]), "62 41 fe 48 6f c8");
        assert_eq!(hex("vmovdqu64", &[at(R12, 0), z(9)]), "62 51 fe 48 6f 0c 24");
        assert_eq!(hex("vmovdqa64", &[z(17), z(18)]), "62 a1 fd 48 6f d1");
        assert_eq!(hex("vmovdqa64", &[x(17), x(18)]), "62 a1 fd 08 6f d1");
        assert_eq!(hex("vmovdqa64", &[Value::Xmm(xmm(1)), x(18)]), "62 e1 fd 08 6f d1");
        assert_eq!(hex("vpaddq", &[z(16), z(17), z(18)]), "62 a1 f5 40 d4 d0");
        assert_eq!(hex("vpaddq", &[z(29), z(30), z(31)]), "62 01 8d 40 d4 fd");
        assert_eq!(hex("vpxorq", &[z(16), z(16), z(16)]), "62 a1 fd 40 ef c0");
        assert_eq!(
            hex("vpternlogq", &[Value::Imm(0x96), z(16), z(17), z(18)]),
            "62 a3 f5 40 25 d0 96"
        );
        assert_eq!(hex("vpopcntq", &[z(1), z(2)]), "62 f2 fd 48 55 d1");
        assert_eq!(
            hex("vpclmulqdq", &[Value::Imm(0x11), z(1), z(2), z(3)]),
            "62 f3 6d 48 44 d9 11"
        );
        assert_eq!(hex("vextracti32x4", &[Value::Imm(1), z(16), x(17)]), "62 a3 7d 48 39 c1 01");
        assert_eq!(hex("vextracti32x4", &[Value::Imm(1), y(16), x(17)]), "62 a3 7d 28 39 c1 01");
        assert_eq!(hex("vextracti64x4", &[Value::Imm(1), z(16), y(17)]), "62 a3 fd 48 3b c1 01");
        assert_eq!(hex("vpbroadcastb", &[long(R10), z(31)]), "62 42 7d 48 7a fa");
        assert_eq!(
            hex("vshufi64x2", &[Value::Imm(0x4e), z(16), z(16), z(17)]),
            "62 a3 fd 40 43 c8 4e"
        );
        assert_eq!(hex("vpshufd", &[Value::Imm(0x4e), x(16), x(17)]), "62 a1 7d 08 70 c8 4e");
        assert_eq!(hex("vmovq", &[x(31), quad(R11)]), "62 41 fd 08 7e fb");
        assert_eq!(hex("vmovq", &[quad(RAX), x(16)]), "62 e1 fd 08 6e c0");
    }

    #[test]
    fn a_one_byte_displacement_under_avx512_is_counted_in_whole_accesses() {
        assert_eq!(hex("vmovdqu64", &[at(RDI, 64), z(17)]), "62 e1 fe 48 6f 4f 01");
        assert_eq!(hex("vmovdqu64", &[at(RSP, -128), z(31)]), "62 61 fe 48 6f 7c 24 fe");
        assert_eq!(hex("vmovdqu64", &[at(RDI, 100), z(16)]), "62 e1 fe 48 6f 87 64 00 00 00");
        assert_eq!(hex("vmovdqu64", &[at(RDI, 0x2000), z(16)]), "62 e1 fe 48 6f 87 00 20 00 00");
        assert_eq!(hex("vmovdqu64", &[at(RAX, 16), x(17)]), "62 e1 fe 08 6f 48 01");
        assert_eq!(hex("vmovdqu64", &[y(16), at(RAX, 32)]), "62 e1 fe 28 7f 40 01");
        assert_eq!(hex("vpaddq", &[at(RAX, 128), z(17), z(18)]), "62 e1 f5 40 d4 50 02");
        let scaled = Value::Mem(Addr {
            base: Some(RSP),
            index: Some(RCX),
            scale: 8,
            disp: 64,
            ..Addr::default()
        });
        assert_eq!(hex("vmovdqu64", &[z(20), scaled]), "62 e1 fe 48 7f 64 cc 01");
        // A sixteen byte lane is counted in sixteen bytes whatever the length.
        assert_eq!(hex("vbroadcasti32x4", &[at(RAX, 32), z(16)]), "62 e2 7d 48 5a 40 02");
        assert_eq!(hex("vbroadcasti32x4", &[at(RAX, 16), y(16)]), "62 e2 7d 28 5a 40 01");
        assert_eq!(
            hex("vextracti32x4", &[Value::Imm(2), z(16), at(RAX, 32)]),
            "62 e3 7d 48 39 40 02 02"
        );
        assert_eq!(
            hex("vpternlogq", &[Value::Imm(0x96), at(RAX, 64), z(17), z(18)]),
            "62 e3 f5 40 25 50 01 96"
        );
    }

    #[test]
    fn an_instruction_with_a_vex_form_is_written_that_way_unless_something_needs_evex() {
        assert_eq!(hex("vpaddq", &[x(1), x(2), x(3)]), "c5 e9 d4 d9");
        assert_eq!(hex("vpaddq", &[y(9), y(10), y(11)]), "c4 41 2d d4 d9");
        assert_eq!(hex("vpaddq", &[at(RAX, 0), y(2), y(3)]), "c5 ed d4 18");
        assert_eq!(hex("vpaddq", &[z(1), z(2), z(3)]), "62 f1 ed 48 d4 d9");
        assert_eq!(hex("vpaddq", &[x(16), x(17), x(18)]), "62 a1 f5 00 d4 d0");
        assert_eq!(hex("vpclmulqdq", &[Value::Imm(0), x(1), x(2), x(3)]), "c4 e3 69 44 d9 00");
        assert_eq!(hex("vpclmulqdq", &[Value::Imm(0), y(1), y(2), y(3)]), "c4 e3 6d 44 d9 00");
        assert_eq!(
            hex("vpclmulqdq", &[Value::Imm(0), x(16), x(17), x(18)]),
            "62 a3 75 00 44 d0 00"
        );
        assert_eq!(hex("vpshufd", &[Value::Imm(0x4e), x(1), x(2)]), "c5 f9 70 d1 4e");
        assert_eq!(hex("vmovq", &[x(1), quad(RAX)]), "c4 e1 f9 7e c8");
        assert_eq!(hex("vmovq", &[quad(RAX), x(1)]), "c4 e1 f9 6e c8");
        // vpternlogq has no VEX form, so it is EVEX at every length.
        assert_eq!(
            hex("vpternlogq", &[Value::Imm(0x96), x(1), x(2), x(3)]),
            "62 f3 ed 08 25 d9 96"
        );
    }

    #[test]
    fn a_mask_and_zeroing_go_in_the_last_byte_of_the_prefix() {
        let masked = |mask: Opmask, values: &[Value]| {
            let mut out = Vec::new();
            encode_masked("vmovdqu8", values, mask, &mut out).expect("vmovdqu8 takes a mask");
            out.iter().map(|byte| format!("{byte:02x}")).collect::<Vec<_>>().join(" ")
        };
        let index =
            Value::Mem(Addr { base: Some(R9), index: Some(R10), scale: 1, ..Addr::default() });
        assert_eq!(masked(Opmask { k: 1, zero: true }, &[at(RBX, 0), z(16)]), "62 e1 7f c9 6f 03");
        assert_eq!(masked(Opmask { k: 7, zero: true }, &[index, z(30)]), "62 01 7f cf 6f 34 11");
        assert_eq!(masked(Opmask { k: 1, zero: false }, &[at(RBX, 0), z(16)]), "62 e1 7f 49 6f 03");
        assert_eq!(masked(Opmask::default(), &[z(16), at(RBX, 0)]), "62 e1 7f 48 7f 03");
        assert_eq!(masked(Opmask { k: 2, zero: false }, &[z(16), at(RBX, 0)]), "62 e1 7f 4a 7f 03");
        let mut out = Vec::new();
        let error =
            encode_masked("addq", &[quad(RAX), quad(RBX)], Opmask { k: 1, zero: false }, &mut out);
        assert!(matches!(error, Err(Error::Mask { .. })), "{error:?}");
    }

    #[test]
    fn a_mask_register_moves_to_and_from_a_general_purpose_one_vex_encoded() {
        assert_eq!(hex("kmovq", &[quad(RAX), Value::Mask(1)]), "c4 e1 fb 92 c8");
        assert_eq!(hex("kmovq", &[quad(R13), Value::Mask(7)]), "c4 c1 fb 92 fd");
        assert_eq!(hex("kmovq", &[Value::Mask(1), quad(RAX)]), "c4 e1 fb 93 c1");
        assert_eq!(hex("kmovq", &[Value::Mask(3), quad(R9)]), "c4 61 fb 93 cb");
    }

    /// A mask cleared by xoring it with itself, which is what `-fzero-call-used-regs=all` writes
    /// for each of the eight in front of a `ret` on a machine with AVX-512. The bytes are the ones
    /// the GNU assembler writes for the same line.
    #[test]
    fn a_mask_register_is_cleared_with_kxorw() {
        let k = Value::Mask;
        assert_eq!(hex("kxorw", &[k(0), k(0), k(0)]), "c5 fc 47 c0");
        assert_eq!(hex("kxorw", &[k(7), k(7), k(7)]), "c5 c4 47 ff");
    }

    /// The upper sixteen vector registers are cleared with the EVEX form of `vxorps` when the
    /// unit has AVX-512VL, and the rest still with the VEX form, the bytes being gas's.
    #[test]
    fn vxorps_reaches_the_upper_sixteen_registers_with_evex() {
        assert_eq!(hex("vxorps", &[x(16), x(16), x(16)]), "62 a1 7c 00 57 c0");
        assert_eq!(hex("vxorps", &[x(31), x(31), x(31)]), "62 01 04 00 57 ff");
        assert_eq!(hex("vxorps", &[x(1), x(1), x(1)]), "c5 f0 57 c9");
        assert_eq!(hex("vpxord", &[z(16), z(16), z(16)]), "62 a1 7d 40 ef c0");
    }

    /// crypto/xor.c xors a block into a `ymm` register with `vxorps`, and the other three
    /// bitwise operations on packed floats come with it.
    #[test]
    fn the_bitwise_operations_on_packed_floats_are_the_bytes_gas_writes() {
        assert_eq!(hex("vxorps", &[at(RAX, 0), y(0), y(0)]), "c5 fc 57 00");
        assert_eq!(hex("vxorps", &[y(1), y(2), y(3)]), "c5 ec 57 d9");
        assert_eq!(hex("vxorps", &[y(9), y(13), y(0)]), "c4 c1 14 57 c1");
        assert_eq!(hex("vxorpd", &[at(RCX, 32), x(4), x(5)]), "c5 d9 57 69 20");
        assert_eq!(hex("vandps", &[y(1), y(2), y(3)]), "c5 ec 54 d9");
        assert_eq!(hex("vandnpd", &[x(11), x(2), x(3)]), "c4 c1 69 55 db");
        assert_eq!(hex("vorps", &[at(R8, 0), y(12), y(2)]), "c4 c1 1c 56 10");
        assert_eq!(hex("vorpd", &[y(1), y(2), y(3)]), "c5 ed 56 d9");
        assert_eq!(hex("vandpd", &[x(1), x(2), x(3)]), "c5 e9 54 d9");
        assert_eq!(hex("vandnps", &[y(1), y(2), y(3)]), "c5 ec 55 d9");
    }

    /// lib/raid6/recov_avx512.c moves whole `zmm` registers with the floating point moves, which
    /// gas writes EVEX encoded only when VEX cannot name the operands.
    #[test]
    fn a_floating_point_move_is_evex_encoded_only_when_vex_cannot_say_it() {
        assert_eq!(hex("vmovapd", &[z(0), z(13)]), "62 71 fd 48 28 e8");
        assert_eq!(hex("vmovapd", &[z(13), z(0)]), "62 d1 fd 48 28 c5");
        assert_eq!(hex("vmovapd", &[at(RAX, 0), z(9)]), "62 71 fd 48 28 08");
        assert_eq!(hex("vmovapd", &[z(9), at(RAX, 64)]), "62 71 fd 48 29 48 01");
        assert_eq!(hex("vmovapd", &[y(17), y(0)]), "62 b1 fd 28 28 c1");
        assert_eq!(hex("vmovapd", &[y(13), y(0)]), "c5 7d 29 e8");
        assert_eq!(hex("vmovaps", &[z(1), z(2)]), "62 f1 7c 48 28 d1");
        assert_eq!(hex("vmovaps", &[y(13), y(0)]), "c5 7c 29 e8");
        assert_eq!(hex("vmovaps", &[at(RCX, 0), x(3)]), "c5 f8 28 19");
        assert_eq!(hex("vmovups", &[z(20), at(RDX, 0)]), "62 e1 7c 48 11 22");
        assert_eq!(hex("vmovupd", &[at(RAX, 128), z(5)]), "62 f1 fd 48 10 68 02");
        assert_eq!(hex("vmovupd", &[x(1), x(2)]), "c5 f9 10 d1");
    }

    /// What lib/raid6 writes to work out its parity: stores that go around the cache, the shift
    /// that spreads a sign across a word, and the compare into a mask and back that doubles every
    /// byte in GF(2^8).
    #[test]
    fn the_stores_and_shifts_raid6_writes_are_the_bytes_gas_writes() {
        let to = Addr { base: Some(R8), disp: 16, ..Addr::default() };
        assert_eq!(hex("movntdq", &[Value::Xmm(xmm(0)), at(RAX, 0)]), "66 0f e7 00");
        assert_eq!(hex("movntdq", &[Value::Xmm(xmm(9)), Value::Mem(to)]), "66 45 0f e7 48 10");
        // VEX for what VEX can name, and EVEX for a whole `zmm` or a register past fifteen.
        assert_eq!(hex("vmovntdq", &[y(0), at(RAX, 0)]), "c5 fd e7 00");
        assert_eq!(hex("vmovntdq", &[y(9), at(R8, 32)]), "c4 41 7d e7 48 20");
        assert_eq!(hex("vmovntdq", &[x(2), at(RCX, 0)]), "c5 f9 e7 11");
        assert_eq!(hex("vmovntdq", &[z(2), at(RAX, 0)]), "62 f1 7d 48 e7 10");
        assert_eq!(hex("vmovntdq", &[z(17), at(RDX, 64)]), "62 e1 7d 48 e7 4a 01");
        assert_eq!(hex("vmovntdq", &[y(20), at(RAX, 32)]), "62 e1 7d 28 e7 60 01");
        assert_eq!(hex("vpsraw", &[Value::Imm(7), y(2), y(3)]), "c5 e5 71 e2 07");
        assert_eq!(hex("vpsraw", &[Value::Imm(1), x(9), x(12)]), "c4 c1 19 71 e1 01");
        assert_eq!(hex("vpsraw", &[Value::Imm(3), z(2), z(3)]), "62 f1 65 48 71 e2 03");
        assert_eq!(hex("vpcmpgtb", &[z(4), z(1), Value::Mask(1)]), "62 f1 75 48 64 cc");
        assert_eq!(hex("vpcmpgtb", &[z(14), z(15), Value::Mask(4)]), "62 d1 05 48 64 e6");
        assert_eq!(hex("vpcmpgtb", &[z(20), z(1), Value::Mask(7)]), "62 b1 75 48 64 fc");
        assert_eq!(hex("vpcmpgtb", &[at(RAX, 64), z(1), Value::Mask(2)]), "62 f1 75 48 64 50 01");
        assert_eq!(hex("vpmovm2b", &[Value::Mask(1), z(5)]), "62 f2 7e 48 28 e9");
        assert_eq!(hex("vpmovm2b", &[Value::Mask(4), z(15)]), "62 72 7e 48 28 fc");
        assert_eq!(hex("vpmovm2b", &[Value::Mask(2), z(21)]), "62 e2 7e 48 28 ea");
        assert_eq!(hex("vpmovm2b", &[Value::Mask(1), y(5)]), "62 f2 7e 28 28 e9");
        assert_eq!(hex("vmovapd", &[y(0), y(13)]), "c5 7d 28 e8");
        assert_eq!(hex("vmovapd", &[y(13), y(0)]), "c5 7d 29 e8");
        assert_eq!(hex("vmovapd", &[at(RAX, 0), y(9)]), "c5 7d 28 08");
        assert_eq!(hex("vmovapd", &[y(9), at(RAX, 32)]), "c5 7d 29 48 20");
    }

    /// A control, debug or segment register goes in the field beside the addressing byte, and a
    /// control or debug register past seven reaches it through `REX.R` the way a general purpose
    /// one does. The bytes are llvm-mc's for the same lines.
    #[test]
    fn a_control_debug_or_segment_register_is_the_register_field_of_the_addressing_byte() {
        let cr = Value::Control;
        let dr = Value::Debug;
        assert_eq!(hex("movq", &[cr(3), quad(R9)]), "41 0f 20 d9");
        assert_eq!(hex("movq", &[quad(RAX), cr(8)]), "44 0f 22 c0");
        assert_eq!(hex("movq", &[dr(7), quad(RAX)]), "0f 21 f8");
        assert_eq!(hex("movq", &[quad(R10), dr(1)]), "41 0f 23 ca");
        let mut out = Vec::new();
        assert!(encode("movq", &[cr(16), quad(RAX)], &mut out).is_err());
        let ds = Value::Seg(Segment::Ds);
        let gs = Value::Seg(Segment::Gs);
        assert_eq!(hex("movl", &[ds, long(RAX)]), "8c d8");
        assert_eq!(hex("movw", &[ds, word(RAX)]), "66 8c d8");
        assert_eq!(hex("movq", &[ds, quad(RAX)]), "48 8c d8");
        assert_eq!(hex("movl", &[gs, long(R8)]), "41 8c e8");
        assert_eq!(hex("movw", &[word(RAX), Value::Seg(Segment::Es)]), "8e c0");
        let at = Value::Mem(Addr { base: Some(RAX), scale: 1, ..Addr::default() });
        assert_eq!(hex("mov", &[at, ds]), "8e 18");
        assert_eq!(hex("mov", &[ds, at]), "8c 18");
        assert_eq!(hex("pushq %fs", &[]), "0f a0");
        assert_eq!(hex("popq %gs", &[]), "0f a9");
    }

    /// Every segment override is the prefix byte the manual gives it, in front of everything else.
    #[test]
    fn every_segment_override_is_its_own_prefix() {
        for (segment, prefix) in [
            (Segment::Es, "26"),
            (Segment::Cs, "2e"),
            (Segment::Ss, "36"),
            (Segment::Ds, "3e"),
            (Segment::Fs, "64"),
            (Segment::Gs, "65"),
        ] {
            let at = Value::Mem(Addr {
                segment: Some(segment),
                base: Some(RAX),
                scale: 1,
                ..Addr::default()
            });
            assert_eq!(hex("movl", &[at, long(RAX)]), format!("{prefix} 8b 00"));
        }
    }

    /// A few of the system instructions with no operand, one with an immediate, and the port I/O
    /// forms, against llvm-mc.
    #[test]
    fn the_system_instructions_are_the_manuals_bytes() {
        assert_eq!(hex("swapgs", &[]), "0f 01 f8");
        assert_eq!(hex("sysretq", &[]), "48 0f 07");
        assert_eq!(hex("iretq", &[]), "48 cf");
        assert_eq!(hex("wrmsrns", &[]), "0f 01 c6");
        assert_eq!(hex("eretu", &[]), "f3 0f 01 ca");
        assert_eq!(hex("tdcall", &[]), "66 0f 01 cc");
        assert_eq!(hex("int", &[Value::Imm(0x80)]), "cd 80");
        assert_eq!(hex("lretq", &[Value::Imm(8)]), "48 ca 08 00");
        let at = Value::Mem(Addr { base: Some(RDI), scale: 1, ..Addr::default() });
        assert_eq!(hex("xsaves64", &[at]), "48 0f c7 2f");
        assert_eq!(hex("wrussq", &[quad(RAX), at]), "66 48 0f 38 f5 07");
        assert_eq!(hex("rdfsbaseq", &[quad(RAX)]), "f3 48 0f ae c0");
        assert_eq!(hex("inw", &[word(RDX), word(RAX)]), "66 ed");
        assert_eq!(hex("outb", &[byte(RAX), Value::Imm(0x80)]), "e6 80");
        assert_eq!(hex("rep insw", &[]), "66 f3 6d");
    }

    #[test]
    fn a_register_past_fifteen_is_refused_by_a_row_that_cannot_name_it() {
        let mut out = Vec::new();
        let error = encode("addss", &[x(16), Value::Xmm(xmm(1))], &mut out);
        assert!(matches!(error, Err(Error::Argument { .. })), "{error:?}");
    }

    /// The bytes of that instruction in thirty two bit mode.
    fn hex32(mnemonic: &str, values: &[Value]) -> String {
        let mut out = Vec::new();
        encode_in(Mode::Bits32, mnemonic, values, &mut out)
            .unwrap_or_else(|error| panic!("{mnemonic} {values:?}: {error}"));
        out.iter().map(|byte| format!("{byte:02x}")).collect::<Vec<_>>().join(" ")
    }

    #[test]
    fn an_i386_instruction_is_the_bytes_an_i386_assembler_writes() {
        // Every expected string is what `as --32` (GNU as 2.42) and `llvm-mc --triple=i386
        // --show-encoding` both write for the line in the comment beside it.
        let mem = |base, index, scale, disp| {
            Value::Mem(Addr { base, index, scale, disp, ..Addr::default() })
        };
        let absolute = mem(None, None, 1, 0x1234);
        let indexed = mem(None, Some(RAX), 4, 0x1234);
        let sum = mem(Some(RBX), Some(RSI), 2, 4);
        let wide = mem(Some(RBX), Some(RCX), 8, 0x40);
        let tls = Value::Mem(Addr { disp: 0x14, segment: Some(Segment::Gs), ..Addr::default() });
        let table: [(&str, Vec<Value>, &str); 44] = [
            ("incl", vec![long(RAX)], "40"),                          // incl %eax
            ("decl", vec![long(RDI)], "4f"),                          // decl %edi
            ("incw", vec![word(RCX)], "66 41"),                       // incw %cx
            ("decw", vec![word(RDX)], "66 4a"),                       // decw %dx
            ("incb", vec![byte(RAX)], "fe c0"),                       // incb %al
            ("incl", vec![at(RAX, 0)], "ff 00"),                      // incl (%eax)
            ("decl", vec![at(RSI, 4)], "ff 4e 04"),                   // decl 4(%esi)
            ("pushl", vec![long(RBP)], "55"),                         // pushl %ebp
            ("popl", vec![long(RBP)], "5d"),                          // popl %ebp
            ("pushl", vec![long(RDI)], "57"),                         // pushl %edi
            ("pushl", vec![Value::Imm(1)], "6a 01"),                  // pushl $1
            ("pushl", vec![Value::Imm(0x12345)], "68 45 23 01 00"),   // pushl $0x12345
            ("pushl", vec![at(RBP, 8)], "ff 75 08"),                  // pushl 8(%ebp)
            ("popl", vec![at(RAX, 0)], "8f 00"),                      // popl (%eax)
            ("pushfl", vec![], "9c"),                                 // pushfl
            ("popfl", vec![], "9d"),                                  // popfl
            ("movl", vec![long(RSP), long(RBP)], "89 e5"),            // movl %esp, %ebp
            ("movl", vec![at(RBP, 8), long(RAX)], "8b 45 08"),        // movl 8(%ebp), %eax
            ("movl", vec![absolute, long(RCX)], "8b 0d 34 12 00 00"), // movl 0x1234, %ecx
            ("movl", vec![long(RDX), indexed], "89 14 85 34 12 00 00"), // movl %edx, 0x1234(,%eax,4)
            ("movl", vec![at(RSP, 0), long(RAX)], "8b 04 24"),          // movl (%esp), %eax
            ("movl", vec![long(RBX), at(RBP, -4)], "89 5d fc"),         // movl %ebx, -4(%ebp)
            ("leal", vec![sum, long(RDI)], "8d 7c 73 04"),              // leal 4(%ebx,%esi,2), %edi
            ("addl", vec![Value::Imm(1000), long(RBX)], "81 c3 e8 03 00 00"), // addl $1000, %ebx
            ("subl", vec![Value::Imm(16), long(RSP)], "83 ec 10"),      // subl $16, %esp
            ("movb", vec![Value::High(RAX), byte(RBX)], "88 e3"),       // movb %ah, %bl
            ("movb", vec![byte(RDX), Value::High(RBX)], "88 d7"),       // movb %dl, %bh
            ("movzbl", vec![byte(RBX), long(RAX)], "0f b6 c3"),         // movzbl %bl, %eax
            ("movl", vec![tls, long(RCX)], "65 8b 0d 14 00 00 00"),     // movl %gs:0x14, %ecx
            ("movsd", vec![at(RSP, 8), Value::Xmm(xmm(7))], "f2 0f 10 7c 24 08"), // movsd 8(%esp), %xmm7
            ("addsd", vec![Value::Xmm(xmm(1)), Value::Xmm(xmm(0))], "f2 0f 58 c1"), // addsd %xmm1, %xmm0
            ("cvtsi2sdl", vec![long(RAX), Value::Xmm(xmm(0))], "f2 0f 2a c0"), // cvtsi2sdl %eax, %xmm0
            ("call", vec![long(RAX)], "ff d0"),                                // call *%eax
            ("call", vec![at(RBX, 4)], "ff 53 04"),                            // call *4(%ebx)
            ("ret", vec![], "c3"),                                             // ret
            ("leave", vec![], "c9"),                                           // leave
            ("cltd", vec![], "99"),                                            // cltd
            ("bswapl", vec![long(RCX)], "0f c9"),                              // bswapl %ecx
            ("fldl", vec![at(RSP, 8)], "dd 44 24 08"),                         // fldl 8(%esp)
            ("imull", vec![Value::Imm(3), long(RCX), long(RDX)], "6b d1 03"), // imull $3, %ecx, %edx
            ("shldl", vec![Value::Imm(5), long(RSI), long(RDI)], "0f a4 f7 05"), // shldl $5, %esi, %edi
            ("xorl", vec![long(RAX), long(RAX)], "31 c0"),                       // xorl %eax, %eax
            ("cmpl", vec![Value::Imm(1), at(RBP, 0)], "83 7d 00 01"),            // cmpl $1, (%ebp)
            ("movl", vec![Value::Imm(0x1234_5678), wide], "c7 44 cb 40 78 56 34 12"), // movl $0x12345678, 0x40(%ebx,%ecx,8)
        ];
        for (mnemonic, values, bytes) in table {
            assert_eq!(hex32(mnemonic, &values), bytes, "{mnemonic} {values:?}");
        }
    }

    #[test]
    fn an_i386_absolute_address_the_linker_fills_in_leaves_its_four_bytes_open() {
        let mut out = Vec::new();
        let named = Addr { linked: true, ..Addr::default() };
        let holes = encode_in(Mode::Bits32, "movl", &[Value::Mem(named), long(RCX)], &mut out)
            .expect("an absolute load");
        assert_eq!(out, [0x8b, 0x0d, 0, 0, 0, 0]);
        assert_eq!(holes, Holes { disp: Some(2), ..Holes::default() });
    }

    #[test]
    fn what_i386_has_no_way_to_write_is_refused_rather_than_written_as_something_else() {
        let refused = |mnemonic: &str, values: &[Value]| {
            let mut out = Vec::new();
            let error = encode_in(Mode::Bits32, mnemonic, values, &mut out)
                .expect_err("an instruction i386 cannot write");
            assert!(out.is_empty(), "{mnemonic} wrote {out:02x?} before it was refused");
            error
        };
        let register =
            |mnemonic: &str, number| Error::Register { mnemonic: mnemonic.into(), number };
        let wide = |mnemonic: &str| Error::Wide { mnemonic: mnemonic.into() };
        assert_eq!(refused("addl", &[long(R8), long(RAX)]), register("addl", 8));
        assert_eq!(refused("addl", &[long(RAX), long(R15)]), register("addl", 15));
        assert_eq!(refused("movb", &[byte(RSI), byte(RAX)]), register("movb", 6));
        assert_eq!(refused("movl", &[at(R9, 0), long(RAX)]), register("movl", 9));
        let index =
            Value::Mem(Addr { base: Some(RAX), index: Some(R10), scale: 1, ..Addr::default() });
        assert_eq!(refused("movl", &[index, long(RAX)]), register("movl", 10));
        let sse = [Value::Xmm(xmm(8)), Value::Xmm(xmm(0))];
        assert_eq!(refused("addsd", &sse), register("addsd", 8));
        assert_eq!(refused("addq", &[quad(RAX), quad(RBX)]), wide("addq"));
        assert_eq!(refused("cltq", &[]), wide("cltq"));
        assert_eq!(refused("movabsq", &[Value::Imm(1 << 40), quad(RAX)]), wide("movabsq"));
        assert_eq!(refused("pushq", &[quad(RBP)]), wide("pushq"));
        assert_eq!(refused("popfq", &[]), wide("popfq"));
        let rip = Value::Mem(Addr { rip: true, ..Addr::default() });
        assert_eq!(refused("movl", &[rip, long(RAX)]), Error::Relative { mnemonic: "movl".into() });
    }

    #[test]
    fn a_sixty_four_bit_instruction_is_the_same_bytes_it_was_before_there_were_two_modes() {
        // The rows only i386 has are never looked at in sixty four bit mode, so `incl %eax` and
        // `pushq %rbp` are still what they were, and `pushl` is still nothing at all.
        assert_eq!(hex("incl", &[long(RAX)]), "ff c0");
        assert_eq!(hex("decw", &[word(RDX)]), "66 ff ca");
        assert_eq!(hex("pushq", &[quad(RBP)]), "55");
        let absolute = Value::Mem(Addr { disp: 0x1234, ..Addr::default() });
        assert_eq!(hex("movl", &[absolute, long(RCX)]), "8b 0c 25 34 12 00 00");
        let mut out = Vec::new();
        let error = encode("pushl", &[long(RBP)], &mut out);
        assert!(matches!(error, Err(Error::Unwritten { .. })), "{error:?}");
    }

    #[test]
    fn a_shared_row_naming_only_what_i386_has_is_the_same_bytes_in_both_modes() {
        // Every row of the shared table, given arguments both modes can name, comes out the same
        // unless thirty two bit mode chose a row of its own for it or refused it outright.
        let value = |kind: Kind| match kind {
            Kind::Reg => long(RCX),
            Kind::Vec => Value::Xmm(xmm(2)),
            Kind::Mem => at(RBX, 8),
            Kind::Imm => Value::Imm(1),
            Kind::Dest => Value::Dest,
            Kind::Mask => Value::Mask(1),
            Kind::Stack => Value::Stack,
            Kind::Control => Value::Control(0),
            Kind::Debug => Value::Debug(0),
            Kind::Seg => Value::Seg(Segment::Es),
        };
        let mut compared = 0;
        for row in ENCODINGS {
            let values: Vec<Value> = row.args.iter().map(|&kind| value(kind)).collect();
            let chosen = encoding_in(Mode::Bits32, row.mnemonic, row.args, 1);
            if !chosen.is_some_and(|chosen| {
                std::ptr::eq(chosen, encoding(row.mnemonic, row.args, 1).unwrap())
            }) {
                continue;
            }
            let (mut long_mode, mut legacy) = (Vec::new(), Vec::new());
            let Ok(holes) = encode_in(Mode::Bits32, row.mnemonic, &values, &mut legacy) else {
                continue;
            };
            let same = encode(row.mnemonic, &values, &mut long_mode).expect("both modes encode it");
            assert_eq!(legacy, long_mode, "{} {:?}", row.mnemonic, row.args);
            assert_eq!(holes, same);
            compared += 1;
        }
        assert!(compared > 500, "only {compared} rows compared");
    }

    #[test]
    fn a_byte_from_0x40_to_0x4f_is_a_prefix_in_one_mode_and_an_instruction_in_the_other() {
        assert_eq!(Mode::Bits64.rex(0x48), Some(0x8));
        assert_eq!(Mode::Bits64.rex(0x41), Some(0x1));
        assert_eq!(Mode::Bits64.rex(0x8b), None);
        assert_eq!(Mode::Bits32.rex(0x48), None);
        assert_eq!(Mode::Bits32.counted(0x40), Some(("incl", RAX)));
        assert_eq!(Mode::Bits32.counted(0x47), Some(("incl", RDI)));
        assert_eq!(Mode::Bits32.counted(0x48), Some(("decl", RAX)));
        assert_eq!(Mode::Bits32.counted(0x4f), Some(("decl", RDI)));
        assert_eq!(Mode::Bits32.counted(0x50), None);
        assert_eq!(Mode::Bits64.counted(0x40), None);
        // And what the encoder writes for those two reads back as them.
        for (mnemonic, reg) in [("incl", RBX), ("decl", RSI)] {
            let mut out = Vec::new();
            encode_in(Mode::Bits32, mnemonic, &[long(reg)], &mut out).expect("a one byte form");
            assert_eq!(Mode::Bits32.counted(out[0]), Some((mnemonic, reg)));
        }
    }
}