rticx-riscv 0.2.0

RTICX distribution for single-core RISC-V targets (generic SLIC, ESP32-C3, ESP32-C6)
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// SLIC-based RISC-V distribution: rely on the `riscv-slic` crate for the
// runtime. The upstream exports re-export the SLIC primitives verbatim,
// and define a small `interrupt` shim mirroring the cortex-m layout.
//
// Upstream: `upstream/exports/slic.rs`.
pub use riscv_slic::{self, InterruptNumber, codegen, lock, pend, run, set_priority};

pub mod interrupt {
    #[inline]
    pub fn disable() {
        riscv_slic::disable();
    }

    /// # Safety
    ///
    /// Caller must ensure the SLIC interrupt controller is initialized.
    #[inline]
    pub unsafe fn enable() {
        unsafe { riscv_slic::enable() };
    }
}