rssn-advanced 0.1.0

This is rssn-advanced: The next generation symbolic core of rssn.
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116

//! `add_f64x2` — 2-lane packed `f64` addition.
//!
//! * `x86_64`: SSE2 `addpd xmm` (128-bit, 2 lanes; SSE2 is `x86_64` ABI baseline).
//! * `AArch64`: NEON `fadd v.2d` (NEON is mandatory on ARMv8-A).
//! * riscv64 + RVV: `vfadd.vv` with `vsetvli vl=2, e64`.
//! * fallback: scalar loop.

#![allow(unsafe_code)]

/// Adds two 2-lane `f64` arrays element-wise, writing the result to `out`.
#[allow(clippy::inline_always)]
#[inline(always)]
pub fn apply(lhs: &[f64; 2], rhs: &[f64; 2], out: &mut [f64; 2]) {
    #[cfg(target_arch = "x86_64")]
    {
        // SSE2 is part of the x86_64 ABI baseline — no runtime detection needed.
        unsafe {
            use core::arch::asm;
            asm!(
                "movupd xmm0, xmmword ptr [{lhs}]",
                "movupd xmm1, xmmword ptr [{rhs}]",
                "addpd  xmm0, xmm1",
                "movupd xmmword ptr [{out}], xmm0",
                lhs = in(reg) lhs.as_ptr(),
                rhs = in(reg) rhs.as_ptr(),
                out = in(reg) out.as_mut_ptr(),
                out("xmm0") _,
                out("xmm1") _,
                options(nostack, preserves_flags),
            );
        }
        return;
    }

    #[cfg(target_arch = "aarch64")]
    {
        // NEON is mandatory on ARMv8-A — no runtime detection needed.
        unsafe {
            use core::arch::asm;
            asm!(
                "ld1 {{v0.2d}}, [{lhs}]",
                "ld1 {{v1.2d}}, [{rhs}]",
                "fadd v0.2d, v0.2d, v1.2d",
                "st1 {{v0.2d}}, [{out}]",
                lhs = in(reg) lhs.as_ptr(),
                rhs = in(reg) rhs.as_ptr(),
                out = in(reg) out.as_mut_ptr(),
                out("v0") _,
                out("v1") _,
                options(nostack, preserves_flags),
            );
        }
        return;
    }

    #[cfg(all(target_arch = "riscv64", target_feature = "v"))]
    {
        // RVV 1.0 with vl=2, e64.
        unsafe {
            use core::arch::asm;
            asm!(
                "li t0, 2",
                "vsetvli t0, t0, e64, m1, ta, ma",
                "vle64.v v0, ({lhs})",
                "vle64.v v1, ({rhs})",
                "vfadd.vv v0, v0, v1",
                "vse64.v v0, ({out})",
                lhs = in(reg) lhs.as_ptr(),
                rhs = in(reg) rhs.as_ptr(),
                out = in(reg) out.as_mut_ptr(),
                out("t0") _,
                out("v0") _,
                out("v1") _,
                options(nostack),
            );
        }
        return;
    }

    // Scalar fallback.
    out[0] = lhs[0] + rhs[0];
    out[1] = lhs[1] + rhs[1];
}

/// AArch64 NEON intrinsic helper — retained for backward compatibility.
#[cfg(target_arch = "aarch64")]
#[target_feature(enable = "neon")]
pub unsafe fn apply_neon(lhs: &[f64; 2], rhs: &[f64; 2], out: &mut [f64; 2]) {
    use std::arch::aarch64::*;
    let a = vld1q_f64(lhs.as_ptr());
    let b = vld1q_f64(rhs.as_ptr());
    vst1q_f64(out.as_mut_ptr(), vaddq_f64(a, b));
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn add_matches_scalar() {
        let a = [1.0_f64, 2.0];
        let b = [10.0_f64, 20.0];
        let mut out = [0.0_f64; 2];
        apply(&a, &b, &mut out);
        assert_eq!(out, [11.0, 22.0]);
    }

    #[test]
    fn add_negative() {
        let a = [-3.0_f64, 4.0];
        let b = [3.0_f64, -4.0];
        let mut out = [0.0_f64; 2];
        apply(&a, &b, &mut out);
        assert_eq!(out, [0.0, 0.0]);
    }
}