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//! CPU cores.
//!
//! One Cargo feature per core (`ROADMAP.md` §3), so a NES build links a 6502
//! and nothing else. Cores are `no_std + alloc` and reach guest memory only
//! through [`AddressSpace`](crate::core::space::AddressSpace) — cycle
//! accounting is therefore per bus access rather than a post-hoc table of
//! instruction lengths (`ROADMAP.md` §6, CLAUDE.md "CPU cores").
//!
//! | Core | Feature | State |
//! | --- | --- | --- |
//! | `mos6502` | `cpu-mos6502` | cycle-accurate interpreter, illegal opcodes, disassembler |
//! | `z80` | `cpu-z80` | cycle-accurate interpreter, every prefix page, MEMPTR, separate I/O space |
//! | `x86` | `cpu-x86` | Intel 8086/8088 real mode and 80386/80486 protected mode with paging, hardware-checked against `SingleStepTests/8088` |
//! | `riscv` | `cpu-riscv` | RV64GC/RV32 interpreter, privileged modes, Sv39, software IEEE-754 |
//! | `m68k` | `cpu-m68k` | MC68000 interpreter with a modelled prefetch queue, exceptions, disassembler |
//!
//! Every core ships an interpreter first; the IR frontend comes later and is
//! differentially tested against it forever. **The interpreter is the oracle.**
// The family module always compiles and links nothing; the cores underneath
// it are individually gated.