rp2040/
pll_sys.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - Control and Status\\n GENERAL CONSTRAINTS:\\n Reference clock frequency min=5MHz, max=800MHz\\n Feedback divider min=16, max=320\\n VCO frequency min=400MHz, max=1600MHz"]
5    pub cs: CS,
6    #[doc = "0x04 - Controls the PLL power modes."]
7    pub pwr: PWR,
8    #[doc = "0x08 - Feedback divisor\\n (note: this PLL does not support fractional division)"]
9    pub fbdiv_int: FBDIV_INT,
10    #[doc = "0x0c - Controls the PLL post dividers for the primary output\\n (note: this PLL does not have a secondary output)\\n the primary output is driven from VCO divided by postdiv1*postdiv2"]
11    pub prim: PRIM,
12}
13#[doc = "Control and Status\\n GENERAL CONSTRAINTS:\\n Reference clock frequency min=5MHz, max=800MHz\\n Feedback divider min=16, max=320\\n VCO frequency min=400MHz, max=1600MHz\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](cs) module"]
14pub type CS = crate::Reg<u32, _CS>;
15#[allow(missing_docs)]
16#[doc(hidden)]
17pub struct _CS;
18#[doc = "`read()` method returns [cs::R](cs::R) reader structure"]
19impl crate::Readable for CS {}
20#[doc = "`write(|w| ..)` method takes [cs::W](cs::W) writer structure"]
21impl crate::Writable for CS {}
22#[doc = "Control and Status\\n GENERAL CONSTRAINTS:\\n Reference clock frequency min=5MHz, max=800MHz\\n Feedback divider min=16, max=320\\n VCO frequency min=400MHz, max=1600MHz"]
23pub mod cs;
24#[doc = "Controls the PLL power modes.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwr](pwr) module"]
25pub type PWR = crate::Reg<u32, _PWR>;
26#[allow(missing_docs)]
27#[doc(hidden)]
28pub struct _PWR;
29#[doc = "`read()` method returns [pwr::R](pwr::R) reader structure"]
30impl crate::Readable for PWR {}
31#[doc = "`write(|w| ..)` method takes [pwr::W](pwr::W) writer structure"]
32impl crate::Writable for PWR {}
33#[doc = "Controls the PLL power modes."]
34pub mod pwr;
35#[doc = "Feedback divisor\\n (note: this PLL does not support fractional division)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fbdiv_int](fbdiv_int) module"]
36pub type FBDIV_INT = crate::Reg<u32, _FBDIV_INT>;
37#[allow(missing_docs)]
38#[doc(hidden)]
39pub struct _FBDIV_INT;
40#[doc = "`read()` method returns [fbdiv_int::R](fbdiv_int::R) reader structure"]
41impl crate::Readable for FBDIV_INT {}
42#[doc = "`write(|w| ..)` method takes [fbdiv_int::W](fbdiv_int::W) writer structure"]
43impl crate::Writable for FBDIV_INT {}
44#[doc = "Feedback divisor\\n (note: this PLL does not support fractional division)"]
45pub mod fbdiv_int;
46#[doc = "Controls the PLL post dividers for the primary output\\n (note: this PLL does not have a secondary output)\\n the primary output is driven from VCO divided by postdiv1*postdiv2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prim](prim) module"]
47pub type PRIM = crate::Reg<u32, _PRIM>;
48#[allow(missing_docs)]
49#[doc(hidden)]
50pub struct _PRIM;
51#[doc = "`read()` method returns [prim::R](prim::R) reader structure"]
52impl crate::Readable for PRIM {}
53#[doc = "`write(|w| ..)` method takes [prim::W](prim::W) writer structure"]
54impl crate::Writable for PRIM {}
55#[doc = "Controls the PLL post dividers for the primary output\\n (note: this PLL does not have a secondary output)\\n the primary output is driven from VCO divided by postdiv1*postdiv2"]
56pub mod prim;
rp2040/pll_sys.rs

rp2040/
pll_sys.rs
