rlx-fpga

FPGA backend for RLX — per-graph datapath synthesis. Takes an rlx-ir graph (or a Model) and emits target-agnostic SystemVerilog plus weight .mem files, with optional Yosys/nextpnr scripts for a concrete part.

Like rlx-cortexm, this crate sits one layer below the runtime Backend trait. The entry points are export_graph / rlx_runtime::export (feature fpga), not Session::compile.

See docs/fpga-export.md for the full export configuration and HwTarget matrix.

Quick start

cargo test  -p rlx-fpga --release
cargo run   -p rlx-fpga --release --bin rlx-fpga-emit -- --hw generic
cargo run   -p rlx-fpga --release --example export_mnist
just fpga-emit
just fpga-mnist-demo

Checked-in demo: examples/mnist_sv/ (top.sv + layers + weights).

use rlx::prelude::*; // feature = "fpga"

ExportSession::fpga("hw/out")
    .hw_target(HwTarget::Generic)
    .sideband(SidebandSpec::input("temp", 8))
    .sideband(SidebandSpec::input("batch_id", 16))
    .export_model(&tinyconv_mnist_from_cortexm())?;

use rlx_fpga::{export_graph, FpgaExportConfig, HwTarget};
// ... build or load an INT8 Graph ...
export_graph(&graph, &FpgaExportConfig::default(), "hw/out")?;

Hardware targets

What's here

• export / export_config — Graph → Model → emit with tune + HwTarget
• from_graph — Model::from_graph / FromGraphOptions
• quant — integer-only Q0.31 / Q0.15 requantize
• verilog — pure-Rust SystemVerilog writer
• codegen — per-op emitters + emit_with_config
• reference — Rust forward pass (parity vs Verilog)
• bin/rlx-fpga-emit — CLI

License

GPL-3.0-only.