/* Generated by rlvgl-creator from chipdb/rlvgl-chips-ti/db/chips/{{ chip_stem }}.yaml.
*
* Linker supplement for {{ ir.chip.name }} ({{ ir.chip.arch }}). Adds the
* SimpleLink-family CCFG (Customer Configuration) section to the link
* picture and provides any other chip-specific section directives beyond
* the cortex-m-rt default.
*
* CCFG authority: TI SWCU185 §11.1 "Customer Configuration Area (CCFG)".
* The CCFG block is a fixed-address structure consumed by the SimpleLink
* boot ROM at chip reset. Origin / length are sourced from the chip
* yaml's `linker.ccfg_origin` / `linker.ccfg_length` fields.
*
* Consumed via the example crate's build.rs as `-T{{ chip_stem }}.x`,
* sequenced after `-Tmemory.x` and before `-Tlink.x` so FLASH is defined
* when this file is parsed.
*/
{% if ir.chip.linker.ccfg_origin is defined and ir.chip.linker.ccfg_length is defined %}
/* Fixed-address CCFG region carved out of the last sector of Flash. The
* boot ROM reads this on every reset; if it is absent or malformed the
* chip will not run user code. The consuming crate must define a
* `#[link_section = ".ccfg"]` static covering the full {{ ir.chip.linker.ccfg_length }}
* bytes — see TI SWCU185 §11.1 Table 11-1 for the field layout. */
SECTIONS
{
.ccfg ORIGIN({{ ir.chip.linker.region_text|upper }}) + LENGTH({{ ir.chip.linker.region_text|upper }}) - {{ ir.chip.linker.ccfg_length|hex32 }} :
{
KEEP(*(.ccfg))
. = ALIGN(4);
} > {{ ir.chip.linker.region_text|upper }}
} INSERT BEFORE .text;
{% else %}
/* No CCFG region declared in chip IR (`linker.ccfg_origin` /
* `linker.ccfg_length` absent). Either this chip does not require a
* customer-configuration block, or the chipdb yaml is incomplete. */
{% endif %}