rlvgl 0.2.4

A modular, idiomatic Rust reimplementation of the LVGL graphics library for embedded and simulator use.
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{#
  Minimal template used by BSP tests.
  Emits a flat summary of clocks, pins and peripherals.
#}
/* Auto-generated by rlvgl-creator
 * SPDX-FileCopyrightText: 2020 STMicroelectronics
 * SPDX-FileCopyrightText: 2025 Softoboros Technology, Inc.
 * SPDX-License-Identifier: BSD-3-Clause
 * Provenance: STM32_open_pin_data (commit <hash>), build <build-hash>.
*/
{% if meta is defined %}
board {{ meta.vendor }} {{ meta.board }} {{ meta.chip }}
{% endif %}
{%- for name, pll in spec.clocks.pll | dictsort %}
pll {{ name }} m{{ pll.m }} n{{ pll.n }} p{{ pll.p }} q{{ pll.q }} r{{ pll.r }}
{%- endfor %}
{%- for name, src in spec.clocks.kernels | dictsort %}
kernel {{ name }} {{ src }}
{%- endfor %}
{%- for pin in spec.pinctrl %}
pin {{ pin.pin }} {{ pin.func }} af{{ pin.af }}
{%- endfor %}
{%- for name, periph in spec.peripherals | dictsort %}
peripheral {{ name }} {{ periph.class }}
{%- if periph.class == "serial" %}
  ctor Serial::usart{{ name | replace("usart", "") }}
{%- elif periph.class == "spi" %}
  ctor Spi::spi{{ name | replace("spi", "") }}
{%- elif periph.class == "i2c" %}
  ctor I2c::i2c{{ name | replace("i2c", "") }}
{%- endif %}
{%- for role, pin in periph.signals | dictsort %}
  {{ role }}={{ pin }}
{%- endfor %}
{%- endfor %}