rlvgl 0.2.4

A modular, idiomatic Rust reimplementation of the LVGL graphics library for embedded and simulator use.
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/* Generated by rlvgl-creator from chipdb/rlvgl-chips-silabs/db/chips/{{ chip_stem }}.yaml.
 *
 * MEMORY block for {{ ir.chip.name }} ({{ ir.chip.arch }}). Each region
 * comes from the chip yaml's `memory:` array; sizes are sourced from the
 * EFM32GG11B Family Reference Manual ("Memory System Overview / Memory
 * Map") and the EFM32GG11B820 data sheet Table 2.1.
 *
 * The REGION_ALIAS lines map the chip's regions onto the names that
 * cortex-m-rt's `link.x` consumes (FLASH / RAM are the canonical names;
 * the REGION_TEXT / REGION_DATA / REGION_RODATA aliases are accepted by
 * recent cortex-m-rt link scripts and are harmless on older versions).
 * The alias targets come from the chip yaml's `linker:` section.
 *
 * Frozen by CHIPS-SILABS-05 ยง5.2: FLASH origin/length and SRAM
 * origin/length for the EFM32GG11B820 SKU are Standards-Action values.
 */

MEMORY
{
{%- for r in ir.chip.memory %}
  {{ r.name|upper }} : ORIGIN = {{ r.base|hex32 }}, LENGTH = {{ r.size|hex32 }}    /* {{ r.access }} */
{%- endfor %}
}

/* Canonical cortex-m-rt names. */
REGION_ALIAS("FLASH", {{ ir.chip.linker.region_text|upper }});
REGION_ALIAS("RAM",   {{ ir.chip.linker.region_data|upper }});

/* Optional aliases consumed by newer link.x scripts; harmless if unused. */
REGION_ALIAS("REGION_TEXT",   {{ ir.chip.linker.region_text|upper }});
REGION_ALIAS("REGION_RODATA", {{ ir.chip.linker.region_text|upper }});
REGION_ALIAS("REGION_DATA",   {{ ir.chip.linker.region_data|upper }});
REGION_ALIAS("REGION_BSS",    {{ ir.chip.linker.region_data|upper }});
REGION_ALIAS("REGION_HEAP",   {{ ir.chip.linker.region_data|upper }});
REGION_ALIAS("REGION_STACK",  {{ ir.chip.linker.region_data|upper }});