/* Generated by rlvgl-creator from
* chipdb/rlvgl-chips-microchip/db/chips/{{ ir.chip.name }}.yaml.
*
* MEMORY block for {{ ir.chip.name }} ({{ ir.chip.arch }}). Each region
* comes from the chip yaml's `memory:` array and is sized by
* {{ ir.chip.source.datasheet }} rev {{ ir.chip.source.revision }}.
*
* `cortex-m-rt`'s `link.x.in` consumes regions named `FLASH` and `RAM`;
* the chip yaml's `linker:` section names which `memory:` entries back
* those names. Additional regions (e.g. `BKUPRAM`) are emitted alongside
* for application code that wants them.
*/
MEMORY
{
{%- for r in ir.chip.memory %}
{{ r.name|upper }} : ORIGIN = {{ r.base|hex32 }}, LENGTH = {{ r.size|hex32 }} /* {{ r.access }} */
{%- endfor %}
}
/* Aliases consumed by cortex-m-rt's link.x. */
REGION_ALIAS("FLASH", {{ ir.chip.linker.region_text|upper }});
REGION_ALIAS("RAM", {{ ir.chip.linker.region_data|upper }});