/* Generated by rlvgl-creator from chipdb/rlvgl-chips-esp/db/chips/{{ chip_stem }}.yaml.
*
* Linker supplement for {{ ir.chip.name }} ({{ ir.chip.arch }}). Defines
* the symbols esp-riscv-rt expects the chip's HAL to provide so that bare
* raw-PAC examples can link without pulling esp-hal as a dependency.
*
* Required by:
* - esp-riscv-rt 0.13's _dispatch_exception (calls _start_trap_rust_hal)
* - esp-riscv-rt 0.13's _pre_default_start_trap (reads _dram_data_start
* for stack-overflow detection)
*
* Consumed via the example crate's build.rs as `-T{{ chip_stem }}.x`,
* sequenced after `-Tmemory.x` and before `-Tlink.x` so REGION_DATA is
* defined when this file is parsed.
*/
/* Start of writable RAM region — used as the stack-overflow threshold
* inside esp-riscv-rt's pre-default trap handler. */
PROVIDE(_dram_data_start = ORIGIN(REGION_DATA));
/* Default Rust-side trap handler. esp-riscv-rt's _dispatch_exception
* calls this on every unhandled exception. Real HALs override; the
* default here aborts so the panic handler runs. */
PROVIDE(_start_trap_rust_hal = abort);
/* Default vectored-interrupt dispatcher. esp-riscv-rt's per-interrupt
* trampolines (`Trap1..Trap31`) load the IRQ number into `a0` and
* `j handle_interrupts`. Real HALs replace this with a CLINT/PLIC
* dispatch routine; the default aborts. */
PROVIDE(handle_interrupts = abort);