1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
//! Device emulation operations for VPlicGlobal.
//!
//! Implements the `BaseDeviceOps` trait for MMIO read/write handling.
use axaddrspace::{GuestPhysAddrRange, HostPhysAddr, device::AccessWidth};
use axdevice_base::{BaseDeviceOps, EmuDeviceType};
use crate::{consts::*, utils::*, vplic::VPlicGlobal};
/// Implementation of device emulation operations for virtual PLIC.
impl BaseDeviceOps<GuestPhysAddrRange> for VPlicGlobal {
fn emu_type(&self) -> axdevice_base::EmuDeviceType {
EmuDeviceType::PPPTGlobal
}
fn address_range(&self) -> GuestPhysAddrRange {
GuestPhysAddrRange::from_start_size(self.addr, self.size)
}
/// Handles MMIO read operations from the virtual PLIC.
///
/// Only 32-bit (Dword) accesses are supported.
/// Read operations are forwarded to the host PLIC for most registers,
/// except for pending and claim/complete registers which are emulated.
fn handle_read(
&self,
addr: <GuestPhysAddrRange as axaddrspace::device::DeviceAddrRange>::Addr,
width: axaddrspace::device::AccessWidth,
) -> ax_errno::AxResult<usize> {
assert_eq!(width, AccessWidth::Dword);
let reg = addr - self.addr;
let host_addr = HostPhysAddr::from_usize(reg + self.host_plic_addr.as_usize());
// info!("vPlicGlobal read reg {reg:#x} width {width:?}");
match reg {
// priority
PLIC_PRIORITY_OFFSET..PLIC_PENDING_OFFSET => perform_mmio_read(host_addr, width),
// pending
PLIC_PENDING_OFFSET..PLIC_ENABLE_OFFSET => {
let reg_index = reg - PLIC_PENDING_OFFSET / 4;
let bit_index_start = reg_index * 32;
let mut val: u32 = 0;
let mut bit_mask: u32 = 1;
let pending_irqs = self.pending_irqs.lock();
for i in 0..32 {
if pending_irqs.get(bit_index_start + i as usize) {
val |= bit_mask;
}
bit_mask <<= 1;
}
Ok(val as usize)
}
// enable
PLIC_ENABLE_OFFSET..PLIC_CONTEXT_CTRL_OFFSET => perform_mmio_read(host_addr, width),
// threshold
offset
if offset >= PLIC_CONTEXT_CTRL_OFFSET
&& (offset - PLIC_CONTEXT_CTRL_OFFSET).is_multiple_of(PLIC_CONTEXT_STRIDE) =>
{
perform_mmio_read(host_addr, width)
}
// claim/complete
offset
if offset >= PLIC_CONTEXT_CTRL_OFFSET
&& (offset - PLIC_CONTEXT_CTRL_OFFSET - PLIC_CONTEXT_CLAIM_COMPLETE_OFFSET)
.is_multiple_of(PLIC_CONTEXT_STRIDE) =>
{
let context_id =
(offset - PLIC_CONTEXT_CTRL_OFFSET - PLIC_CONTEXT_CLAIM_COMPLETE_OFFSET)
/ PLIC_CONTEXT_STRIDE;
assert!(
context_id < self.contexts_num,
"Invalid context id {context_id}"
);
let mut pending_irqs = self.pending_irqs.lock();
let irq_id = match pending_irqs.first_index() {
Some(id) => id,
None => return Ok(0),
};
// Check if the IRQ is belong to this context_id, check if is enabled, etc.
// TODO: check enable bit and priority, threshold.
// Clear the pending bit and set the active bit, means the IRQ is being handling.
pending_irqs.set(irq_id, false);
self.active_irqs.lock().set(irq_id, true);
Ok(irq_id)
}
_ => {
unimplemented!("Unsupported vPlicGlobal read for reg {reg:#x}")
}
}
}
/// Handles MMIO write operations to the virtual PLIC.
///
/// Only 32-bit (Dword) accesses are supported.
/// Write operations are forwarded to the host PLIC for most registers.
/// Writes to the pending register are used for interrupt injection by the hypervisor.
/// Writes to the claim/complete register complete interrupt handling.
fn handle_write(
&self,
addr: <GuestPhysAddrRange as axaddrspace::device::DeviceAddrRange>::Addr,
width: axaddrspace::device::AccessWidth,
val: usize,
) -> ax_errno::AxResult {
assert_eq!(width, AccessWidth::Dword);
let reg = addr - self.addr;
let host_addr = HostPhysAddr::from_usize(reg + self.host_plic_addr.as_usize());
// info!("vPlicGlobal write reg {reg:#x} width {width:?} val {val:#x}");
match reg {
// priority
PLIC_PRIORITY_OFFSET..PLIC_PENDING_OFFSET => perform_mmio_write(host_addr, width, val),
// pending (Here is uesd for hyperivosr to inject pending IRQs, later should move it to a separate interface)
PLIC_PENDING_OFFSET..PLIC_ENABLE_OFFSET => {
// Note: here append, not overwrite.
let reg_index = (reg - PLIC_PENDING_OFFSET) / 4;
let val = val as u32;
let mut bit_mask: u32 = 1;
let mut pending_irqs = self.pending_irqs.lock();
for i in 0..32 {
if (val & bit_mask) != 0 {
let irq_id = reg_index * 32 + i;
// Set the pending bit.
pending_irqs.set(irq_id, true);
// info!("vPlicGlobal: IRQ {} set to pending", irq_id);
}
bit_mask <<= 1;
}
// Inject the interrupt to the hart by setting the VSEIP bit in HVIP register.
if !pending_irqs.is_empty() {
unsafe {
riscv_h::register::hvip::set_vseip();
}
}
Ok(())
}
// enable
PLIC_ENABLE_OFFSET..PLIC_CONTEXT_CTRL_OFFSET => {
perform_mmio_write(host_addr, width, val)
}
// threshold
offset
if offset >= PLIC_CONTEXT_CTRL_OFFSET
&& (offset - PLIC_CONTEXT_CTRL_OFFSET).is_multiple_of(PLIC_CONTEXT_STRIDE) =>
{
perform_mmio_write(host_addr, width, val)
}
// claim/complete
offset
if offset >= PLIC_CONTEXT_CTRL_OFFSET
&& (offset - PLIC_CONTEXT_CTRL_OFFSET - PLIC_CONTEXT_CLAIM_COMPLETE_OFFSET)
.is_multiple_of(PLIC_CONTEXT_STRIDE) =>
{
// info!("vPlicGlobal: Writing to CLAIM/COMPLETE reg {reg:#x} val {val:#x}");
let context_id =
(offset - PLIC_CONTEXT_CTRL_OFFSET - PLIC_CONTEXT_CLAIM_COMPLETE_OFFSET)
/ PLIC_CONTEXT_STRIDE;
assert!(
context_id < self.contexts_num,
"Invalid context id {context_id}"
);
let irq_id = val;
// There is no irq to handle.
if self.pending_irqs.lock().is_empty() {
unsafe {
riscv_h::register::hvip::clear_vseip();
}
}
// Clear the active bit, means the IRQ handling is complete.
self.active_irqs.lock().set(irq_id, false);
// Write host PLIC.
perform_mmio_write(host_addr, width, irq_id)
}
_ => {
unimplemented!("Unsupported vPlicGlobal read for reg {reg:#x}")
}
}
}
}