riscv-types 0.1.0

Low level access to RISC-V processors
Documentation 
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[lib]
name = "riscv_types"
path = "src/lib.rs"

[package]
authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
autobenches = false
autobins = false
autoexamples = false
autolib = false
autotests = false
build = false
categories = ["embedded", "hardware-support", "no-std"]
description = "Low level access to RISC-V processors"
documentation = "https://docs.rs/riscv-types"
edition = "2021"
keywords = ["riscv", "register", "peripheral"]
license = "MIT OR Apache-2.0"
name = "riscv-types"
readme = "README.md"
repository = "https://github.com/rust-embedded/riscv"
rust-version = "1.81"
version = "0.1.0"

[package.metadata.docs.rs]
default-target = "riscv64imac-unknown-none-elf"
targets = ["riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf", "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf"]