riscv-rt 0.6.1

Minimal runtime / startup for RISC-V CPU's
#ifndef _RISCV_RT_ASM_H
#define _RISCV_RT_ASM_H

#if __riscv_xlen == 64
# define STORE    sd
# define LOAD     ld
# define LOG_REGBYTES 3
#else
# define STORE    sw
# define LOAD     lw
# define LOG_REGBYTES 2
#endif
#define REGBYTES (1 << LOG_REGBYTES)

#endif