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// Copyright 2025 The Axvisor Team
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//! RISC-V Hypervisor Extension Registers for 64-bit Systems
//!
//! This module contains implementations of all hypervisor and virtual supervisor
//! registers for 64-bit RISC-V systems with the hypervisor extension.
/// Hypervisor counter enable register
/// Hypervisor exception delegation register
/// Hypervisor guest address translation and protection register
/// Hypervisor guest external interrupt enable register
/// Hypervisor guest external interrupt pending register
/// Hypervisor interrupt delegation register
/// Hypervisor interrupt enable register
/// Hypervisor interrupt pending register
/// Hypervisor status register
/// Hypervisor time delta register
/// Hypervisor time delta high register (for RV32)
/// Hypervisor trap instruction register
/// Hypervisor trap value register
/// Hypervisor virtual interrupt pending register
/// Virtual supervisor address translation and protection register
/// Virtual supervisor cause register
/// Virtual supervisor exception program counter
/// Virtual supervisor interrupt enable register
/// Virtual supervisor interrupt pending register
/// Virtual supervisor scratch register
/// Virtual supervisor status register
/// Virtual supervisor timer compare register
/// Virtual supervisor trap value register
/// Virtual supervisor trap vector register