riscv-aia 0.0.0

Low level access to the RISC-V Advanced Interrupt Architecture (AIA)
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

//! Hypervisor VIPRIO1 high-half (hviprio1h) (RV32 only)

riscv::read_write_csr! {
    /// Upper 32 bits of hviprio1.
    Hviprio1h: 0x656,
    mask: 0xFFFF_FFFF,
}

impl Hviprio1h {
    #[inline]
    pub const fn raw(self) -> usize {
        self.bits
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn hviprio1h_raw_roundtrip() {
        let bits: usize = 0xDEAD_BEEFusize & 0xFFFF_FFFF;
        let reg = Hviprio1h::from_bits(bits);
        assert_eq!(reg.raw(), bits);
    }
}