// Copyright 2023 RISC Zero, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// This code is automatically generated
#include "ffi.h"
#include "fp.h"
#include <array>
#include <cassert>
#include <stdexcept>
// clang-format off
namespace risc0::circuit::rv32im {
#if defined(__clang__)
#pragma clang diagnostic ignored "-Wunused-parameter"
#pragma clang diagnostic ignored "-Wunused-variable"
#endif
Fp step_exec(void* ctx, HostBridge host, size_t steps, size_t cycle, Fp** args) {
size_t mask = steps - 1;
std::array<Fp, 32> host_args;
std::array<Fp, 32> host_outs;
// loc("cirgen/circuit/rv32im/ffpu.cpp":51:20)
Fp x0(943718400);
// loc("cirgen/circuit/rv32im/ffpu.cpp":47:25)
Fp x1(268435454);
// loc("cirgen/circuit/rv32im/page_fault.cpp":143:20)
Fp x2(56361024);
// loc("cirgen/circuit/rv32im/page_fault.cpp":141:23)
Fp x3(54525952);
// loc("cirgen/circuit/rv32im/page_fault.cpp":134:18)
Fp x4(63);
// loc("cirgen/circuit/rv32im/page_fault.cpp":123:68)
Fp x5(218806);
// loc("cirgen/circuit/rv32im/page_fault.cpp":109:32)
Fp x6(218805);
// loc("cirgen/components/u32.cpp":56:26)
Fp x7(2013265801);
// loc("cirgen/components/u32.cpp":49:17)
Fp x8(16711680);
// loc("cirgen/components/u32.cpp":48:17)
Fp x9(65280);
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
Fp x10(2013265910);
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
Fp x11(62914560);
// loc("cirgen/circuit/rv32im/sha.cpp":381:24)
Fp x12(56361023);
// loc("cirgen/circuit/rv32im/sha.cpp":342:18)
Fp x13(47);
// loc("cirgen/circuit/rv32im/sha.cpp":314:24)
Fp x14(56360975);
// loc("cirgen/circuit/rv32im/sha.cpp":309:24)
Fp x15(56360967);
// loc("cirgen/circuit/rv32im/sha.cpp":111:30)
Fp x16(2013235201);
// loc("cirgen/circuit/rv32im/sha.cpp":104:46)
Fp x17(2013204481);
// loc("cirgen/circuit/rv32im/sha.cpp":104:34)
Fp x18(32768);
// loc("cirgen/circuit/rv32im/sha.cpp":104:46)
Fp x19(2013143041);
// loc("cirgen/circuit/rv32im/sha.cpp":104:46)
Fp x20(2013020161);
// loc("cirgen/circuit/rv32im/sha.cpp":104:34)
Fp x21(8192);
// loc("cirgen/circuit/rv32im/sha.cpp":104:46)
Fp x22(2012774401);
// loc("cirgen/circuit/rv32im/sha.cpp":104:34)
Fp x23(4096);
// loc("cirgen/circuit/rv32im/sha.cpp":104:46)
Fp x24(2012282881);
// loc("cirgen/circuit/rv32im/sha.cpp":104:34)
Fp x25(2048);
// loc("cirgen/circuit/rv32im/sha.cpp":104:46)
Fp x26(2011299841);
// loc("cirgen/circuit/rv32im/sha.cpp":104:46)
Fp x27(2009333761);
// loc("cirgen/circuit/rv32im/sha.cpp":104:34)
Fp x28(512);
// loc("cirgen/circuit/rv32im/page_fault.cpp":54:24)
Fp x29(1024);
// loc("cirgen/circuit/rv32im/sha.cpp":196:24)
Fp x30(50331661);
// loc("cirgen/circuit/rv32im/sha.cpp":195:24)
Fp x31(50331660);
// loc("cirgen/circuit/rv32im/ecall.cpp":90:25)
Fp x32(50331662);
// loc("cirgen/circuit/rv32im/ecall.cpp":38:45)
Fp x33(50331659);
// loc("cirgen/circuit/rv32im/ecall.cpp":36:43)
Fp x34(50331658);
// loc("cirgen/circuit/rv32im/ecall.cpp":129:49)
Fp x35(50331653);
// loc("cirgen/circuit/rv32im/ecall.cpp":124:21)
Fp x36(115);
// loc("cirgen/components/u32.cpp":238:19)
Fp x37(131070);
// loc("cirgen/components/u32.cpp":234:19)
Fp x38(131072);
// loc("cirgen/components/u32.cpp":189:21)
Fp x39(15);
// loc("cirgen/circuit/rv32im/multiply.cpp":65:32)
Fp x40(31);
// loc("cirgen/circuit/rv32im/multiply.cpp":63:34)
Fp x41(192);
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
Fp x42(35);
// loc("cirgen/circuit/rv32im/memio.cpp":80:79)
Fp x43(16384);
// loc("cirgen/circuit/rv32im/memio.cpp":80:56)
Fp x44(4194304);
// loc("./cirgen/circuit/rv32im/rv32im.inl":60:68)
Fp x45(23);
// loc("./cirgen/circuit/rv32im/rv32im.inl":59:68)
Fp x46(55);
// loc("./cirgen/circuit/rv32im/rv32im.inl":58:68)
Fp x47(103);
// loc("./cirgen/circuit/rv32im/rv32im.inl":57:68)
Fp x48(111);
// loc("./cirgen/circuit/rv32im/rv32im.inl":51:68)
Fp x49(99);
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
Fp x50(240);
// loc("./cirgen/circuit/rv32im/rv32im.inl":45:68)
Fp x51(19);
// loc("./cirgen/circuit/rv32im/rv32im.inl":38:68)
Fp x52(51);
// loc("cirgen/components/u32.cpp":65:36)
Fp x53(1996488705);
// loc("cirgen/components/u32.cpp":65:28)
Fp x54(465814468);
// loc("cirgen/circuit/rv32im/compute.cpp":134:39)
Fp x55(50331648);
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
Fp x56(248);
// loc("cirgen/circuit/rv32im/compute.cpp":45:13)
Fp x57(2013265919);
// loc("cirgen/circuit/rv32im/compute.cpp":17:12)
Fp x58(2013265920);
// loc("cirgen/circuit/rv32im/decode.cpp":28:34)
Fp x59(127);
// loc("cirgen/circuit/rv32im/decode.cpp":24:36)
Fp x60(48);
// loc("cirgen/circuit/rv32im/decode.cpp":23:43)
Fp x61(1981808641);
// loc("cirgen/circuit/rv32im/decode.cpp":23:35)
Fp x62(64);
// loc("cirgen/circuit/rv32im/decode.cpp":15:41)
Fp x63(1006632961);
// loc("cirgen/circuit/rv32im/decode.cpp":14:40)
Fp x64(1761607681);
// loc("cirgen/circuit/rv32im/decode.cpp":13:40)
Fp x65(1887436801);
// loc("cirgen/circuit/rv32im/decode.cpp":13:32)
Fp x66(16);
// loc("cirgen/circuit/rv32im/decode.cpp":12:41)
Fp x67(1950351361);
// loc("cirgen/circuit/rv32im/decode.cpp":12:41)
Fp x68(32);
// loc("cirgen/circuit/rv32im/decode.cpp":12:33)
Fp x69(96);
// loc("cirgen/circuit/rv32im/decode.cpp":11:40)
Fp x70(1997537281);
// loc("cirgen/circuit/rv32im/decode.cpp":11:32)
Fp x71(128);
// loc("./cirgen/components/onehot.h":35:32)
Fp x72(13);
// loc("./cirgen/components/onehot.h":35:32)
Fp x73(12);
// loc("./cirgen/components/onehot.h":35:32)
Fp x74(11);
// loc("./cirgen/components/onehot.h":35:32)
Fp x75(10);
// loc("./cirgen/components/onehot.h":35:32)
Fp x76(9);
// loc("./cirgen/components/onehot.h":35:32)
Fp x77(8);
// loc("./cirgen/components/onehot.h":35:32)
Fp x78(7);
// loc("./cirgen/components/onehot.h":35:32)
Fp x79(6);
// loc("./cirgen/components/onehot.h":35:32)
Fp x80(5);
// loc("cirgen/circuit/rv32im/body.cpp":31:21)
Fp x81(67108864);
// loc("cirgen/circuit/rv32im/body.cpp":48:18)
Fp x82(14);
// loc("cirgen/circuit/rv32im/body.cpp":18:43)
Fp x83(1509949441);
// loc("cirgen/circuit/rv32im/body.cpp":17:32)
Fp x84(3);
// loc("cirgen/circuit/rv32im/body.cpp":14:29)
Fp x85(4);
// loc("./cirgen/components/u32.h":27:12)
Fp x86(16777216);
// loc("./cirgen/components/u32.h":26:12)
Fp x87(65536);
// loc("cirgen/circuit/rv32im/body.cpp":45:40)
Fp x88(56014263);
// loc("cirgen/circuit/rv32im/body.cpp":45:40)
Fp x89(56014262);
// loc("cirgen/circuit/rv32im/body.cpp":45:40)
Fp x90(56014261);
// loc("cirgen/circuit/rv32im/body.cpp":45:40)
Fp x91(56014260);
// loc("cirgen/circuit/rv32im/body.cpp":45:40)
Fp x92(56014259);
// loc("cirgen/circuit/rv32im/body.cpp":45:40)
Fp x93(56014258);
// loc("cirgen/circuit/rv32im/body.cpp":45:40)
Fp x94(56014257);
// loc("cirgen/circuit/rv32im/body.cpp":45:40)
Fp x95(56014256);
// loc("cirgen/components/bytes.cpp":83:30)
Fp x96(2005401601);
// loc("cirgen/components/bytes.cpp":83:30)
Fp x97(256);
// loc("cirgen/components/bytes.cpp":82:26)
Fp x98(255);
// loc("cirgen/components/bytes.cpp":37:25)
Fp x99(2);
// loc("cirgen/components/bytes.cpp":34:29)
Fp x100(254);
// loc("cirgen/components/bytes.cpp":21:13)
Fp x101(0);
// loc("cirgen/circuit/rv32im/top.cpp":18:17)
Fp x102(1);
// loc("Top/Code/OneHot/Reg1"("./cirgen/components/mux.h":37:25))
auto x103 = args[0][2 * steps + ((cycle - 0) & mask)];
assert(x103 != Fp::invalid());
if (x103 != 0) {
// loc("Top/Code/OneHot/Reg1"("cirgen/circuit/rv32im/top.cpp":18:69))
auto x104 = args[0][2 * steps + ((cycle - 1) & mask)];
assert(x104 != Fp::invalid());
// loc("cirgen/circuit/rv32im/top.cpp":18:17)
auto x105 = x102 - x104;
// loc("Top/Code/Mux/1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x106 = args[0][8 * steps + ((cycle - 0) & mask)];
assert(x106 != Fp::invalid());
if (x105 != 0) {
// loc("cirgen/components/bytes.cpp":21:3)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":22:3)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("cirgen/components/bytes.cpp":103:17)
auto x107 = x102 - x105;
if (x107 != 0) {
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x108 = args[2][50 * steps + ((cycle - 1) & mask)];
assert(x108 != Fp::invalid());
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement20/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x109 = args[2][51 * steps + ((cycle - 1) & mask)];
assert(x109 != Fp::invalid());
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x110 = x109 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x111 = (x110 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x112 = x102 - x111;
if (x112 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x108);
reg = x108;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x113 = x109 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x113);
reg = x113;
}
}
if (x111 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x114 = x108 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x114);
reg = x114;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x115 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x115 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x116 = x115 - x108;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x117 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x117 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x118 = x117 - x109;
// loc("cirgen/components/bytes.cpp":46:19)
auto x119 = x116 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x120 = x116 * x119;
// loc("cirgen/components/bytes.cpp":46:7)
if (x120 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x121 = x118 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x122 = x116 * x121;
// loc("cirgen/components/bytes.cpp":47:7)
if (x122 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x123 = x118 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x124 = x119 * x123;
// loc("cirgen/components/bytes.cpp":48:7)
if (x124 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x125 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x125 != Fp::invalid());
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x126 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x126 != Fp::invalid());
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x127 = x126 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x128 = (x127 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x129 = x102 - x128;
if (x129 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x125);
reg = x125;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x130 = x126 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][13 * steps + cycle];
assert(reg == Fp::invalid() || reg == x130);
reg = x130;
}
}
if (x128 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x131 = x125 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x131);
reg = x131;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][13 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement1/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x132 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x132 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x133 = x132 - x125;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement1/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x134 = args[2][13 * steps + ((cycle - 0) & mask)];
assert(x134 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x135 = x134 - x126;
// loc("cirgen/components/bytes.cpp":46:19)
auto x136 = x133 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x137 = x133 * x136;
// loc("cirgen/components/bytes.cpp":46:7)
if (x137 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x138 = x135 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x139 = x133 * x138;
// loc("cirgen/components/bytes.cpp":47:7)
if (x139 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x140 = x135 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x141 = x136 * x140;
// loc("cirgen/components/bytes.cpp":48:7)
if (x141 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x142 = x134 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x143 = (x142 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x144 = x102 - x143;
if (x144 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][14 * steps + cycle];
assert(reg == Fp::invalid() || reg == x132);
reg = x132;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x145 = x134 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][15 * steps + cycle];
assert(reg == Fp::invalid() || reg == x145);
reg = x145;
}
}
if (x143 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x146 = x132 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][14 * steps + cycle];
assert(reg == Fp::invalid() || reg == x146);
reg = x146;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][15 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement2/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x147 = args[2][14 * steps + ((cycle - 0) & mask)];
assert(x147 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x148 = x147 - x132;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement2/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x149 = args[2][15 * steps + ((cycle - 0) & mask)];
assert(x149 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x150 = x149 - x134;
// loc("cirgen/components/bytes.cpp":46:19)
auto x151 = x148 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x152 = x148 * x151;
// loc("cirgen/components/bytes.cpp":46:7)
if (x152 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x153 = x150 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x154 = x148 * x153;
// loc("cirgen/components/bytes.cpp":47:7)
if (x154 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x155 = x150 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x156 = x151 * x155;
// loc("cirgen/components/bytes.cpp":48:7)
if (x156 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x157 = x149 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x158 = (x157 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x159 = x102 - x158;
if (x159 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][16 * steps + cycle];
assert(reg == Fp::invalid() || reg == x147);
reg = x147;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x160 = x149 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][17 * steps + cycle];
assert(reg == Fp::invalid() || reg == x160);
reg = x160;
}
}
if (x158 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x161 = x147 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][16 * steps + cycle];
assert(reg == Fp::invalid() || reg == x161);
reg = x161;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][17 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement3/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x162 = args[2][16 * steps + ((cycle - 0) & mask)];
assert(x162 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x163 = x162 - x147;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement3/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x164 = args[2][17 * steps + ((cycle - 0) & mask)];
assert(x164 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x165 = x164 - x149;
// loc("cirgen/components/bytes.cpp":46:19)
auto x166 = x163 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x167 = x163 * x166;
// loc("cirgen/components/bytes.cpp":46:7)
if (x167 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x168 = x165 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x169 = x163 * x168;
// loc("cirgen/components/bytes.cpp":47:7)
if (x169 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x170 = x165 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x171 = x166 * x170;
// loc("cirgen/components/bytes.cpp":48:7)
if (x171 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x172 = x164 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x173 = (x172 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x174 = x102 - x173;
if (x174 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][18 * steps + cycle];
assert(reg == Fp::invalid() || reg == x162);
reg = x162;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x175 = x164 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][19 * steps + cycle];
assert(reg == Fp::invalid() || reg == x175);
reg = x175;
}
}
if (x173 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x176 = x162 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][18 * steps + cycle];
assert(reg == Fp::invalid() || reg == x176);
reg = x176;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][19 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement4/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x177 = args[2][18 * steps + ((cycle - 0) & mask)];
assert(x177 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x178 = x177 - x162;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement4/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x179 = args[2][19 * steps + ((cycle - 0) & mask)];
assert(x179 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x180 = x179 - x164;
// loc("cirgen/components/bytes.cpp":46:19)
auto x181 = x178 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x182 = x178 * x181;
// loc("cirgen/components/bytes.cpp":46:7)
if (x182 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x183 = x180 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x184 = x178 * x183;
// loc("cirgen/components/bytes.cpp":47:7)
if (x184 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x185 = x180 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x186 = x181 * x185;
// loc("cirgen/components/bytes.cpp":48:7)
if (x186 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x187 = x179 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x188 = (x187 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x189 = x102 - x188;
if (x189 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][20 * steps + cycle];
assert(reg == Fp::invalid() || reg == x177);
reg = x177;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x190 = x179 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][21 * steps + cycle];
assert(reg == Fp::invalid() || reg == x190);
reg = x190;
}
}
if (x188 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x191 = x177 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][20 * steps + cycle];
assert(reg == Fp::invalid() || reg == x191);
reg = x191;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][21 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement5/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x192 = args[2][20 * steps + ((cycle - 0) & mask)];
assert(x192 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x193 = x192 - x177;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement5/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x194 = args[2][21 * steps + ((cycle - 0) & mask)];
assert(x194 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x195 = x194 - x179;
// loc("cirgen/components/bytes.cpp":46:19)
auto x196 = x193 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x197 = x193 * x196;
// loc("cirgen/components/bytes.cpp":46:7)
if (x197 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x198 = x195 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x199 = x193 * x198;
// loc("cirgen/components/bytes.cpp":47:7)
if (x199 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x200 = x195 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x201 = x196 * x200;
// loc("cirgen/components/bytes.cpp":48:7)
if (x201 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x202 = x194 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x203 = (x202 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x204 = x102 - x203;
if (x204 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][22 * steps + cycle];
assert(reg == Fp::invalid() || reg == x192);
reg = x192;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x205 = x194 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][23 * steps + cycle];
assert(reg == Fp::invalid() || reg == x205);
reg = x205;
}
}
if (x203 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x206 = x192 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][22 * steps + cycle];
assert(reg == Fp::invalid() || reg == x206);
reg = x206;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][23 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement6/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x207 = args[2][22 * steps + ((cycle - 0) & mask)];
assert(x207 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x208 = x207 - x192;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement6/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x209 = args[2][23 * steps + ((cycle - 0) & mask)];
assert(x209 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x210 = x209 - x194;
// loc("cirgen/components/bytes.cpp":46:19)
auto x211 = x208 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x212 = x208 * x211;
// loc("cirgen/components/bytes.cpp":46:7)
if (x212 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x213 = x210 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x214 = x208 * x213;
// loc("cirgen/components/bytes.cpp":47:7)
if (x214 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x215 = x210 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x216 = x211 * x215;
// loc("cirgen/components/bytes.cpp":48:7)
if (x216 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x217 = x209 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x218 = (x217 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x219 = x102 - x218;
if (x219 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][24 * steps + cycle];
assert(reg == Fp::invalid() || reg == x207);
reg = x207;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x220 = x209 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x220);
reg = x220;
}
}
if (x218 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x221 = x207 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][24 * steps + cycle];
assert(reg == Fp::invalid() || reg == x221);
reg = x221;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement7/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x222 = args[2][24 * steps + ((cycle - 0) & mask)];
assert(x222 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x223 = x222 - x207;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement7/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x224 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x224 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x225 = x224 - x209;
// loc("cirgen/components/bytes.cpp":46:19)
auto x226 = x223 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x227 = x223 * x226;
// loc("cirgen/components/bytes.cpp":46:7)
if (x227 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x228 = x225 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x229 = x223 * x228;
// loc("cirgen/components/bytes.cpp":47:7)
if (x229 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x230 = x225 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x231 = x226 * x230;
// loc("cirgen/components/bytes.cpp":48:7)
if (x231 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
if (x106 != 0) {
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][42 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][43 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][44 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][45 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][46 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][47 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][48 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][49 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":112:7)
{
auto& reg = args[2][50 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":113:7)
{
auto& reg = args[2][51 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("cirgen/components/bytes.cpp":116:16)
auto x232 = x102 - x106;
if (x232 != 0) {
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x233 = x224 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x234 = (x233 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x235 = x102 - x234;
if (x235 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x222);
reg = x222;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x236 = x224 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x236);
reg = x236;
}
}
if (x234 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x237 = x222 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x237);
reg = x237;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement8/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x238 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x238 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x239 = x238 - x222;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement8/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x240 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x240 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x241 = x240 - x224;
// loc("cirgen/components/bytes.cpp":46:19)
auto x242 = x239 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x243 = x239 * x242;
// loc("cirgen/components/bytes.cpp":46:7)
if (x243 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x244 = x241 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x245 = x239 * x244;
// loc("cirgen/components/bytes.cpp":47:7)
if (x245 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x246 = x241 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x247 = x242 * x246;
// loc("cirgen/components/bytes.cpp":48:7)
if (x247 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x248 = x240 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x249 = (x248 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x250 = x102 - x249;
if (x250 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x238);
reg = x238;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x251 = x240 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x251);
reg = x251;
}
}
if (x249 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x252 = x238 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x252);
reg = x252;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement9/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x253 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x253 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x254 = x253 - x238;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement9/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x255 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x255 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x256 = x255 - x240;
// loc("cirgen/components/bytes.cpp":46:19)
auto x257 = x254 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x258 = x254 * x257;
// loc("cirgen/components/bytes.cpp":46:7)
if (x258 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x259 = x256 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x260 = x254 * x259;
// loc("cirgen/components/bytes.cpp":47:7)
if (x260 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x261 = x256 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x262 = x257 * x261;
// loc("cirgen/components/bytes.cpp":48:7)
if (x262 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x263 = x255 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x264 = (x263 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x265 = x102 - x264;
if (x265 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x253);
reg = x253;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x266 = x255 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x266);
reg = x266;
}
}
if (x264 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x267 = x253 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x267);
reg = x267;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement10/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x268 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x268 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x269 = x268 - x253;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement10/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x270 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x270 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x271 = x270 - x255;
// loc("cirgen/components/bytes.cpp":46:19)
auto x272 = x269 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x273 = x269 * x272;
// loc("cirgen/components/bytes.cpp":46:7)
if (x273 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x274 = x271 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x275 = x269 * x274;
// loc("cirgen/components/bytes.cpp":47:7)
if (x275 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x276 = x271 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x277 = x272 * x276;
// loc("cirgen/components/bytes.cpp":48:7)
if (x277 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x278 = x270 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x279 = (x278 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x280 = x102 - x279;
if (x280 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x268);
reg = x268;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x281 = x270 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x281);
reg = x281;
}
}
if (x279 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x282 = x268 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x282);
reg = x282;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement11/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x283 = args[2][32 * steps + ((cycle - 0) & mask)];
assert(x283 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x284 = x283 - x268;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement11/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x285 = args[2][33 * steps + ((cycle - 0) & mask)];
assert(x285 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x286 = x285 - x270;
// loc("cirgen/components/bytes.cpp":46:19)
auto x287 = x284 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x288 = x284 * x287;
// loc("cirgen/components/bytes.cpp":46:7)
if (x288 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x289 = x286 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x290 = x284 * x289;
// loc("cirgen/components/bytes.cpp":47:7)
if (x290 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x291 = x286 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x292 = x287 * x291;
// loc("cirgen/components/bytes.cpp":48:7)
if (x292 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x293 = x285 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x294 = (x293 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x295 = x102 - x294;
if (x295 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x283);
reg = x283;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x296 = x285 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x296);
reg = x296;
}
}
if (x294 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x297 = x283 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x297);
reg = x297;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement12/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x298 = args[2][34 * steps + ((cycle - 0) & mask)];
assert(x298 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x299 = x298 - x283;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement12/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x300 = args[2][35 * steps + ((cycle - 0) & mask)];
assert(x300 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x301 = x300 - x285;
// loc("cirgen/components/bytes.cpp":46:19)
auto x302 = x299 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x303 = x299 * x302;
// loc("cirgen/components/bytes.cpp":46:7)
if (x303 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x304 = x301 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x305 = x299 * x304;
// loc("cirgen/components/bytes.cpp":47:7)
if (x305 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x306 = x301 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x307 = x302 * x306;
// loc("cirgen/components/bytes.cpp":48:7)
if (x307 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x308 = x300 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x309 = (x308 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x310 = x102 - x309;
if (x310 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x298);
reg = x298;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x311 = x300 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x311);
reg = x311;
}
}
if (x309 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x312 = x298 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x312);
reg = x312;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement13/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x313 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x313 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x314 = x313 - x298;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement13/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x315 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x315 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x316 = x315 - x300;
// loc("cirgen/components/bytes.cpp":46:19)
auto x317 = x314 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x318 = x314 * x317;
// loc("cirgen/components/bytes.cpp":46:7)
if (x318 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x319 = x316 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x320 = x314 * x319;
// loc("cirgen/components/bytes.cpp":47:7)
if (x320 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x321 = x316 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x322 = x317 * x321;
// loc("cirgen/components/bytes.cpp":48:7)
if (x322 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x323 = x315 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x324 = (x323 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x325 = x102 - x324;
if (x325 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x313);
reg = x313;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x326 = x315 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x326);
reg = x326;
}
}
if (x324 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x327 = x313 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x327);
reg = x327;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement14/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x328 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x328 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x329 = x328 - x313;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement14/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x330 = args[2][39 * steps + ((cycle - 0) & mask)];
assert(x330 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x331 = x330 - x315;
// loc("cirgen/components/bytes.cpp":46:19)
auto x332 = x329 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x333 = x329 * x332;
// loc("cirgen/components/bytes.cpp":46:7)
if (x333 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x334 = x331 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x335 = x329 * x334;
// loc("cirgen/components/bytes.cpp":47:7)
if (x335 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x336 = x331 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x337 = x332 * x336;
// loc("cirgen/components/bytes.cpp":48:7)
if (x337 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x338 = x330 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x339 = (x338 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x340 = x102 - x339;
if (x340 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x328);
reg = x328;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x341 = x330 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x341);
reg = x341;
}
}
if (x339 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x342 = x328 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x342);
reg = x342;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement15/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x343 = args[2][40 * steps + ((cycle - 0) & mask)];
assert(x343 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x344 = x343 - x328;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement15/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x345 = args[2][41 * steps + ((cycle - 0) & mask)];
assert(x345 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x346 = x345 - x330;
// loc("cirgen/components/bytes.cpp":46:19)
auto x347 = x344 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x348 = x344 * x347;
// loc("cirgen/components/bytes.cpp":46:7)
if (x348 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x349 = x346 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x350 = x344 * x349;
// loc("cirgen/components/bytes.cpp":47:7)
if (x350 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x351 = x346 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x352 = x347 * x351;
// loc("cirgen/components/bytes.cpp":48:7)
if (x352 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x353 = x345 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x354 = (x353 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x355 = x102 - x354;
if (x355 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][42 * steps + cycle];
assert(reg == Fp::invalid() || reg == x343);
reg = x343;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x356 = x345 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][43 * steps + cycle];
assert(reg == Fp::invalid() || reg == x356);
reg = x356;
}
}
if (x354 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x357 = x343 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][42 * steps + cycle];
assert(reg == Fp::invalid() || reg == x357);
reg = x357;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][43 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement16/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x358 = args[2][42 * steps + ((cycle - 0) & mask)];
assert(x358 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x359 = x358 - x343;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement16/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x360 = args[2][43 * steps + ((cycle - 0) & mask)];
assert(x360 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x361 = x360 - x345;
// loc("cirgen/components/bytes.cpp":46:19)
auto x362 = x359 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x363 = x359 * x362;
// loc("cirgen/components/bytes.cpp":46:7)
if (x363 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x364 = x361 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x365 = x359 * x364;
// loc("cirgen/components/bytes.cpp":47:7)
if (x365 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x366 = x361 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x367 = x362 * x366;
// loc("cirgen/components/bytes.cpp":48:7)
if (x367 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x368 = x360 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x369 = (x368 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x370 = x102 - x369;
if (x370 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][44 * steps + cycle];
assert(reg == Fp::invalid() || reg == x358);
reg = x358;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x371 = x360 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][45 * steps + cycle];
assert(reg == Fp::invalid() || reg == x371);
reg = x371;
}
}
if (x369 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x372 = x358 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][44 * steps + cycle];
assert(reg == Fp::invalid() || reg == x372);
reg = x372;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][45 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement17/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x373 = args[2][44 * steps + ((cycle - 0) & mask)];
assert(x373 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x374 = x373 - x358;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement17/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x375 = args[2][45 * steps + ((cycle - 0) & mask)];
assert(x375 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x376 = x375 - x360;
// loc("cirgen/components/bytes.cpp":46:19)
auto x377 = x374 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x378 = x374 * x377;
// loc("cirgen/components/bytes.cpp":46:7)
if (x378 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x379 = x376 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x380 = x374 * x379;
// loc("cirgen/components/bytes.cpp":47:7)
if (x380 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x381 = x376 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x382 = x377 * x381;
// loc("cirgen/components/bytes.cpp":48:7)
if (x382 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x383 = x375 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x384 = (x383 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x385 = x102 - x384;
if (x385 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][46 * steps + cycle];
assert(reg == Fp::invalid() || reg == x373);
reg = x373;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x386 = x375 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][47 * steps + cycle];
assert(reg == Fp::invalid() || reg == x386);
reg = x386;
}
}
if (x384 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x387 = x373 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][46 * steps + cycle];
assert(reg == Fp::invalid() || reg == x387);
reg = x387;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][47 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement18/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x388 = args[2][46 * steps + ((cycle - 0) & mask)];
assert(x388 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x389 = x388 - x373;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement18/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x390 = args[2][47 * steps + ((cycle - 0) & mask)];
assert(x390 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x391 = x390 - x375;
// loc("cirgen/components/bytes.cpp":46:19)
auto x392 = x389 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x393 = x389 * x392;
// loc("cirgen/components/bytes.cpp":46:7)
if (x393 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x394 = x391 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x395 = x389 * x394;
// loc("cirgen/components/bytes.cpp":47:7)
if (x395 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x396 = x391 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x397 = x392 * x396;
// loc("cirgen/components/bytes.cpp":48:7)
if (x397 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x398 = x390 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x399 = (x398 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x400 = x102 - x399;
if (x400 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][48 * steps + cycle];
assert(reg == Fp::invalid() || reg == x388);
reg = x388;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x401 = x390 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][49 * steps + cycle];
assert(reg == Fp::invalid() || reg == x401);
reg = x401;
}
}
if (x399 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x402 = x388 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][48 * steps + cycle];
assert(reg == Fp::invalid() || reg == x402);
reg = x402;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][49 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement19/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x403 = args[2][48 * steps + ((cycle - 0) & mask)];
assert(x403 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x404 = x403 - x388;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement19/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x405 = args[2][49 * steps + ((cycle - 0) & mask)];
assert(x405 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x406 = x405 - x390;
// loc("cirgen/components/bytes.cpp":46:19)
auto x407 = x404 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x408 = x404 * x407;
// loc("cirgen/components/bytes.cpp":46:7)
if (x408 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x409 = x406 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x410 = x404 * x409;
// loc("cirgen/components/bytes.cpp":47:7)
if (x410 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x411 = x406 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x412 = x407 * x411;
// loc("cirgen/components/bytes.cpp":48:7)
if (x412 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
{
// loc("cirgen/components/bytes.cpp":34:20)
auto x413 = x405 - x100;
// loc("cirgen/components/bytes.cpp":34:20)
auto x414 = (x413 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/bytes.cpp":35:16)
auto x415 = x102 - x414;
if (x415 != 0) {
// loc("cirgen/components/bytes.cpp":36:7)
{
auto& reg = args[2][50 * steps + cycle];
assert(reg == Fp::invalid() || reg == x403);
reg = x403;
}
// loc("cirgen/components/bytes.cpp":37:16)
auto x416 = x405 + x99;
// loc("cirgen/components/bytes.cpp":37:7)
{
auto& reg = args[2][51 * steps + cycle];
assert(reg == Fp::invalid() || reg == x416);
reg = x416;
}
}
if (x414 != 0) {
// loc("cirgen/components/bytes.cpp":40:17)
auto x417 = x403 + x102;
// loc("cirgen/components/bytes.cpp":40:7)
{
auto& reg = args[2][50 * steps + cycle];
assert(reg == Fp::invalid() || reg == x417);
reg = x417;
}
// loc("cirgen/components/bytes.cpp":41:7)
{
auto& reg = args[2][51 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement20/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x418 = args[2][50 * steps + ((cycle - 0) & mask)];
assert(x418 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":44:18)
auto x419 = x418 - x403;
// loc("Top/Mux/1/BytesSetup/PlonkBody/BytesPlonkElement20/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x420 = args[2][51 * steps + ((cycle - 0) & mask)];
assert(x420 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":45:17)
auto x421 = x420 - x405;
// loc("cirgen/components/bytes.cpp":46:19)
auto x422 = x419 - x102;
// loc("cirgen/components/bytes.cpp":46:7)
auto x423 = x419 * x422;
// loc("cirgen/components/bytes.cpp":46:7)
if (x423 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:46");
// loc("cirgen/components/bytes.cpp":47:19)
auto x424 = x421 + x100;
// loc("cirgen/components/bytes.cpp":47:7)
auto x425 = x419 * x424;
// loc("cirgen/components/bytes.cpp":47:7)
if (x425 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:47");
// loc("cirgen/components/bytes.cpp":48:25)
auto x426 = x421 - x99;
// loc("cirgen/components/bytes.cpp":48:7)
auto x427 = x422 * x426;
// loc("cirgen/components/bytes.cpp":48:7)
if (x427 != 0) throw std::runtime_error("eqz failed at: cirgen/components/bytes.cpp:48");
}
}
// loc("Top/Code/OneHot/Reg2"("./cirgen/components/mux.h":37:25))
auto x428 = args[0][3 * steps + ((cycle - 0) & mask)];
assert(x428 != Fp::invalid());
if (x428 != 0) {
// loc("Top/Code/Mux/2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x429 = args[0][9 * steps + ((cycle - 0) & mask)];
assert(x429 != Fp::invalid());
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x430 = Fp(x429.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][19 * steps + cycle];
assert(reg == Fp::invalid() || reg == x430);
reg = x430;
}
}
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement4/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x431 = args[2][19 * steps + ((cycle - 0) & mask)];
assert(x431 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x432 = x429 - x431;
// loc("cirgen/components/bytes.cpp":83:10)
auto x433 = x432 * x96;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][20 * steps + cycle];
assert(reg == Fp::invalid() || reg == x433);
reg = x433;
}
// loc("Top/Code/Mux/2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x434 = args[0][10 * steps + ((cycle - 0) & mask)];
assert(x434 != Fp::invalid());
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x435 = Fp(x434.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][21 * steps + cycle];
assert(reg == Fp::invalid() || reg == x435);
reg = x435;
}
}
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement5/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x436 = args[2][21 * steps + ((cycle - 0) & mask)];
assert(x436 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x437 = x434 - x436;
// loc("cirgen/components/bytes.cpp":83:10)
auto x438 = x437 * x96;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][22 * steps + cycle];
assert(reg == Fp::invalid() || reg == x438);
reg = x438;
}
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement5/Reg"("cirgen/components/bytes.cpp":78:10))
auto x439 = args[2][20 * steps + ((cycle - 0) & mask)];
assert(x439 != Fp::invalid());
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement6/Reg"("cirgen/components/bytes.cpp":78:10))
auto x440 = args[2][22 * steps + ((cycle - 0) & mask)];
assert(x440 != Fp::invalid());
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x441 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x441 != Fp::invalid());
// loc("Top/Code/Mux/2/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x442 = args[0][8 * steps + ((cycle - 0) & mask)];
assert(x442 != Fp::invalid());
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][58 * steps + cycle];
assert(reg == Fp::invalid() || reg == x431);
reg = x431;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][59 * steps + cycle];
assert(reg == Fp::invalid() || reg == x439);
reg = x439;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][60 * steps + cycle];
assert(reg == Fp::invalid() || reg == x436);
reg = x436;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][61 * steps + cycle];
assert(reg == Fp::invalid() || reg == x440);
reg = x440;
}
{
host_args.at(0) = x442;
host_args.at(1) = x431;
host_args.at(2) = x439;
host_args.at(3) = x436;
host_args.at(4) = x440;
host_args.at(5) = x101;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x443 = args[2][58 * steps + ((cycle - 0) & mask)];
assert(x443 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x444 = args[2][59 * steps + ((cycle - 0) & mask)];
assert(x444 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x445 = args[2][60 * steps + ((cycle - 0) & mask)];
assert(x445 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x446 = args[2][61 * steps + ((cycle - 0) & mask)];
assert(x446 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][55 * steps + cycle];
assert(reg == Fp::invalid() || reg == x442);
reg = x442;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][56 * steps + cycle];
assert(reg == Fp::invalid() || reg == x441);
reg = x441;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][57 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][58 * steps + cycle];
assert(reg == Fp::invalid() || reg == x443);
reg = x443;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][59 * steps + cycle];
assert(reg == Fp::invalid() || reg == x444);
reg = x444;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][60 * steps + cycle];
assert(reg == Fp::invalid() || reg == x445);
reg = x445;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][61 * steps + cycle];
assert(reg == Fp::invalid() || reg == x446);
reg = x446;
}
// loc("Top/Code/Mux/2/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x447 = args[0][11 * steps + ((cycle - 0) & mask)];
assert(x447 != Fp::invalid());
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x448 = Fp(x447.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][23 * steps + cycle];
assert(reg == Fp::invalid() || reg == x448);
reg = x448;
}
}
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement6/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x449 = args[2][23 * steps + ((cycle - 0) & mask)];
assert(x449 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x450 = x447 - x449;
// loc("cirgen/components/bytes.cpp":83:10)
auto x451 = x450 * x96;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][24 * steps + cycle];
assert(reg == Fp::invalid() || reg == x451);
reg = x451;
}
// loc("Top/Code/Mux/2/Reg4"("./cirgen/compiler/edsl/component.h":85:27))
auto x452 = args[0][12 * steps + ((cycle - 0) & mask)];
assert(x452 != Fp::invalid());
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x453 = Fp(x452.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x453);
reg = x453;
}
}
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x454 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x454 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x455 = x452 - x454;
// loc("cirgen/components/bytes.cpp":83:10)
auto x456 = x455 * x96;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x456);
reg = x456;
}
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement7/Reg"("cirgen/components/bytes.cpp":78:10))
auto x457 = args[2][24 * steps + ((cycle - 0) & mask)];
assert(x457 != Fp::invalid());
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("cirgen/components/bytes.cpp":78:10))
auto x458 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x458 != Fp::invalid());
// loc("cirgen/circuit/rv32im/top.cpp":38:44)
auto x459 = x442 + x102;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][65 * steps + cycle];
assert(reg == Fp::invalid() || reg == x449);
reg = x449;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][66 * steps + cycle];
assert(reg == Fp::invalid() || reg == x457);
reg = x457;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][67 * steps + cycle];
assert(reg == Fp::invalid() || reg == x454);
reg = x454;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][68 * steps + cycle];
assert(reg == Fp::invalid() || reg == x458);
reg = x458;
}
{
host_args.at(0) = x459;
host_args.at(1) = x449;
host_args.at(2) = x457;
host_args.at(3) = x454;
host_args.at(4) = x458;
host_args.at(5) = x101;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x460 = args[2][65 * steps + ((cycle - 0) & mask)];
assert(x460 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x461 = args[2][66 * steps + ((cycle - 0) & mask)];
assert(x461 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x462 = args[2][67 * steps + ((cycle - 0) & mask)];
assert(x462 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x463 = args[2][68 * steps + ((cycle - 0) & mask)];
assert(x463 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][62 * steps + cycle];
assert(reg == Fp::invalid() || reg == x459);
reg = x459;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][63 * steps + cycle];
assert(reg == Fp::invalid() || reg == x441);
reg = x441;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][64 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][65 * steps + cycle];
assert(reg == Fp::invalid() || reg == x460);
reg = x460;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][66 * steps + cycle];
assert(reg == Fp::invalid() || reg == x461);
reg = x461;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][67 * steps + cycle];
assert(reg == Fp::invalid() || reg == x462);
reg = x462;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][68 * steps + cycle];
assert(reg == Fp::invalid() || reg == x463);
reg = x463;
}
// loc("Top/Code/Mux/2/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x464 = args[0][13 * steps + ((cycle - 0) & mask)];
assert(x464 != Fp::invalid());
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x465 = Fp(x464.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x465);
reg = x465;
}
}
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x466 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x466 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x467 = x464 - x466;
// loc("cirgen/components/bytes.cpp":83:10)
auto x468 = x467 * x96;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x468);
reg = x468;
}
// loc("Top/Code/Mux/2/Reg6"("./cirgen/compiler/edsl/component.h":85:27))
auto x469 = args[0][14 * steps + ((cycle - 0) & mask)];
assert(x469 != Fp::invalid());
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x470 = Fp(x469.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x470);
reg = x470;
}
}
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x471 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x471 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x472 = x469 - x471;
// loc("cirgen/components/bytes.cpp":83:10)
auto x473 = x472 * x96;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x473);
reg = x473;
}
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("cirgen/components/bytes.cpp":78:10))
auto x474 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x474 != Fp::invalid());
// loc("Top/Mux/2/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("cirgen/components/bytes.cpp":78:10))
auto x475 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x475 != Fp::invalid());
// loc("cirgen/circuit/rv32im/top.cpp":38:44)
auto x476 = x442 + x99;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x466);
reg = x466;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x474);
reg = x474;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][74 * steps + cycle];
assert(reg == Fp::invalid() || reg == x471);
reg = x471;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][75 * steps + cycle];
assert(reg == Fp::invalid() || reg == x475);
reg = x475;
}
{
host_args.at(0) = x476;
host_args.at(1) = x466;
host_args.at(2) = x474;
host_args.at(3) = x471;
host_args.at(4) = x475;
host_args.at(5) = x101;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x477 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x477 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x478 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x478 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x479 = args[2][74 * steps + ((cycle - 0) & mask)];
assert(x479 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x480 = args[2][75 * steps + ((cycle - 0) & mask)];
assert(x480 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][69 * steps + cycle];
assert(reg == Fp::invalid() || reg == x476);
reg = x476;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][70 * steps + cycle];
assert(reg == Fp::invalid() || reg == x441);
reg = x441;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][71 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x477);
reg = x477;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x478);
reg = x478;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][74 * steps + cycle];
assert(reg == Fp::invalid() || reg == x479);
reg = x479;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][75 * steps + cycle];
assert(reg == Fp::invalid() || reg == x480);
reg = x480;
}
}
// loc("Top/Code/OneHot/Reg3"("./cirgen/components/mux.h":37:25))
auto x481 = args[0][4 * steps + ((cycle - 0) & mask)];
assert(x481 != Fp::invalid());
if (x481 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x482 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x482 != Fp::invalid());
// loc("Top/Mux/3/U32Reg1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x483 = args[1][4];
// loc("Top/Mux/3/U32Reg1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x484 = args[1][5];
// loc("Top/Mux/3/U32Reg1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x485 = args[1][6];
// loc("Top/Mux/3/U32Reg1/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x486 = args[1][7];
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][97 * steps + cycle];
assert(reg == Fp::invalid() || reg == x483);
reg = x483;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][98 * steps + cycle];
assert(reg == Fp::invalid() || reg == x484);
reg = x484;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][99 * steps + cycle];
assert(reg == Fp::invalid() || reg == x485);
reg = x485;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][100 * steps + cycle];
assert(reg == Fp::invalid() || reg == x486);
reg = x486;
}
{
host_args.at(0) = x95;
host_args.at(1) = x483;
host_args.at(2) = x484;
host_args.at(3) = x485;
host_args.at(4) = x486;
host_args.at(5) = x101;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x487 = args[2][97 * steps + ((cycle - 0) & mask)];
assert(x487 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x488 = args[2][98 * steps + ((cycle - 0) & mask)];
assert(x488 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x489 = args[2][99 * steps + ((cycle - 0) & mask)];
assert(x489 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x490 = args[2][100 * steps + ((cycle - 0) & mask)];
assert(x490 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][94 * steps + cycle];
assert(reg == Fp::invalid() || reg == x95);
reg = x95;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][95 * steps + cycle];
assert(reg == Fp::invalid() || reg == x482);
reg = x482;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][96 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][97 * steps + cycle];
assert(reg == Fp::invalid() || reg == x487);
reg = x487;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][98 * steps + cycle];
assert(reg == Fp::invalid() || reg == x488);
reg = x488;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][99 * steps + cycle];
assert(reg == Fp::invalid() || reg == x489);
reg = x489;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][100 * steps + cycle];
assert(reg == Fp::invalid() || reg == x490);
reg = x490;
}
// loc("Top/Mux/3/U32Reg2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x491 = args[1][8];
// loc("Top/Mux/3/U32Reg2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x492 = args[1][9];
// loc("Top/Mux/3/U32Reg2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x493 = args[1][10];
// loc("Top/Mux/3/U32Reg2/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x494 = args[1][11];
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][104 * steps + cycle];
assert(reg == Fp::invalid() || reg == x491);
reg = x491;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][105 * steps + cycle];
assert(reg == Fp::invalid() || reg == x492);
reg = x492;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][106 * steps + cycle];
assert(reg == Fp::invalid() || reg == x493);
reg = x493;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][107 * steps + cycle];
assert(reg == Fp::invalid() || reg == x494);
reg = x494;
}
{
host_args.at(0) = x94;
host_args.at(1) = x491;
host_args.at(2) = x492;
host_args.at(3) = x493;
host_args.at(4) = x494;
host_args.at(5) = x101;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x495 = args[2][104 * steps + ((cycle - 0) & mask)];
assert(x495 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x496 = args[2][105 * steps + ((cycle - 0) & mask)];
assert(x496 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x497 = args[2][106 * steps + ((cycle - 0) & mask)];
assert(x497 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x498 = args[2][107 * steps + ((cycle - 0) & mask)];
assert(x498 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][101 * steps + cycle];
assert(reg == Fp::invalid() || reg == x94);
reg = x94;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][102 * steps + cycle];
assert(reg == Fp::invalid() || reg == x482);
reg = x482;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][103 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][104 * steps + cycle];
assert(reg == Fp::invalid() || reg == x495);
reg = x495;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][105 * steps + cycle];
assert(reg == Fp::invalid() || reg == x496);
reg = x496;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][106 * steps + cycle];
assert(reg == Fp::invalid() || reg == x497);
reg = x497;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][107 * steps + cycle];
assert(reg == Fp::invalid() || reg == x498);
reg = x498;
}
// loc("Top/Mux/3/U32Reg3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x499 = args[1][12];
// loc("Top/Mux/3/U32Reg3/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x500 = args[1][13];
// loc("Top/Mux/3/U32Reg3/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x501 = args[1][14];
// loc("Top/Mux/3/U32Reg3/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x502 = args[1][15];
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x499);
reg = x499;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x500);
reg = x500;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x501);
reg = x501;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x502);
reg = x502;
}
{
host_args.at(0) = x93;
host_args.at(1) = x499;
host_args.at(2) = x500;
host_args.at(3) = x501;
host_args.at(4) = x502;
host_args.at(5) = x101;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x503 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x503 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x504 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x504 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x505 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x505 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x506 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x506 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x93);
reg = x93;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x482);
reg = x482;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x503);
reg = x503;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x504);
reg = x504;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x505);
reg = x505;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x506);
reg = x506;
}
// loc("Top/Mux/3/U32Reg4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x507 = args[1][16];
// loc("Top/Mux/3/U32Reg4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x508 = args[1][17];
// loc("Top/Mux/3/U32Reg4/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x509 = args[1][18];
// loc("Top/Mux/3/U32Reg4/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x510 = args[1][19];
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x507);
reg = x507;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x508);
reg = x508;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x509);
reg = x509;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x510);
reg = x510;
}
{
host_args.at(0) = x92;
host_args.at(1) = x507;
host_args.at(2) = x508;
host_args.at(3) = x509;
host_args.at(4) = x510;
host_args.at(5) = x101;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x511 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x511 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x512 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x512 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x513 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x513 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x514 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x514 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x92);
reg = x92;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x482);
reg = x482;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x511);
reg = x511;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x512);
reg = x512;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x513);
reg = x513;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x514);
reg = x514;
}
// loc("Top/Mux/3/U32Reg5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x515 = args[1][20];
// loc("Top/Mux/3/U32Reg5/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x516 = args[1][21];
// loc("Top/Mux/3/U32Reg5/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x517 = args[1][22];
// loc("Top/Mux/3/U32Reg5/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x518 = args[1][23];
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x515);
reg = x515;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x516);
reg = x516;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x517);
reg = x517;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x518);
reg = x518;
}
{
host_args.at(0) = x91;
host_args.at(1) = x515;
host_args.at(2) = x516;
host_args.at(3) = x517;
host_args.at(4) = x518;
host_args.at(5) = x101;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x519 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x519 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x520 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x520 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x521 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x521 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x522 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x522 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x91);
reg = x91;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x482);
reg = x482;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x519);
reg = x519;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x520);
reg = x520;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x521);
reg = x521;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x522);
reg = x522;
}
// loc("Top/Mux/3/U32Reg6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x523 = args[1][24];
// loc("Top/Mux/3/U32Reg6/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x524 = args[1][25];
// loc("Top/Mux/3/U32Reg6/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x525 = args[1][26];
// loc("Top/Mux/3/U32Reg6/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x526 = args[1][27];
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x523);
reg = x523;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x524);
reg = x524;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x525);
reg = x525;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x526);
reg = x526;
}
{
host_args.at(0) = x90;
host_args.at(1) = x523;
host_args.at(2) = x524;
host_args.at(3) = x525;
host_args.at(4) = x526;
host_args.at(5) = x101;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement5/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x527 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x527 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement5/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x528 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x528 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement5/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x529 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x529 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement5/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x530 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x530 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x90);
reg = x90;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x482);
reg = x482;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x527);
reg = x527;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x528);
reg = x528;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x529);
reg = x529;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x530);
reg = x530;
}
// loc("Top/Mux/3/U32Reg7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x531 = args[1][28];
// loc("Top/Mux/3/U32Reg7/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x532 = args[1][29];
// loc("Top/Mux/3/U32Reg7/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x533 = args[1][30];
// loc("Top/Mux/3/U32Reg7/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x534 = args[1][31];
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x531);
reg = x531;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x532);
reg = x532;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x533);
reg = x533;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x534);
reg = x534;
}
{
host_args.at(0) = x89;
host_args.at(1) = x531;
host_args.at(2) = x532;
host_args.at(3) = x533;
host_args.at(4) = x534;
host_args.at(5) = x101;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement6/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x535 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x535 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement6/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x536 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x536 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement6/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x537 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x537 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement6/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x538 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x538 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x89);
reg = x89;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x482);
reg = x482;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x535);
reg = x535;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x536);
reg = x536;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x537);
reg = x537;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x538);
reg = x538;
}
// loc("Top/Mux/3/U32Reg8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x539 = args[1][32];
// loc("Top/Mux/3/U32Reg8/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x540 = args[1][33];
// loc("Top/Mux/3/U32Reg8/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x541 = args[1][34];
// loc("Top/Mux/3/U32Reg8/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x542 = args[1][35];
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][146 * steps + cycle];
assert(reg == Fp::invalid() || reg == x539);
reg = x539;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][147 * steps + cycle];
assert(reg == Fp::invalid() || reg == x540);
reg = x540;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][148 * steps + cycle];
assert(reg == Fp::invalid() || reg == x541);
reg = x541;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][149 * steps + cycle];
assert(reg == Fp::invalid() || reg == x542);
reg = x542;
}
{
host_args.at(0) = x88;
host_args.at(1) = x539;
host_args.at(2) = x540;
host_args.at(3) = x541;
host_args.at(4) = x542;
host_args.at(5) = x101;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement7/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x543 = args[2][146 * steps + ((cycle - 0) & mask)];
assert(x543 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement7/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x544 = args[2][147 * steps + ((cycle - 0) & mask)];
assert(x544 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement7/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x545 = args[2][148 * steps + ((cycle - 0) & mask)];
assert(x545 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement7/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x546 = args[2][149 * steps + ((cycle - 0) & mask)];
assert(x546 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][143 * steps + cycle];
assert(reg == Fp::invalid() || reg == x88);
reg = x88;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][144 * steps + cycle];
assert(reg == Fp::invalid() || reg == x482);
reg = x482;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][145 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][146 * steps + cycle];
assert(reg == Fp::invalid() || reg == x543);
reg = x543;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][147 * steps + cycle];
assert(reg == Fp::invalid() || reg == x544);
reg = x544;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][148 * steps + cycle];
assert(reg == Fp::invalid() || reg == x545);
reg = x545;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][149 * steps + cycle];
assert(reg == Fp::invalid() || reg == x546);
reg = x546;
}
// loc("Top/Mux/3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x547 = args[1][0];
// loc("Top/Mux/3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x548 = args[1][1];
// loc("Top/Mux/3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x549 = args[1][2];
// loc("Top/Mux/3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x550 = args[1][3];
// loc("./cirgen/components/u32.h":25:12)
auto x551 = x548 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x552 = x547 + x551;
// loc("./cirgen/components/u32.h":26:12)
auto x553 = x549 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x554 = x552 + x553;
// loc("./cirgen/components/u32.h":27:12)
auto x555 = x550 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x556 = x554 + x555;
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x557 = x556 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x558 = Fp(x557.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x558);
reg = x558;
}
}
// loc("Top/Mux/3/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x559 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x559 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x560 = x557 - x559;
// loc("cirgen/components/bytes.cpp":83:10)
auto x561 = x560 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x562 = Fp(x561.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x562);
reg = x562;
}
}
// loc("Top/Mux/3/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x563 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x563 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x564 = x561 - x563;
// loc("cirgen/components/bytes.cpp":83:10)
auto x565 = x564 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x566 = Fp(x565.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x566);
reg = x566;
}
}
// loc("Top/Mux/3/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x567 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x567 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x568 = x565 - x567;
// loc("cirgen/components/bytes.cpp":83:10)
auto x569 = x568 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x570 = Fp(x569.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x570);
reg = x570;
}
}
// loc("Top/Mux/3/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x571 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x571 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x572 = x569 - x571;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x573 = x572 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x573);
reg = x573;
}
// loc("Top/Mux/3/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x574 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x574 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x575 = x102 - x574;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x576 = x574 * x575;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x576);
reg = x576;
}
// loc("Top/Mux/3/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x577 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x577 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x578 = x99 - x574;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x579 = x577 * x578;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x579 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("cirgen/circuit/rv32im/body.cpp":48:3)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":28:10)
auto x580 = x563 * x97;
// loc("cirgen/circuit/rv32im/body.cpp":27:10)
auto x581 = x559 + x580;
// loc("cirgen/circuit/rv32im/body.cpp":29:10)
auto x582 = x567 * x87;
// loc("cirgen/circuit/rv32im/body.cpp":27:10)
auto x583 = x581 + x582;
// loc("cirgen/circuit/rv32im/body.cpp":30:10)
auto x584 = x571 * x86;
// loc("cirgen/circuit/rv32im/body.cpp":27:10)
auto x585 = x583 + x584;
// loc("cirgen/circuit/rv32im/body.cpp":31:10)
auto x586 = x574 * x81;
// loc("cirgen/circuit/rv32im/body.cpp":27:10)
auto x587 = x585 + x586;
// loc("cirgen/circuit/rv32im/body.cpp":27:10)
auto x588 = x587 - x85;
host_args.at(0) = x482;
host_args.at(1) = x588;
host(ctx, "log", "%u: Reset: PC = 0x%x", host_args.data(), 2, host_outs.data(), 0);
}
// loc("Top/Code/OneHot/Reg4"("./cirgen/components/mux.h":37:25))
auto x589 = args[0][5 * steps + ((cycle - 0) & mask)];
assert(x589 != Fp::invalid());
if (x589 != 0) {
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":78:10))
auto x590 = args[2][10 * steps + ((cycle - 1) & mask)];
assert(x590 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x591 = args[2][11 * steps + ((cycle - 1) & mask)];
assert(x591 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":28:10)
auto x592 = x591 * x97;
// loc("cirgen/circuit/rv32im/body.cpp":27:10)
auto x593 = x590 + x592;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":78:10))
auto x594 = args[2][12 * steps + ((cycle - 1) & mask)];
assert(x594 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":29:10)
auto x595 = x594 * x87;
// loc("cirgen/circuit/rv32im/body.cpp":27:10)
auto x596 = x593 + x595;
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x597 = args[2][72 * steps + ((cycle - 1) & mask)];
assert(x597 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":30:10)
auto x598 = x597 * x86;
// loc("cirgen/circuit/rv32im/body.cpp":27:10)
auto x599 = x596 + x598;
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x600 = args[2][73 * steps + ((cycle - 1) & mask)];
assert(x600 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":31:10)
auto x601 = x600 * x81;
// loc("cirgen/circuit/rv32im/body.cpp":27:10)
auto x602 = x599 + x601;
// loc("cirgen/circuit/rv32im/body.cpp":27:10)
auto x603 = x602 - x85;
{
// loc("Top/Mux/4/Reg"("cirgen/circuit/rv32im/body.cpp":59:45))
auto x604 = args[2][93 * steps + ((cycle - 1) & mask)];
assert(x604 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":60:24)
auto x605 = x604 - x82;
// loc("cirgen/circuit/rv32im/body.cpp":60:24)
auto x606 = (x605 == 0) ? Fp(1) : Fp(0);
if (x606 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x607 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x607 != Fp::invalid());
host_args.at(0) = x607;
host_args.at(1) = x603;
host(ctx, "log", "%u: BODY pc: 0x%x", host_args.data(), 2, host_outs.data(), 0);
host_args.at(0) = x603;
host(ctx, "trace", "", host_args.data(), 1, host_outs.data(), 0);
host_args.at(0) = x603;
host(ctx, "getMajor", "", host_args.data(), 1, host_outs.data(), 1);
auto x608 = host_outs.at(0);
{
// loc("./cirgen/components/onehot.h":35:26)
auto x609 = (x608 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][94 * steps + cycle];
assert(reg == Fp::invalid() || reg == x609);
reg = x609;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x610 = x608 - x102;
// loc("./cirgen/components/onehot.h":35:26)
auto x611 = (x610 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][95 * steps + cycle];
assert(reg == Fp::invalid() || reg == x611);
reg = x611;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x612 = x608 - x99;
// loc("./cirgen/components/onehot.h":35:26)
auto x613 = (x612 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][96 * steps + cycle];
assert(reg == Fp::invalid() || reg == x613);
reg = x613;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x614 = x608 - x84;
// loc("./cirgen/components/onehot.h":35:26)
auto x615 = (x614 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][97 * steps + cycle];
assert(reg == Fp::invalid() || reg == x615);
reg = x615;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x616 = x608 - x85;
// loc("./cirgen/components/onehot.h":35:26)
auto x617 = (x616 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][98 * steps + cycle];
assert(reg == Fp::invalid() || reg == x617);
reg = x617;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x618 = x608 - x80;
// loc("./cirgen/components/onehot.h":35:26)
auto x619 = (x618 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][99 * steps + cycle];
assert(reg == Fp::invalid() || reg == x619);
reg = x619;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x620 = x608 - x79;
// loc("./cirgen/components/onehot.h":35:26)
auto x621 = (x620 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][100 * steps + cycle];
assert(reg == Fp::invalid() || reg == x621);
reg = x621;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x622 = x608 - x78;
// loc("./cirgen/components/onehot.h":35:26)
auto x623 = (x622 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][101 * steps + cycle];
assert(reg == Fp::invalid() || reg == x623);
reg = x623;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x624 = x608 - x77;
// loc("./cirgen/components/onehot.h":35:26)
auto x625 = (x624 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][102 * steps + cycle];
assert(reg == Fp::invalid() || reg == x625);
reg = x625;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x626 = x608 - x76;
// loc("./cirgen/components/onehot.h":35:26)
auto x627 = (x626 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][103 * steps + cycle];
assert(reg == Fp::invalid() || reg == x627);
reg = x627;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x628 = x608 - x75;
// loc("./cirgen/components/onehot.h":35:26)
auto x629 = (x628 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][104 * steps + cycle];
assert(reg == Fp::invalid() || reg == x629);
reg = x629;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x630 = x608 - x74;
// loc("./cirgen/components/onehot.h":35:26)
auto x631 = (x630 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][105 * steps + cycle];
assert(reg == Fp::invalid() || reg == x631);
reg = x631;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x632 = x608 - x73;
// loc("./cirgen/components/onehot.h":35:26)
auto x633 = (x632 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][106 * steps + cycle];
assert(reg == Fp::invalid() || reg == x633);
reg = x633;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x634 = x608 - x72;
// loc("./cirgen/components/onehot.h":35:26)
auto x635 = (x634 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][107 * steps + cycle];
assert(reg == Fp::invalid() || reg == x635);
reg = x635;
}
}
// loc("Top/Mux/4/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x636 = args[2][95 * steps + ((cycle - 0) & mask)];
assert(x636 != Fp::invalid());
// loc("Top/Mux/4/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x637 = args[2][96 * steps + ((cycle - 0) & mask)];
assert(x637 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x638 = x637 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x639 = x636 + x638;
// loc("Top/Mux/4/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x640 = args[2][97 * steps + ((cycle - 0) & mask)];
assert(x640 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x641 = x640 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x642 = x639 + x641;
// loc("Top/Mux/4/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x643 = args[2][98 * steps + ((cycle - 0) & mask)];
assert(x643 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x644 = x643 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x645 = x642 + x644;
// loc("Top/Mux/4/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x646 = args[2][99 * steps + ((cycle - 0) & mask)];
assert(x646 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x647 = x646 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x648 = x645 + x647;
// loc("Top/Mux/4/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x649 = args[2][100 * steps + ((cycle - 0) & mask)];
assert(x649 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x650 = x649 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x651 = x648 + x650;
// loc("Top/Mux/4/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x652 = args[2][101 * steps + ((cycle - 0) & mask)];
assert(x652 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x653 = x652 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x654 = x651 + x653;
// loc("Top/Mux/4/OneHot/Reg8"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x655 = args[2][102 * steps + ((cycle - 0) & mask)];
assert(x655 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x656 = x655 * x77;
// loc("./cirgen/components/onehot.h":44:13)
auto x657 = x654 + x656;
// loc("Top/Mux/4/OneHot/Reg9"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x658 = args[2][103 * steps + ((cycle - 0) & mask)];
assert(x658 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x659 = x658 * x76;
// loc("./cirgen/components/onehot.h":44:13)
auto x660 = x657 + x659;
// loc("Top/Mux/4/OneHot/Reg10"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x661 = args[2][104 * steps + ((cycle - 0) & mask)];
assert(x661 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x662 = x661 * x75;
// loc("./cirgen/components/onehot.h":44:13)
auto x663 = x660 + x662;
// loc("Top/Mux/4/OneHot/Reg11"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x664 = args[2][105 * steps + ((cycle - 0) & mask)];
assert(x664 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x665 = x664 * x74;
// loc("./cirgen/components/onehot.h":44:13)
auto x666 = x663 + x665;
// loc("Top/Mux/4/OneHot/Reg12"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x667 = args[2][106 * steps + ((cycle - 0) & mask)];
assert(x667 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x668 = x667 * x73;
// loc("./cirgen/components/onehot.h":44:13)
auto x669 = x666 + x668;
// loc("Top/Mux/4/OneHot/Reg13"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x670 = args[2][107 * steps + ((cycle - 0) & mask)];
assert(x670 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x671 = x670 * x72;
// loc("./cirgen/components/onehot.h":44:13)
auto x672 = x669 + x671;
// loc("./cirgen/components/onehot.h":38:8)
auto x673 = x672 - x608;
// loc("./cirgen/components/onehot.h":38:8)
if (x673 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
// loc("cirgen/circuit/rv32im/body.cpp":67:20)
auto x674 = x102 - x606;
if (x674 != 0) {
// loc("cirgen/circuit/rv32im/body.cpp":68:48)
auto x675 = x604 - x77;
// loc("cirgen/circuit/rv32im/body.cpp":68:48)
auto x676 = (x675 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/circuit/rv32im/body.cpp":68:48)
auto x677 = x102 - x676;
if (x677 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x678 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x678 != Fp::invalid());
host_args.at(0) = x678;
host_args.at(1) = x603;
host_args.at(2) = x604;
host(ctx, "log", "%u: BODY pc: 0x%x, major = %u", host_args.data(), 3, host_outs.data(), 0);
}
{
// loc("./cirgen/components/onehot.h":35:26)
auto x679 = (x604 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][94 * steps + cycle];
assert(reg == Fp::invalid() || reg == x679);
reg = x679;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x680 = x604 - x102;
// loc("./cirgen/components/onehot.h":35:26)
auto x681 = (x680 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][95 * steps + cycle];
assert(reg == Fp::invalid() || reg == x681);
reg = x681;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x682 = x604 - x99;
// loc("./cirgen/components/onehot.h":35:26)
auto x683 = (x682 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][96 * steps + cycle];
assert(reg == Fp::invalid() || reg == x683);
reg = x683;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x684 = x604 - x84;
// loc("./cirgen/components/onehot.h":35:26)
auto x685 = (x684 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][97 * steps + cycle];
assert(reg == Fp::invalid() || reg == x685);
reg = x685;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x686 = x604 - x85;
// loc("./cirgen/components/onehot.h":35:26)
auto x687 = (x686 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][98 * steps + cycle];
assert(reg == Fp::invalid() || reg == x687);
reg = x687;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x688 = x604 - x80;
// loc("./cirgen/components/onehot.h":35:26)
auto x689 = (x688 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][99 * steps + cycle];
assert(reg == Fp::invalid() || reg == x689);
reg = x689;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x690 = x604 - x79;
// loc("./cirgen/components/onehot.h":35:26)
auto x691 = (x690 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][100 * steps + cycle];
assert(reg == Fp::invalid() || reg == x691);
reg = x691;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x692 = x604 - x78;
// loc("./cirgen/components/onehot.h":35:26)
auto x693 = (x692 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][101 * steps + cycle];
assert(reg == Fp::invalid() || reg == x693);
reg = x693;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][102 * steps + cycle];
assert(reg == Fp::invalid() || reg == x676);
reg = x676;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x694 = x604 - x76;
// loc("./cirgen/components/onehot.h":35:26)
auto x695 = (x694 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][103 * steps + cycle];
assert(reg == Fp::invalid() || reg == x695);
reg = x695;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x696 = x604 - x75;
// loc("./cirgen/components/onehot.h":35:26)
auto x697 = (x696 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][104 * steps + cycle];
assert(reg == Fp::invalid() || reg == x697);
reg = x697;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x698 = x604 - x74;
// loc("./cirgen/components/onehot.h":35:26)
auto x699 = (x698 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][105 * steps + cycle];
assert(reg == Fp::invalid() || reg == x699);
reg = x699;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x700 = x604 - x73;
// loc("./cirgen/components/onehot.h":35:26)
auto x701 = (x700 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][106 * steps + cycle];
assert(reg == Fp::invalid() || reg == x701);
reg = x701;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x702 = x604 - x72;
// loc("./cirgen/components/onehot.h":35:26)
auto x703 = (x702 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][107 * steps + cycle];
assert(reg == Fp::invalid() || reg == x703);
reg = x703;
}
}
// loc("Top/Mux/4/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x704 = args[2][95 * steps + ((cycle - 0) & mask)];
assert(x704 != Fp::invalid());
// loc("Top/Mux/4/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x705 = args[2][96 * steps + ((cycle - 0) & mask)];
assert(x705 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x706 = x705 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x707 = x704 + x706;
// loc("Top/Mux/4/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x708 = args[2][97 * steps + ((cycle - 0) & mask)];
assert(x708 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x709 = x708 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x710 = x707 + x709;
// loc("Top/Mux/4/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x711 = args[2][98 * steps + ((cycle - 0) & mask)];
assert(x711 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x712 = x711 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x713 = x710 + x712;
// loc("Top/Mux/4/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x714 = args[2][99 * steps + ((cycle - 0) & mask)];
assert(x714 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x715 = x714 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x716 = x713 + x715;
// loc("Top/Mux/4/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x717 = args[2][100 * steps + ((cycle - 0) & mask)];
assert(x717 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x718 = x717 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x719 = x716 + x718;
// loc("Top/Mux/4/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x720 = args[2][101 * steps + ((cycle - 0) & mask)];
assert(x720 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x721 = x720 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x722 = x719 + x721;
// loc("Top/Mux/4/OneHot/Reg8"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x723 = args[2][102 * steps + ((cycle - 0) & mask)];
assert(x723 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x724 = x723 * x77;
// loc("./cirgen/components/onehot.h":44:13)
auto x725 = x722 + x724;
// loc("Top/Mux/4/OneHot/Reg9"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x726 = args[2][103 * steps + ((cycle - 0) & mask)];
assert(x726 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x727 = x726 * x76;
// loc("./cirgen/components/onehot.h":44:13)
auto x728 = x725 + x727;
// loc("Top/Mux/4/OneHot/Reg10"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x729 = args[2][104 * steps + ((cycle - 0) & mask)];
assert(x729 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x730 = x729 * x75;
// loc("./cirgen/components/onehot.h":44:13)
auto x731 = x728 + x730;
// loc("Top/Mux/4/OneHot/Reg11"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x732 = args[2][105 * steps + ((cycle - 0) & mask)];
assert(x732 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x733 = x732 * x74;
// loc("./cirgen/components/onehot.h":44:13)
auto x734 = x731 + x733;
// loc("Top/Mux/4/OneHot/Reg12"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x735 = args[2][106 * steps + ((cycle - 0) & mask)];
assert(x735 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x736 = x735 * x73;
// loc("./cirgen/components/onehot.h":44:13)
auto x737 = x734 + x736;
// loc("Top/Mux/4/OneHot/Reg13"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x738 = args[2][107 * steps + ((cycle - 0) & mask)];
assert(x738 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x739 = x738 * x72;
// loc("./cirgen/components/onehot.h":44:13)
auto x740 = x737 + x739;
// loc("./cirgen/components/onehot.h":38:8)
auto x741 = x740 - x604;
// loc("./cirgen/components/onehot.h":38:8)
if (x741 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
}
// loc("Top/Mux/4/OneHot/Reg"("./cirgen/components/mux.h":37:25))
auto x742 = args[2][94 * steps + ((cycle - 0) & mask)];
assert(x742 != Fp::invalid());
if (x742 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x743 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x743 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":112:41)
auto x744 = x603 * x83;
{
host_args.at(0) = x744;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x745 = host_outs.at(0);
auto x746 = host_outs.at(1);
auto x747 = host_outs.at(2);
auto x748 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x745);
reg = x745;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x746);
reg = x746;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x747);
reg = x747;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x748);
reg = x748;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x749 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x749 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x750 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x750 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x751 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x751 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x752 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x752 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x744);
reg = x744;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x743);
reg = x743;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x749);
reg = x749;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x750);
reg = x750;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x751);
reg = x751;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x752);
reg = x752;
}
{
// loc("cirgen/circuit/rv32im/decode.cpp":11:16)
auto x753 = Fp(x752.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":11:15)
auto x754 = x753 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x754);
reg = x754;
}
// loc("cirgen/circuit/rv32im/decode.cpp":12:17)
auto x755 = Fp(x752.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":12:16)
auto x756 = x755 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x756);
reg = x756;
}
// loc("cirgen/circuit/rv32im/decode.cpp":13:16)
auto x757 = Fp(x752.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":13:15)
auto x758 = x757 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x758);
reg = x758;
}
// loc("cirgen/circuit/rv32im/decode.cpp":14:16)
auto x759 = Fp(x752.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":14:15)
auto x760 = x759 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x760);
reg = x760;
}
// loc("cirgen/circuit/rv32im/decode.cpp":15:17)
auto x761 = Fp(x752.asUInt32() & x79.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":15:16)
auto x762 = x761 * x63;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][78 * steps + cycle];
assert(reg == Fp::invalid() || reg == x762);
reg = x762;
}
// loc("cirgen/circuit/rv32im/decode.cpp":16:17)
auto x763 = Fp(x752.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x763);
reg = x763;
}
// loc("cirgen/circuit/rv32im/decode.cpp":17:17)
auto x764 = Fp(x751.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":17:16)
auto x765 = x764 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x765);
reg = x765;
}
// loc("cirgen/circuit/rv32im/decode.cpp":18:18)
auto x766 = Fp(x751.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":18:17)
auto x767 = x766 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x767);
reg = x767;
}
// loc("cirgen/circuit/rv32im/decode.cpp":19:17)
auto x768 = Fp(x751.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":19:16)
auto x769 = x768 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x769);
reg = x769;
}
// loc("cirgen/circuit/rv32im/decode.cpp":20:18)
auto x770 = Fp(x751.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":20:17)
auto x771 = x770 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x771);
reg = x771;
}
// loc("cirgen/circuit/rv32im/decode.cpp":21:18)
auto x772 = Fp(x751.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x772);
reg = x772;
}
// loc("cirgen/circuit/rv32im/decode.cpp":22:17)
auto x773 = Fp(x750.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":22:16)
auto x774 = x773 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x774);
reg = x774;
}
// loc("cirgen/circuit/rv32im/decode.cpp":23:19)
auto x775 = Fp(x750.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":23:18)
auto x776 = x775 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x776);
reg = x776;
}
// loc("cirgen/circuit/rv32im/decode.cpp":24:20)
auto x777 = Fp(x750.asUInt32() & x60.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":24:19)
auto x778 = x777 * x65;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x778);
reg = x778;
}
// loc("cirgen/circuit/rv32im/decode.cpp":25:17)
auto x779 = Fp(x750.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":25:16)
auto x780 = x779 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x780);
reg = x780;
}
// loc("cirgen/circuit/rv32im/decode.cpp":26:17)
auto x781 = Fp(x750.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x781);
reg = x781;
}
// loc("cirgen/circuit/rv32im/decode.cpp":27:16)
auto x782 = Fp(x749.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":27:15)
auto x783 = x782 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][169 * steps + cycle];
assert(reg == Fp::invalid() || reg == x783);
reg = x783;
}
// loc("cirgen/circuit/rv32im/decode.cpp":28:18)
auto x784 = Fp(x749.asUInt32() & x59.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":28:5)
{
auto& reg = args[2][170 * steps + cycle];
assert(reg == Fp::invalid() || reg == x784);
reg = x784;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x785 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x785 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x786 = x785 * x62;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x787 = args[2][79 * steps + ((cycle - 0) & mask)];
assert(x787 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x788 = x787 * x66;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x789 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x789 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:25)
auto x790 = x789 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x791 = x788 + x790;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x792 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x792 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:39)
auto x793 = x792 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x794 = x791 + x793;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x795 = args[2][78 * steps + ((cycle - 0) & mask)];
assert(x795 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x796 = x794 + x795;
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x797 = x786 + x796;
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x798 = x797 * x99;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x799 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x799 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x800 = x798 + x799;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
auto x801 = x752 - x800;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
if (x801 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:30");
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x802 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x802 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x803 = x802 * x77;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Twit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x804 = args[2][80 * steps + ((cycle - 0) & mask)];
assert(x804 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:37)
auto x805 = x804 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x806 = x803 + x805;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x807 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x807 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x808 = x806 + x807;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x809 = x808 * x66;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Twit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x810 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x810 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:69)
auto x811 = x810 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x812 = x809 + x811;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Twit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x813 = args[2][81 * steps + ((cycle - 0) & mask)];
assert(x813 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x814 = x812 + x813;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
auto x815 = x751 - x814;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
if (x815 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:31");
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x816 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x816 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x817 = x816 * x71;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x818 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x818 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x819 = x818 * x85;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Twit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x820 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x820 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x821 = x819 + x820;
// loc("cirgen/circuit/rv32im/decode.cpp":32:36)
auto x822 = x821 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x823 = x817 + x822;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x824 = args[2][85 * steps + ((cycle - 0) & mask)];
assert(x824 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:53)
auto x825 = x824 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x826 = x823 + x825;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x827 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x827 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x828 = x826 + x827;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
auto x829 = x750 - x828;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
if (x829 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:32");
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x830 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x830 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x831 = x830 * x71;
// loc("Top/Mux/4/Mux/0/ComputeCycle/Decoder/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x832 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x832 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x833 = x831 + x832;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
auto x834 = x749 - x833;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
if (x834 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:33");
{
host_args.at(0) = x749;
host_args.at(1) = x750;
host_args.at(2) = x751;
host_args.at(3) = x752;
host(ctx, "getMinor", "", host_args.data(), 4, host_outs.data(), 1);
auto x835 = host_outs.at(0);
{
// loc("./cirgen/components/onehot.h":35:26)
auto x836 = (x835 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][171 * steps + cycle];
assert(reg == Fp::invalid() || reg == x836);
reg = x836;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x837 = x835 - x102;
// loc("./cirgen/components/onehot.h":35:26)
auto x838 = (x837 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][172 * steps + cycle];
assert(reg == Fp::invalid() || reg == x838);
reg = x838;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x839 = x835 - x99;
// loc("./cirgen/components/onehot.h":35:26)
auto x840 = (x839 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x840);
reg = x840;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x841 = x835 - x84;
// loc("./cirgen/components/onehot.h":35:26)
auto x842 = (x841 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][174 * steps + cycle];
assert(reg == Fp::invalid() || reg == x842);
reg = x842;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x843 = x835 - x85;
// loc("./cirgen/components/onehot.h":35:26)
auto x844 = (x843 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][175 * steps + cycle];
assert(reg == Fp::invalid() || reg == x844);
reg = x844;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x845 = x835 - x80;
// loc("./cirgen/components/onehot.h":35:26)
auto x846 = (x845 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x846);
reg = x846;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x847 = x835 - x79;
// loc("./cirgen/components/onehot.h":35:26)
auto x848 = (x847 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x848);
reg = x848;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x849 = x835 - x78;
// loc("./cirgen/components/onehot.h":35:26)
auto x850 = (x849 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x850);
reg = x850;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x851 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x851 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x852 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x852 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x853 = x852 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x854 = x851 + x853;
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x855 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x855 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x856 = x855 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x857 = x854 + x856;
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x858 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x858 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x859 = x858 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x860 = x857 + x859;
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x861 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x861 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x862 = x861 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x863 = x860 + x862;
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x864 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x864 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x865 = x864 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x866 = x863 + x865;
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x867 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x867 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x868 = x867 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x869 = x866 + x868;
// loc("./cirgen/components/onehot.h":38:8)
auto x870 = x869 - x835;
// loc("./cirgen/components/onehot.h":38:8)
if (x870 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
{
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg"("./cirgen/circuit/rv32im/rv32im.inl":38:68))
auto x871 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x871 != Fp::invalid());
if (x871 != 0) {
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":23:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":24:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":25:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg1"("./cirgen/circuit/rv32im/rv32im.inl":39:68))
auto x872 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x872 != Fp::invalid());
if (x872 != 0) {
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg2"("./cirgen/circuit/rv32im/rv32im.inl":40:69))
auto x873 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x873 != Fp::invalid());
if (x873 != 0) {
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":43:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":44:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":45:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x57);
reg = x57;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg3"("./cirgen/circuit/rv32im/rv32im.inl":41:69))
auto x874 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x874 != Fp::invalid());
if (x874 != 0) {
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":38:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":39:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":40:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg4"("./cirgen/circuit/rv32im/rv32im.inl":42:69))
auto x875 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x875 != Fp::invalid());
if (x875 != 0) {
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":33:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":35:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg5"("./cirgen/circuit/rv32im/rv32im.inl":43:68))
auto x876 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x876 != Fp::invalid());
if (x876 != 0) {
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg6"("./cirgen/circuit/rv32im/rv32im.inl":44:68))
auto x877 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x877 != Fp::invalid());
if (x877 != 0) {
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg7"("./cirgen/circuit/rv32im/rv32im.inl":45:68))
auto x878 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x878 != Fp::invalid());
if (x878 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x879 = x792 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x880 = x795 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x881 = x879 + x880;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x882 = x799 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x883 = x882 + x808;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x884 = x881 + x883;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x885 = x785 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x886 = x787 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x887 = x885 + x886;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x888 = x887 + x789;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x889 = x785 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x884);
reg = x884;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x888);
reg = x888;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x889);
reg = x889;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x889);
reg = x889;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":23:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":24:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":25:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
}
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x890 = x810 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":37:26)
auto x891 = x813 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x892 = x890 + x891;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x893 = x892 + x816;
// loc("cirgen/circuit/rv32im/compute.cpp":134:39)
auto x894 = x893 + x55;
{
host_args.at(0) = x894;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x895 = host_outs.at(0);
auto x896 = host_outs.at(1);
auto x897 = host_outs.at(2);
auto x898 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x895);
reg = x895;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x896);
reg = x896;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x897);
reg = x897;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x898);
reg = x898;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x899 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x899 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x900 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x900 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x901 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x901 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x902 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x902 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x894);
reg = x894;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x743);
reg = x743;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x899);
reg = x899;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x900);
reg = x900;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x901);
reg = x901;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x902);
reg = x902;
}
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x903 = x799 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x904 = x903 + x808;
// loc("cirgen/circuit/rv32im/compute.cpp":135:39)
auto x905 = x904 + x55;
{
host_args.at(0) = x905;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x906 = host_outs.at(0);
auto x907 = host_outs.at(1);
auto x908 = host_outs.at(2);
auto x909 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x906);
reg = x906;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x907);
reg = x907;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x908);
reg = x908;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x909);
reg = x909;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x910 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x910 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x911 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x911 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x912 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x912 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x913 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x913 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x905);
reg = x905;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x743);
reg = x743;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x910);
reg = x910;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x911);
reg = x911;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x912);
reg = x912;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x913);
reg = x913;
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x914 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x914 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x915 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x915 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x916 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x916 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x917 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x917 != Fp::invalid());
host_args.at(0) = x914;
host_args.at(1) = x915;
host_args.at(2) = x916;
host_args.at(3) = x917;
host_args.at(4) = x893;
host_args.at(5) = x899;
host_args.at(6) = x900;
host_args.at(7) = x901;
host_args.at(8) = x902;
host_args.at(9) = x904;
host_args.at(10) = x910;
host_args.at(11) = x911;
host_args.at(12) = x912;
host_args.at(13) = x913;
host(ctx, "log", " imm=%w, rs1=x%u -> %w, rs2=x%u -> %w", host_args.data(), 14, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x918 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x918 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":145:17)
auto x919 = x102 - x918;
// loc("cirgen/components/u32.cpp":105:20)
auto x920 = x919 * x899;
// loc("cirgen/components/u32.cpp":105:20)
auto x921 = x919 * x900;
// loc("cirgen/components/u32.cpp":105:20)
auto x922 = x919 * x901;
// loc("cirgen/components/u32.cpp":105:20)
auto x923 = x919 * x902;
// loc("cirgen/circuit/rv32im/body.cpp":35:52)
auto x924 = x600 * x85;
// loc("cirgen/circuit/rv32im/body.cpp":35:41)
auto x925 = x597 + x924;
// loc("cirgen/components/u32.cpp":97:20)
auto x926 = x590 - x85;
// loc("cirgen/components/u32.cpp":105:20)
auto x927 = x918 * x926;
// loc("cirgen/components/u32.cpp":105:20)
auto x928 = x918 * x591;
// loc("cirgen/components/u32.cpp":105:20)
auto x929 = x918 * x594;
// loc("cirgen/components/u32.cpp":105:20)
auto x930 = x918 * x925;
// loc("cirgen/components/u32.cpp":89:20)
auto x931 = x920 + x927;
// loc("cirgen/components/u32.cpp":89:20)
auto x932 = x921 + x928;
// loc("cirgen/components/u32.cpp":89:20)
auto x933 = x922 + x929;
// loc("cirgen/components/u32.cpp":89:20)
auto x934 = x923 + x930;
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x935 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x935 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":147:17)
auto x936 = x102 - x935;
// loc("cirgen/components/u32.cpp":105:20)
auto x937 = x936 * x910;
// loc("cirgen/components/u32.cpp":105:20)
auto x938 = x936 * x911;
// loc("cirgen/components/u32.cpp":105:20)
auto x939 = x936 * x912;
// loc("cirgen/components/u32.cpp":105:20)
auto x940 = x936 * x913;
// loc("cirgen/components/u32.cpp":105:20)
auto x941 = x935 * x914;
// loc("cirgen/components/u32.cpp":105:20)
auto x942 = x935 * x915;
// loc("cirgen/components/u32.cpp":105:20)
auto x943 = x935 * x916;
// loc("cirgen/components/u32.cpp":105:20)
auto x944 = x935 * x917;
// loc("cirgen/components/u32.cpp":89:20)
auto x945 = x937 + x941;
// loc("cirgen/components/u32.cpp":89:20)
auto x946 = x938 + x942;
// loc("cirgen/components/u32.cpp":89:20)
auto x947 = x939 + x943;
// loc("cirgen/components/u32.cpp":89:20)
auto x948 = x940 + x944;
host_args.at(0) = x931;
host_args.at(1) = x932;
host_args.at(2) = x933;
host_args.at(3) = x934;
host_args.at(4) = x945;
host_args.at(5) = x946;
host_args.at(6) = x947;
host_args.at(7) = x948;
host(ctx, "log", " inA = %w, inB = %w", host_args.data(), 8, host_outs.data(), 0);
{
// loc("cirgen/components/u32.cpp":120:18)
auto x949 = Fp(x934.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x950 = x949 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x950);
reg = x950;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x951 = Fp(x934.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x952 = x951 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x952);
reg = x952;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/TopBit/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x953 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x953 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x954 = x953 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x955 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x955 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x956 = x955 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x957 = x954 + x956;
// loc("cirgen/components/u32.cpp":123:6)
auto x958 = x934 - x957;
// loc("cirgen/components/u32.cpp":123:6)
if (x958 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
{
// loc("cirgen/components/u32.cpp":120:18)
auto x959 = Fp(x948.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x960 = x959 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][190 * steps + cycle];
assert(reg == Fp::invalid() || reg == x960);
reg = x960;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x961 = Fp(x948.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x962 = x961 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x962);
reg = x962;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/TopBit1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x963 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x963 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x964 = x963 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("cirgen/components/bytes.cpp":78:10))
auto x965 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x965 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x966 = x965 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x967 = x964 + x966;
// loc("cirgen/components/u32.cpp":123:6)
auto x968 = x948 - x967;
// loc("cirgen/components/u32.cpp":123:6)
if (x968 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][191 * steps + cycle];
assert(reg == Fp::invalid() || reg == x945);
reg = x945;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][192 * steps + cycle];
assert(reg == Fp::invalid() || reg == x946);
reg = x946;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][193 * steps + cycle];
assert(reg == Fp::invalid() || reg == x947);
reg = x947;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][194 * steps + cycle];
assert(reg == Fp::invalid() || reg == x948);
reg = x948;
}
{
// loc("cirgen/components/u32.cpp":113:20)
auto x969 = Fp(x931.asUInt32() & x945.asUInt32());
// loc("cirgen/components/u32.cpp":113:20)
auto x970 = Fp(x932.asUInt32() & x946.asUInt32());
// loc("cirgen/components/u32.cpp":113:20)
auto x971 = Fp(x933.asUInt32() & x947.asUInt32());
// loc("cirgen/components/u32.cpp":113:20)
auto x972 = Fp(x934.asUInt32() & x948.asUInt32());
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][195 * steps + cycle];
assert(reg == Fp::invalid() || reg == x969);
reg = x969;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][196 * steps + cycle];
assert(reg == Fp::invalid() || reg == x970);
reg = x970;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][197 * steps + cycle];
assert(reg == Fp::invalid() || reg == x971);
reg = x971;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][198 * steps + cycle];
assert(reg == Fp::invalid() || reg == x972);
reg = x972;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x973 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x973 != Fp::invalid());
// loc("cirgen/components/u32.cpp":105:20)
auto x974 = x973 * x931;
// loc("cirgen/components/u32.cpp":105:20)
auto x975 = x973 * x932;
// loc("cirgen/components/u32.cpp":105:20)
auto x976 = x973 * x933;
// loc("cirgen/components/u32.cpp":105:20)
auto x977 = x973 * x934;
// loc("cirgen/components/u32.cpp":89:20)
auto x978 = x974 + x97;
// loc("cirgen/components/u32.cpp":89:20)
auto x979 = x975 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x980 = x976 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x981 = x977 + x98;
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x982 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x982 != Fp::invalid());
// loc("cirgen/components/u32.cpp":105:20)
auto x983 = x982 * x945;
// loc("cirgen/components/u32.cpp":105:20)
auto x984 = x982 * x946;
// loc("cirgen/components/u32.cpp":105:20)
auto x985 = x982 * x947;
// loc("cirgen/components/u32.cpp":105:20)
auto x986 = x982 * x948;
// loc("cirgen/components/u32.cpp":89:20)
auto x987 = x978 + x983;
// loc("cirgen/components/u32.cpp":89:20)
auto x988 = x979 + x984;
// loc("cirgen/components/u32.cpp":89:20)
auto x989 = x980 + x985;
// loc("cirgen/components/u32.cpp":89:20)
auto x990 = x981 + x986;
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg4"("./cirgen/compiler/edsl/component.h":85:27))
auto x991 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x991 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x992 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x992 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x993 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x993 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x994 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x994 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg1/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x995 = args[2][198 * steps + ((cycle - 0) & mask)];
assert(x995 != Fp::invalid());
// loc("cirgen/components/u32.cpp":105:20)
auto x996 = x991 * x992;
// loc("cirgen/components/u32.cpp":105:20)
auto x997 = x991 * x993;
// loc("cirgen/components/u32.cpp":105:20)
auto x998 = x991 * x994;
// loc("cirgen/components/u32.cpp":105:20)
auto x999 = x991 * x995;
// loc("cirgen/components/u32.cpp":89:20)
auto x1000 = x987 + x996;
// loc("cirgen/components/u32.cpp":89:20)
auto x1001 = x988 + x997;
// loc("cirgen/components/u32.cpp":89:20)
auto x1002 = x989 + x998;
// loc("cirgen/components/u32.cpp":89:20)
auto x1003 = x990 + x999;
// loc("cirgen/components/u32.cpp":146:29)
auto x1004 = x1001 * x97;
// loc("cirgen/components/u32.cpp":146:15)
auto x1005 = x1000 + x1004;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1006 = Fp(x1005.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1006);
reg = x1006;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1007 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x1007 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1008 = x1005 - x1007;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1009 = x1008 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1010 = Fp(x1009.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1010);
reg = x1010;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1011 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x1011 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1012 = x1009 - x1011;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1013 = x1012 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1013);
reg = x1013;
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Normalize/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1014 = args[2][86 * steps + ((cycle - 0) & mask)];
assert(x1014 != Fp::invalid());
// loc("cirgen/components/u32.cpp":148:16)
auto x1015 = x1014 + x1002;
// loc("cirgen/components/u32.cpp":148:41)
auto x1016 = x1003 * x97;
// loc("cirgen/components/u32.cpp":148:16)
auto x1017 = x1015 + x1016;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1018 = Fp(x1017.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1018);
reg = x1018;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1019 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x1019 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1020 = x1017 - x1019;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1021 = x1020 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1022 = Fp(x1021.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1022);
reg = x1022;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1023 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x1023 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1024 = x1021 - x1023;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1025 = x1024 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1025);
reg = x1025;
}
{
// loc("cirgen/components/u32.cpp":120:18)
auto x1026 = Fp(x1023.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x1027 = x1026 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][199 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1027);
reg = x1027;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x1028 = Fp(x1023.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x1029 = x1028 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1029);
reg = x1029;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/TopBit2/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1030 = args[2][199 * steps + ((cycle - 0) & mask)];
assert(x1030 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x1031 = x1030 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x1032 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x1032 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x1033 = x1032 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x1034 = x1031 + x1033;
// loc("cirgen/components/u32.cpp":123:6)
auto x1035 = x1023 - x1034;
// loc("cirgen/components/u32.cpp":123:6)
if (x1035 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
// loc("cirgen/circuit/rv32im/compute.cpp":69:23)
auto x1036 = x102 - x963;
// loc("cirgen/circuit/rv32im/compute.cpp":69:17)
auto x1037 = x953 * x1036;
// loc("cirgen/circuit/rv32im/compute.cpp":69:34)
auto x1038 = x102 - x1030;
// loc("cirgen/circuit/rv32im/compute.cpp":69:17)
auto x1039 = x1037 * x1038;
// loc("cirgen/circuit/rv32im/compute.cpp":69:45)
auto x1040 = x102 - x953;
// loc("cirgen/circuit/rv32im/compute.cpp":69:44)
auto x1041 = x1040 * x963;
// loc("cirgen/circuit/rv32im/compute.cpp":69:44)
auto x1042 = x1041 * x1030;
// loc("cirgen/circuit/rv32im/compute.cpp":69:17)
auto x1043 = x1039 + x1042;
// loc("cirgen/circuit/rv32im/compute.cpp":69:3)
{
auto& reg = args[2][200 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1043);
reg = x1043;
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1044 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x1044 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":71:11)
auto x1045 = x1044 + x1030;
// loc("cirgen/circuit/rv32im/compute.cpp":71:27)
auto x1046 = x1044 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":71:27)
auto x1047 = x1046 * x1030;
// loc("cirgen/circuit/rv32im/compute.cpp":71:11)
auto x1048 = x1045 - x1047;
// loc("cirgen/circuit/rv32im/compute.cpp":71:3)
{
auto& reg = args[2][201 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1048);
reg = x1048;
}
// loc("cirgen/components/u32.cpp":137:26)
auto x1049 = x1011 * x97;
// loc("cirgen/components/u32.cpp":137:12)
auto x1050 = x1007 + x1049;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x1051 = (x1050 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][202 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1051);
reg = x1051;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x1052 = inv(x1050);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][203 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1052);
reg = x1052;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/IsZeroU32/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1053 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x1053 != Fp::invalid());
if (x1053 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x1050 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x1054 = x102 - x1053;
if (x1054 != 0) {
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/IsZeroU32/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1055 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x1055 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x1056 = x1050 * x1055;
// loc("cirgen/components/iszero.cpp":15:26)
auto x1057 = x1056 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x1057 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("cirgen/components/u32.cpp":138:27)
auto x1058 = x1023 * x97;
// loc("cirgen/components/u32.cpp":138:13)
auto x1059 = x1019 + x1058;
// loc("cirgen/components/u32.cpp":138:47)
auto x1060 = x1054 * x87;
// loc("cirgen/components/u32.cpp":138:13)
auto x1061 = x1059 + x1060;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x1062 = (x1061 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1062);
reg = x1062;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x1063 = inv(x1061);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1063);
reg = x1063;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/IsZeroU32/IsZero1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1064 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x1064 != Fp::invalid());
if (x1064 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x1061 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x1065 = x102 - x1064;
if (x1065 != 0) {
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/IsZeroU32/IsZero1/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1066 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x1066 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x1067 = x1061 * x1066;
// loc("cirgen/components/iszero.cpp":15:26)
auto x1068 = x1067 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x1068 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1069 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x1069 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Normalize/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1070 = args[2][87 * steps + ((cycle - 0) & mask)];
assert(x1070 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":97:10)
auto x1071 = x102 - x1070;
host_args.at(0) = x1007;
host_args.at(1) = x1011;
host_args.at(2) = x1019;
host_args.at(3) = x1023;
host_args.at(4) = x1064;
host_args.at(5) = x1069;
host_args.at(6) = x1071;
host(ctx, "log", " ALU output = %w, EQ:%u, LT:%u, LTU:%u", host_args.data(), 7, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x1072 = x824 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":45:25)
auto x1073 = x827 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x1074 = x1072 + x1073;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x1075 = x1074 + x830;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x1076 = (x1075 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1076);
reg = x1076;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x1077 = inv(x1075);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1077);
reg = x1077;
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1078 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x1078 != Fp::invalid());
if (x1078 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x1075 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x1079 = x102 - x1078;
if (x1079 != 0) {
// loc("Top/Mux/4/Mux/0/ComputeCycle/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1080 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x1080 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x1081 = x1075 * x1080;
// loc("cirgen/components/iszero.cpp":15:26)
auto x1082 = x1081 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x1082 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("cirgen/circuit/rv32im/compute.cpp":160:13)
auto x1083 = x603 + x85;
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg"("./cirgen/circuit/rv32im/rv32im.inl":38:68))
auto x1084 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x1084 != Fp::invalid());
if (x1084 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":38:68)
auto x1085 = x832 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":38:68)
if (x1085 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:38");
// loc("./cirgen/circuit/rv32im/rv32im.inl":38:68)
if (x821 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:38");
// loc("./cirgen/circuit/rv32im/rv32im.inl":38:68)
if (x797 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:38");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":23:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":24:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":25:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1086 = x1083 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1087 = Fp(x1086.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1087);
reg = x1087;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1088 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1088 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1089 = x1086 - x1088;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1090 = x1089 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1091 = Fp(x1090.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1091);
reg = x1091;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1092 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1092 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1093 = x1090 - x1092;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1094 = x1093 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1095 = Fp(x1094.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1095);
reg = x1095;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1096 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1096 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1097 = x1094 - x1096;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1098 = x1097 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1099 = Fp(x1098.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1099);
reg = x1099;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1100 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1100 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1101 = x1098 - x1100;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1102 = x1101 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1102);
reg = x1102;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1103 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1103 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1104 = x102 - x1103;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1105 = x1103 * x1104;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1105);
reg = x1105;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1106 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1106 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1107 = x99 - x1103;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1108 = x1106 * x1107;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1108 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1109 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1109 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":38:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1109);
reg = x1109;
}
if (x1079 != 0) {
host_args.at(0) = x1075;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":38:68)
auto x1110 = x1075 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1007);
reg = x1007;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1011);
reg = x1011;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1019);
reg = x1019;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1023);
reg = x1023;
}
{
host_args.at(0) = x1110;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1111 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1111 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1112 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1112 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1113 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1113 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1114 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1114 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1110);
reg = x1110;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x743);
reg = x743;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1111);
reg = x1111;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1112);
reg = x1112;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1113);
reg = x1113;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1114);
reg = x1114;
}
}
if (x1078 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg1"("./cirgen/circuit/rv32im/rv32im.inl":39:68))
auto x1115 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x1115 != Fp::invalid());
if (x1115 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":39:68)
auto x1116 = x832 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":39:68)
if (x1116 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:39");
// loc("./cirgen/circuit/rv32im/rv32im.inl":39:68)
if (x821 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:39");
// loc("./cirgen/circuit/rv32im/rv32im.inl":39:68)
auto x1117 = x797 - x68;
// loc("./cirgen/circuit/rv32im/rv32im.inl":39:68)
if (x1117 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:39");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1118 = x1083 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1119 = Fp(x1118.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1119);
reg = x1119;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1120 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1120 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1121 = x1118 - x1120;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1122 = x1121 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1123 = Fp(x1122.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1123);
reg = x1123;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1124 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1124 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1125 = x1122 - x1124;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1126 = x1125 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1127 = Fp(x1126.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1127);
reg = x1127;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1128 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1128 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1129 = x1126 - x1128;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1130 = x1129 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1131 = Fp(x1130.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1131);
reg = x1131;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1132 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1132 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1133 = x1130 - x1132;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1134 = x1133 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1134);
reg = x1134;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1135 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1135 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1136 = x102 - x1135;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1137 = x1135 * x1136;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1137);
reg = x1137;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1138 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1138 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1139 = x99 - x1135;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1140 = x1138 * x1139;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1140 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1141 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1141 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":39:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1141);
reg = x1141;
}
if (x1079 != 0) {
host_args.at(0) = x1075;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":39:68)
auto x1142 = x1075 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1007);
reg = x1007;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1011);
reg = x1011;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1019);
reg = x1019;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1023);
reg = x1023;
}
{
host_args.at(0) = x1142;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1143 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1143 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1144 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1144 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1145 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1145 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1146 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1146 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1142);
reg = x1142;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x743);
reg = x743;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1143);
reg = x1143;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1144);
reg = x1144;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1145);
reg = x1145;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1146);
reg = x1146;
}
}
if (x1078 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg2"("./cirgen/circuit/rv32im/rv32im.inl":40:69))
auto x1147 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x1147 != Fp::invalid());
if (x1147 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":40:69)
auto x1148 = x832 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":40:69)
if (x1148 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:40");
// loc("./cirgen/circuit/rv32im/rv32im.inl":40:69)
auto x1149 = x821 - x85;
// loc("./cirgen/circuit/rv32im/rv32im.inl":40:69)
if (x1149 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:40");
// loc("./cirgen/circuit/rv32im/rv32im.inl":40:69)
if (x797 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:40");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":43:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":44:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":45:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x57);
reg = x57;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1150 = x1083 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1151 = Fp(x1150.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1151);
reg = x1151;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1152 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1152 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1153 = x1150 - x1152;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1154 = x1153 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1155 = Fp(x1154.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1155);
reg = x1155;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1156 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1156 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1157 = x1154 - x1156;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1158 = x1157 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1159 = Fp(x1158.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1159);
reg = x1159;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1160 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1160 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1161 = x1158 - x1160;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1162 = x1161 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1163 = Fp(x1162.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1163);
reg = x1163;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1164 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1164 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1165 = x1162 - x1164;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1166 = x1165 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1166);
reg = x1166;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1167 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1167 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1168 = x102 - x1167;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1169 = x1167 * x1168;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1169);
reg = x1169;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1170 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1170 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1171 = x99 - x1167;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1172 = x1170 * x1171;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1172 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1173 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1173 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":40:69)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1173);
reg = x1173;
}
if (x1079 != 0) {
host_args.at(0) = x1075;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":40:69)
auto x1174 = x1075 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1007);
reg = x1007;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1011);
reg = x1011;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1019);
reg = x1019;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1023);
reg = x1023;
}
{
host_args.at(0) = x1174;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1175 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1175 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1176 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1176 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1177 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1177 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1178 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1178 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1174);
reg = x1174;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x743);
reg = x743;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1175);
reg = x1175;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1176);
reg = x1176;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1177);
reg = x1177;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1178);
reg = x1178;
}
}
if (x1078 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg3"("./cirgen/circuit/rv32im/rv32im.inl":41:69))
auto x1179 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x1179 != Fp::invalid());
if (x1179 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":41:69)
auto x1180 = x832 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":41:69)
if (x1180 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:41");
// loc("./cirgen/circuit/rv32im/rv32im.inl":41:69)
auto x1181 = x821 - x79;
// loc("./cirgen/circuit/rv32im/rv32im.inl":41:69)
if (x1181 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:41");
// loc("./cirgen/circuit/rv32im/rv32im.inl":41:69)
if (x797 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:41");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":38:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":39:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":40:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1182 = x1083 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1183 = Fp(x1182.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1183);
reg = x1183;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1184 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1184 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1185 = x1182 - x1184;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1186 = x1185 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1187 = Fp(x1186.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1187);
reg = x1187;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1188 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1188 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1189 = x1186 - x1188;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1190 = x1189 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1191 = Fp(x1190.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1191);
reg = x1191;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1192 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1192 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1193 = x1190 - x1192;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1194 = x1193 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1195 = Fp(x1194.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1195);
reg = x1195;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1196 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1196 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1197 = x1194 - x1196;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1198 = x1197 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1198);
reg = x1198;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1199 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1199 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1200 = x102 - x1199;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1201 = x1199 * x1200;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1201);
reg = x1201;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1202 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1202 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1203 = x99 - x1199;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1204 = x1202 * x1203;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1204 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1205 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1205 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":41:69)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1205);
reg = x1205;
}
if (x1079 != 0) {
host_args.at(0) = x1075;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":41:69)
auto x1206 = x1075 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1007);
reg = x1007;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1011);
reg = x1011;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1019);
reg = x1019;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1023);
reg = x1023;
}
{
host_args.at(0) = x1206;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1207 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1207 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1208 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1208 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1209 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1209 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1210 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1210 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1206);
reg = x1206;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x743);
reg = x743;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1207);
reg = x1207;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1208);
reg = x1208;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1209);
reg = x1209;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1210);
reg = x1210;
}
}
if (x1078 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg4"("./cirgen/circuit/rv32im/rv32im.inl":42:69))
auto x1211 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x1211 != Fp::invalid());
if (x1211 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":42:69)
auto x1212 = x832 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":42:69)
if (x1212 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:42");
// loc("./cirgen/circuit/rv32im/rv32im.inl":42:69)
auto x1213 = x821 - x78;
// loc("./cirgen/circuit/rv32im/rv32im.inl":42:69)
if (x1213 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:42");
// loc("./cirgen/circuit/rv32im/rv32im.inl":42:69)
if (x797 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:42");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":33:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":35:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1214 = x1083 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1215 = Fp(x1214.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1215);
reg = x1215;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1216 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1216 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1217 = x1214 - x1216;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1218 = x1217 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1219 = Fp(x1218.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1219);
reg = x1219;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1220 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1220 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1221 = x1218 - x1220;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1222 = x1221 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1223 = Fp(x1222.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1223);
reg = x1223;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1224 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1224 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1225 = x1222 - x1224;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1226 = x1225 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1227 = Fp(x1226.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1227);
reg = x1227;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1228 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1228 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1229 = x1226 - x1228;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1230 = x1229 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1230);
reg = x1230;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1231 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1231 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1232 = x102 - x1231;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1233 = x1231 * x1232;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1233);
reg = x1233;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1234 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1234 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1235 = x99 - x1231;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1236 = x1234 * x1235;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1236 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1237 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1237 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":42:69)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1237);
reg = x1237;
}
if (x1079 != 0) {
host_args.at(0) = x1075;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":42:69)
auto x1238 = x1075 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1007);
reg = x1007;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1011);
reg = x1011;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1019);
reg = x1019;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1023);
reg = x1023;
}
{
host_args.at(0) = x1238;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1239 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1239 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1240 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1240 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1241 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1241 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1242 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1242 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1238);
reg = x1238;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x743);
reg = x743;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1239);
reg = x1239;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1240);
reg = x1240;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1241);
reg = x1241;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1242);
reg = x1242;
}
}
if (x1078 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg5"("./cirgen/circuit/rv32im/rv32im.inl":43:68))
auto x1243 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x1243 != Fp::invalid());
if (x1243 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":43:68)
auto x1244 = x832 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":43:68)
if (x1244 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:43");
// loc("./cirgen/circuit/rv32im/rv32im.inl":43:68)
auto x1245 = x821 - x99;
// loc("./cirgen/circuit/rv32im/rv32im.inl":43:68)
if (x1245 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:43");
// loc("./cirgen/circuit/rv32im/rv32im.inl":43:68)
if (x797 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:43");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1246 = x1083 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1247 = Fp(x1246.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1247);
reg = x1247;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1248 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1248 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1249 = x1246 - x1248;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1250 = x1249 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1251 = Fp(x1250.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1251);
reg = x1251;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1252 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1252 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1253 = x1250 - x1252;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1254 = x1253 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1255 = Fp(x1254.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1255);
reg = x1255;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1256 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1256 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1257 = x1254 - x1256;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1258 = x1257 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1259 = Fp(x1258.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1259);
reg = x1259;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1260 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1260 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1261 = x1258 - x1260;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1262 = x1261 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1262);
reg = x1262;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1263 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1263 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1264 = x102 - x1263;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1265 = x1263 * x1264;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1265);
reg = x1265;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1266 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1266 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1267 = x99 - x1263;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1268 = x1266 * x1267;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1268 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1269 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1269 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":43:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1269);
reg = x1269;
}
if (x1079 != 0) {
host_args.at(0) = x1075;
host_args.at(1) = x1069;
host_args.at(2) = x101;
host_args.at(3) = x101;
host_args.at(4) = x101;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":43:68)
auto x1270 = x1075 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1069);
reg = x1069;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
{
host_args.at(0) = x1270;
host_args.at(1) = x1069;
host_args.at(2) = x101;
host_args.at(3) = x101;
host_args.at(4) = x101;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1271 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1271 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1272 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1272 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1273 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1273 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1274 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1274 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1270);
reg = x1270;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x743);
reg = x743;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1271);
reg = x1271;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1272);
reg = x1272;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1273);
reg = x1273;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1274);
reg = x1274;
}
}
if (x1078 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg6"("./cirgen/circuit/rv32im/rv32im.inl":44:68))
auto x1275 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x1275 != Fp::invalid());
if (x1275 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":44:68)
auto x1276 = x832 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":44:68)
if (x1276 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:44");
// loc("./cirgen/circuit/rv32im/rv32im.inl":44:68)
auto x1277 = x821 - x84;
// loc("./cirgen/circuit/rv32im/rv32im.inl":44:68)
if (x1277 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:44");
// loc("./cirgen/circuit/rv32im/rv32im.inl":44:68)
if (x797 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:44");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1278 = x1083 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1279 = Fp(x1278.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1279);
reg = x1279;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1280 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1280 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1281 = x1278 - x1280;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1282 = x1281 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1283 = Fp(x1282.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1283);
reg = x1283;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1284 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1284 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1285 = x1282 - x1284;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1286 = x1285 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1287 = Fp(x1286.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1287);
reg = x1287;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1288 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1288 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1289 = x1286 - x1288;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1290 = x1289 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1291 = Fp(x1290.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1291);
reg = x1291;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1292 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1292 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1293 = x1290 - x1292;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1294 = x1293 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1294);
reg = x1294;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1295 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1295 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1296 = x102 - x1295;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1297 = x1295 * x1296;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1297);
reg = x1297;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1298 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1298 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1299 = x99 - x1295;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1300 = x1298 * x1299;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1300 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1301 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1301 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":44:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1301);
reg = x1301;
}
if (x1079 != 0) {
host_args.at(0) = x1075;
host_args.at(1) = x1071;
host_args.at(2) = x101;
host_args.at(3) = x101;
host_args.at(4) = x101;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":44:68)
auto x1302 = x1075 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1071);
reg = x1071;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
{
host_args.at(0) = x1302;
host_args.at(1) = x1071;
host_args.at(2) = x101;
host_args.at(3) = x101;
host_args.at(4) = x101;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1303 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1303 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1304 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1304 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1305 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1305 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1306 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1306 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1302);
reg = x1302;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x743);
reg = x743;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1303);
reg = x1303;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1304);
reg = x1304;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1305);
reg = x1305;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1306);
reg = x1306;
}
}
if (x1078 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/OneHot/Reg7"("./cirgen/circuit/rv32im/rv32im.inl":45:68))
auto x1307 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x1307 != Fp::invalid());
if (x1307 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":45:68)
auto x1308 = x832 - x51;
// loc("./cirgen/circuit/rv32im/rv32im.inl":45:68)
if (x1308 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:45");
// loc("./cirgen/circuit/rv32im/rv32im.inl":45:68)
if (x821 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:45");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1309 = x792 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x1310 = x795 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1311 = x1309 + x1310;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1312 = x1311 + x904;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1313 = x785 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x1314 = x787 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1315 = x1313 + x1314;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1316 = x1315 + x789;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x1317 = x785 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1312);
reg = x1312;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1316);
reg = x1316;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1317);
reg = x1317;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1317);
reg = x1317;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":23:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":24:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":25:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1318 = x1083 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1319 = Fp(x1318.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1319);
reg = x1319;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1320 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1320 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1321 = x1318 - x1320;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1322 = x1321 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1323 = Fp(x1322.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1323);
reg = x1323;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1324 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1324 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1325 = x1322 - x1324;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1326 = x1325 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1327 = Fp(x1326.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1327);
reg = x1327;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1328 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1328 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1329 = x1326 - x1328;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1330 = x1329 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1331 = Fp(x1330.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1331);
reg = x1331;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1332 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1332 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1333 = x1330 - x1332;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1334 = x1333 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1334);
reg = x1334;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1335 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1335 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1336 = x102 - x1335;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1337 = x1335 * x1336;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1337);
reg = x1337;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1338 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1338 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1339 = x99 - x1335;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1340 = x1338 * x1339;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1340 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/0/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1341 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1341 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":45:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1341);
reg = x1341;
}
if (x1079 != 0) {
host_args.at(0) = x1075;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":45:68)
auto x1342 = x1075 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1007);
reg = x1007;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1011);
reg = x1011;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1019);
reg = x1019;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1023);
reg = x1023;
}
{
host_args.at(0) = x1342;
host_args.at(1) = x1007;
host_args.at(2) = x1011;
host_args.at(3) = x1019;
host_args.at(4) = x1023;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1343 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1343 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1344 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1344 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1345 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1345 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1346 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1346 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1342);
reg = x1342;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x743);
reg = x743;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1343);
reg = x1343;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1344);
reg = x1344;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1345);
reg = x1345;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1346);
reg = x1346;
}
}
if (x1078 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
}
// loc("Top/Mux/4/OneHot/Reg1"("./cirgen/components/mux.h":37:25))
auto x1347 = args[2][95 * steps + ((cycle - 0) & mask)];
assert(x1347 != Fp::invalid());
if (x1347 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1348 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x1348 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":112:41)
auto x1349 = x603 * x83;
{
host_args.at(0) = x1349;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x1350 = host_outs.at(0);
auto x1351 = host_outs.at(1);
auto x1352 = host_outs.at(2);
auto x1353 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1350);
reg = x1350;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1351);
reg = x1351;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1352);
reg = x1352;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1353);
reg = x1353;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1354 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x1354 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1355 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x1355 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1356 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x1356 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1357 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x1357 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1349);
reg = x1349;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1348);
reg = x1348;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1354);
reg = x1354;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1355);
reg = x1355;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1356);
reg = x1356;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1357);
reg = x1357;
}
{
// loc("cirgen/circuit/rv32im/decode.cpp":11:16)
auto x1358 = Fp(x1357.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":11:15)
auto x1359 = x1358 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1359);
reg = x1359;
}
// loc("cirgen/circuit/rv32im/decode.cpp":12:17)
auto x1360 = Fp(x1357.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":12:16)
auto x1361 = x1360 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1361);
reg = x1361;
}
// loc("cirgen/circuit/rv32im/decode.cpp":13:16)
auto x1362 = Fp(x1357.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":13:15)
auto x1363 = x1362 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1363);
reg = x1363;
}
// loc("cirgen/circuit/rv32im/decode.cpp":14:16)
auto x1364 = Fp(x1357.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":14:15)
auto x1365 = x1364 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1365);
reg = x1365;
}
// loc("cirgen/circuit/rv32im/decode.cpp":15:17)
auto x1366 = Fp(x1357.asUInt32() & x79.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":15:16)
auto x1367 = x1366 * x63;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][78 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1367);
reg = x1367;
}
// loc("cirgen/circuit/rv32im/decode.cpp":16:17)
auto x1368 = Fp(x1357.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1368);
reg = x1368;
}
// loc("cirgen/circuit/rv32im/decode.cpp":17:17)
auto x1369 = Fp(x1356.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":17:16)
auto x1370 = x1369 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1370);
reg = x1370;
}
// loc("cirgen/circuit/rv32im/decode.cpp":18:18)
auto x1371 = Fp(x1356.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":18:17)
auto x1372 = x1371 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1372);
reg = x1372;
}
// loc("cirgen/circuit/rv32im/decode.cpp":19:17)
auto x1373 = Fp(x1356.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":19:16)
auto x1374 = x1373 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1374);
reg = x1374;
}
// loc("cirgen/circuit/rv32im/decode.cpp":20:18)
auto x1375 = Fp(x1356.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":20:17)
auto x1376 = x1375 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1376);
reg = x1376;
}
// loc("cirgen/circuit/rv32im/decode.cpp":21:18)
auto x1377 = Fp(x1356.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1377);
reg = x1377;
}
// loc("cirgen/circuit/rv32im/decode.cpp":22:17)
auto x1378 = Fp(x1355.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":22:16)
auto x1379 = x1378 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1379);
reg = x1379;
}
// loc("cirgen/circuit/rv32im/decode.cpp":23:19)
auto x1380 = Fp(x1355.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":23:18)
auto x1381 = x1380 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1381);
reg = x1381;
}
// loc("cirgen/circuit/rv32im/decode.cpp":24:20)
auto x1382 = Fp(x1355.asUInt32() & x60.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":24:19)
auto x1383 = x1382 * x65;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1383);
reg = x1383;
}
// loc("cirgen/circuit/rv32im/decode.cpp":25:17)
auto x1384 = Fp(x1355.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":25:16)
auto x1385 = x1384 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1385);
reg = x1385;
}
// loc("cirgen/circuit/rv32im/decode.cpp":26:17)
auto x1386 = Fp(x1355.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1386);
reg = x1386;
}
// loc("cirgen/circuit/rv32im/decode.cpp":27:16)
auto x1387 = Fp(x1354.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":27:15)
auto x1388 = x1387 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][169 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1388);
reg = x1388;
}
// loc("cirgen/circuit/rv32im/decode.cpp":28:18)
auto x1389 = Fp(x1354.asUInt32() & x59.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":28:5)
{
auto& reg = args[2][170 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1389);
reg = x1389;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1390 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x1390 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x1391 = x1390 * x62;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1392 = args[2][79 * steps + ((cycle - 0) & mask)];
assert(x1392 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x1393 = x1392 * x66;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1394 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x1394 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:25)
auto x1395 = x1394 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x1396 = x1393 + x1395;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1397 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x1397 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:39)
auto x1398 = x1397 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x1399 = x1396 + x1398;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1400 = args[2][78 * steps + ((cycle - 0) & mask)];
assert(x1400 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x1401 = x1399 + x1400;
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x1402 = x1391 + x1401;
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x1403 = x1402 * x99;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1404 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x1404 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x1405 = x1403 + x1404;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
auto x1406 = x1357 - x1405;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
if (x1406 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:30");
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1407 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x1407 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x1408 = x1407 * x77;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Twit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1409 = args[2][80 * steps + ((cycle - 0) & mask)];
assert(x1409 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:37)
auto x1410 = x1409 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x1411 = x1408 + x1410;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1412 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x1412 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x1413 = x1411 + x1412;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x1414 = x1413 * x66;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Twit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1415 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x1415 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:69)
auto x1416 = x1415 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x1417 = x1414 + x1416;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Twit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1418 = args[2][81 * steps + ((cycle - 0) & mask)];
assert(x1418 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x1419 = x1417 + x1418;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
auto x1420 = x1356 - x1419;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
if (x1420 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:31");
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1421 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x1421 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x1422 = x1421 * x71;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1423 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x1423 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x1424 = x1423 * x85;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Twit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1425 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x1425 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x1426 = x1424 + x1425;
// loc("cirgen/circuit/rv32im/decode.cpp":32:36)
auto x1427 = x1426 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x1428 = x1422 + x1427;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1429 = args[2][85 * steps + ((cycle - 0) & mask)];
assert(x1429 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:53)
auto x1430 = x1429 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x1431 = x1428 + x1430;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1432 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x1432 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x1433 = x1431 + x1432;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
auto x1434 = x1355 - x1433;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
if (x1434 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:32");
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1435 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x1435 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x1436 = x1435 * x71;
// loc("Top/Mux/4/Mux/1/ComputeCycle/Decoder/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1437 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x1437 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x1438 = x1436 + x1437;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
auto x1439 = x1354 - x1438;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
if (x1439 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:33");
{
host_args.at(0) = x1354;
host_args.at(1) = x1355;
host_args.at(2) = x1356;
host_args.at(3) = x1357;
host(ctx, "getMinor", "", host_args.data(), 4, host_outs.data(), 1);
auto x1440 = host_outs.at(0);
{
// loc("./cirgen/components/onehot.h":35:26)
auto x1441 = (x1440 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][171 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1441);
reg = x1441;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x1442 = x1440 - x102;
// loc("./cirgen/components/onehot.h":35:26)
auto x1443 = (x1442 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][172 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1443);
reg = x1443;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x1444 = x1440 - x99;
// loc("./cirgen/components/onehot.h":35:26)
auto x1445 = (x1444 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1445);
reg = x1445;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x1446 = x1440 - x84;
// loc("./cirgen/components/onehot.h":35:26)
auto x1447 = (x1446 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][174 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1447);
reg = x1447;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x1448 = x1440 - x85;
// loc("./cirgen/components/onehot.h":35:26)
auto x1449 = (x1448 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][175 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1449);
reg = x1449;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x1450 = x1440 - x80;
// loc("./cirgen/components/onehot.h":35:26)
auto x1451 = (x1450 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1451);
reg = x1451;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x1452 = x1440 - x79;
// loc("./cirgen/components/onehot.h":35:26)
auto x1453 = (x1452 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1453);
reg = x1453;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x1454 = x1440 - x78;
// loc("./cirgen/components/onehot.h":35:26)
auto x1455 = (x1454 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1455);
reg = x1455;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1456 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x1456 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1457 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x1457 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x1458 = x1457 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x1459 = x1456 + x1458;
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1460 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x1460 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x1461 = x1460 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x1462 = x1459 + x1461;
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1463 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x1463 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x1464 = x1463 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x1465 = x1462 + x1464;
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1466 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x1466 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x1467 = x1466 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x1468 = x1465 + x1467;
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1469 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x1469 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x1470 = x1469 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x1471 = x1468 + x1470;
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1472 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x1472 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x1473 = x1472 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x1474 = x1471 + x1473;
// loc("./cirgen/components/onehot.h":38:8)
auto x1475 = x1474 - x1440;
// loc("./cirgen/components/onehot.h":38:8)
if (x1475 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
{
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg"("./cirgen/circuit/rv32im/rv32im.inl":46:69))
auto x1476 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x1476 != Fp::invalid());
if (x1476 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1477 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x1478 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1479 = x1477 + x1478;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1480 = x1404 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1481 = x1480 + x1413;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1482 = x1479 + x1481;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1483 = x1390 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x1484 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1485 = x1483 + x1484;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1486 = x1485 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x1487 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1482);
reg = x1482;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1486);
reg = x1486;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1487);
reg = x1487;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1487);
reg = x1487;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":43:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":44:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":45:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x57);
reg = x57;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg1"("./cirgen/circuit/rv32im/rv32im.inl":47:69))
auto x1488 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x1488 != Fp::invalid());
if (x1488 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1489 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x1490 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1491 = x1489 + x1490;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1492 = x1404 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1493 = x1492 + x1413;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1494 = x1491 + x1493;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1495 = x1390 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x1496 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1497 = x1495 + x1496;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1498 = x1497 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x1499 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1494);
reg = x1494;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1498);
reg = x1498;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1499);
reg = x1499;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1499);
reg = x1499;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":38:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":39:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":40:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg2"("./cirgen/circuit/rv32im/rv32im.inl":48:69))
auto x1500 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x1500 != Fp::invalid());
if (x1500 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1501 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x1502 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1503 = x1501 + x1502;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1504 = x1404 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1505 = x1504 + x1413;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1506 = x1503 + x1505;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1507 = x1390 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x1508 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1509 = x1507 + x1508;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1510 = x1509 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x1511 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1506);
reg = x1506;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1510);
reg = x1510;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1511);
reg = x1511;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1511);
reg = x1511;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":33:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":35:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg3"("./cirgen/circuit/rv32im/rv32im.inl":49:68))
auto x1512 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x1512 != Fp::invalid());
if (x1512 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1513 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x1514 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1515 = x1513 + x1514;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1516 = x1404 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1517 = x1516 + x1413;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1518 = x1515 + x1517;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1519 = x1390 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x1520 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1521 = x1519 + x1520;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1522 = x1521 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x1523 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1518);
reg = x1518;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1522);
reg = x1522;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1523);
reg = x1523;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1523);
reg = x1523;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg4"("./cirgen/circuit/rv32im/rv32im.inl":50:68))
auto x1524 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x1524 != Fp::invalid());
if (x1524 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1525 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x1526 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1527 = x1525 + x1526;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1528 = x1404 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1529 = x1528 + x1413;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1530 = x1527 + x1529;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1531 = x1390 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x1532 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1533 = x1531 + x1532;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1534 = x1533 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x1535 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1530);
reg = x1530;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1534);
reg = x1534;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1535);
reg = x1535;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1535);
reg = x1535;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg5"("./cirgen/circuit/rv32im/rv32im.inl":51:68))
auto x1536 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x1536 != Fp::invalid());
if (x1536 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1537 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x1538 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1539 = x1537 + x1538;
// loc("cirgen/circuit/rv32im/decode.cpp":88:36)
auto x1540 = x1429 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1541 = x1539 + x1540;
// loc("cirgen/circuit/rv32im/decode.cpp":88:51)
auto x1542 = x1432 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1543 = x1541 + x1542;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1544 = x1390 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x1545 = x1435 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1546 = x1544 + x1545;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x1547 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1548 = x1546 + x1547;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1549 = x1548 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x1550 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1543);
reg = x1543;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1549);
reg = x1549;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1550);
reg = x1550;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1550);
reg = x1550;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg6"("./cirgen/circuit/rv32im/rv32im.inl":52:68))
auto x1551 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x1551 != Fp::invalid());
if (x1551 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1552 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x1553 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1554 = x1552 + x1553;
// loc("cirgen/circuit/rv32im/decode.cpp":88:36)
auto x1555 = x1429 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1556 = x1554 + x1555;
// loc("cirgen/circuit/rv32im/decode.cpp":88:51)
auto x1557 = x1432 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1558 = x1556 + x1557;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1559 = x1390 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x1560 = x1435 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1561 = x1559 + x1560;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x1562 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1563 = x1561 + x1562;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1564 = x1563 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x1565 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1558);
reg = x1558;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1564);
reg = x1564;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1565);
reg = x1565;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1565);
reg = x1565;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg7"("./cirgen/circuit/rv32im/rv32im.inl":53:68))
auto x1566 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x1566 != Fp::invalid());
if (x1566 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1567 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x1568 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1569 = x1567 + x1568;
// loc("cirgen/circuit/rv32im/decode.cpp":88:36)
auto x1570 = x1429 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1571 = x1569 + x1570;
// loc("cirgen/circuit/rv32im/decode.cpp":88:51)
auto x1572 = x1432 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x1573 = x1571 + x1572;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1574 = x1390 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x1575 = x1435 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1576 = x1574 + x1575;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x1577 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1578 = x1576 + x1577;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x1579 = x1578 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x1580 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1573);
reg = x1573;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1579);
reg = x1579;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1580);
reg = x1580;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1580);
reg = x1580;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
}
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x1581 = x1415 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":37:26)
auto x1582 = x1418 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x1583 = x1581 + x1582;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x1584 = x1583 + x1421;
// loc("cirgen/circuit/rv32im/compute.cpp":134:39)
auto x1585 = x1584 + x55;
{
host_args.at(0) = x1585;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x1586 = host_outs.at(0);
auto x1587 = host_outs.at(1);
auto x1588 = host_outs.at(2);
auto x1589 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1586);
reg = x1586;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1587);
reg = x1587;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1588);
reg = x1588;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1589);
reg = x1589;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1590 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x1590 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1591 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x1591 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1592 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x1592 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1593 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x1593 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1585);
reg = x1585;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1348);
reg = x1348;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1590);
reg = x1590;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1591);
reg = x1591;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1592);
reg = x1592;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1593);
reg = x1593;
}
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1594 = x1404 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x1595 = x1594 + x1413;
// loc("cirgen/circuit/rv32im/compute.cpp":135:39)
auto x1596 = x1595 + x55;
{
host_args.at(0) = x1596;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x1597 = host_outs.at(0);
auto x1598 = host_outs.at(1);
auto x1599 = host_outs.at(2);
auto x1600 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1597);
reg = x1597;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1598);
reg = x1598;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1599);
reg = x1599;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1600);
reg = x1600;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1601 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x1601 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1602 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x1602 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1603 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x1603 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1604 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x1604 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1596);
reg = x1596;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1348);
reg = x1348;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1601);
reg = x1601;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1602);
reg = x1602;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1603);
reg = x1603;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1604);
reg = x1604;
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1605 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x1605 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1606 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x1606 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1607 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x1607 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1608 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x1608 != Fp::invalid());
host_args.at(0) = x1605;
host_args.at(1) = x1606;
host_args.at(2) = x1607;
host_args.at(3) = x1608;
host_args.at(4) = x1584;
host_args.at(5) = x1590;
host_args.at(6) = x1591;
host_args.at(7) = x1592;
host_args.at(8) = x1593;
host_args.at(9) = x1595;
host_args.at(10) = x1601;
host_args.at(11) = x1602;
host_args.at(12) = x1603;
host_args.at(13) = x1604;
host(ctx, "log", " imm=%w, rs1=x%u -> %w, rs2=x%u -> %w", host_args.data(), 14, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1609 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x1609 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":145:17)
auto x1610 = x102 - x1609;
// loc("cirgen/components/u32.cpp":105:20)
auto x1611 = x1610 * x1590;
// loc("cirgen/components/u32.cpp":105:20)
auto x1612 = x1610 * x1591;
// loc("cirgen/components/u32.cpp":105:20)
auto x1613 = x1610 * x1592;
// loc("cirgen/components/u32.cpp":105:20)
auto x1614 = x1610 * x1593;
// loc("cirgen/circuit/rv32im/body.cpp":35:52)
auto x1615 = x600 * x85;
// loc("cirgen/circuit/rv32im/body.cpp":35:41)
auto x1616 = x597 + x1615;
// loc("cirgen/components/u32.cpp":97:20)
auto x1617 = x590 - x85;
// loc("cirgen/components/u32.cpp":105:20)
auto x1618 = x1609 * x1617;
// loc("cirgen/components/u32.cpp":105:20)
auto x1619 = x1609 * x591;
// loc("cirgen/components/u32.cpp":105:20)
auto x1620 = x1609 * x594;
// loc("cirgen/components/u32.cpp":105:20)
auto x1621 = x1609 * x1616;
// loc("cirgen/components/u32.cpp":89:20)
auto x1622 = x1611 + x1618;
// loc("cirgen/components/u32.cpp":89:20)
auto x1623 = x1612 + x1619;
// loc("cirgen/components/u32.cpp":89:20)
auto x1624 = x1613 + x1620;
// loc("cirgen/components/u32.cpp":89:20)
auto x1625 = x1614 + x1621;
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1626 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x1626 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":147:17)
auto x1627 = x102 - x1626;
// loc("cirgen/components/u32.cpp":105:20)
auto x1628 = x1627 * x1601;
// loc("cirgen/components/u32.cpp":105:20)
auto x1629 = x1627 * x1602;
// loc("cirgen/components/u32.cpp":105:20)
auto x1630 = x1627 * x1603;
// loc("cirgen/components/u32.cpp":105:20)
auto x1631 = x1627 * x1604;
// loc("cirgen/components/u32.cpp":105:20)
auto x1632 = x1626 * x1605;
// loc("cirgen/components/u32.cpp":105:20)
auto x1633 = x1626 * x1606;
// loc("cirgen/components/u32.cpp":105:20)
auto x1634 = x1626 * x1607;
// loc("cirgen/components/u32.cpp":105:20)
auto x1635 = x1626 * x1608;
// loc("cirgen/components/u32.cpp":89:20)
auto x1636 = x1628 + x1632;
// loc("cirgen/components/u32.cpp":89:20)
auto x1637 = x1629 + x1633;
// loc("cirgen/components/u32.cpp":89:20)
auto x1638 = x1630 + x1634;
// loc("cirgen/components/u32.cpp":89:20)
auto x1639 = x1631 + x1635;
host_args.at(0) = x1622;
host_args.at(1) = x1623;
host_args.at(2) = x1624;
host_args.at(3) = x1625;
host_args.at(4) = x1636;
host_args.at(5) = x1637;
host_args.at(6) = x1638;
host_args.at(7) = x1639;
host(ctx, "log", " inA = %w, inB = %w", host_args.data(), 8, host_outs.data(), 0);
{
// loc("cirgen/components/u32.cpp":120:18)
auto x1640 = Fp(x1625.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x1641 = x1640 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1641);
reg = x1641;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x1642 = Fp(x1625.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x1643 = x1642 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1643);
reg = x1643;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/TopBit/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1644 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x1644 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x1645 = x1644 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x1646 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x1646 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x1647 = x1646 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x1648 = x1645 + x1647;
// loc("cirgen/components/u32.cpp":123:6)
auto x1649 = x1625 - x1648;
// loc("cirgen/components/u32.cpp":123:6)
if (x1649 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
{
// loc("cirgen/components/u32.cpp":120:18)
auto x1650 = Fp(x1639.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x1651 = x1650 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][190 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1651);
reg = x1651;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x1652 = Fp(x1639.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x1653 = x1652 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1653);
reg = x1653;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/TopBit1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1654 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x1654 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x1655 = x1654 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("cirgen/components/bytes.cpp":78:10))
auto x1656 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x1656 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x1657 = x1656 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x1658 = x1655 + x1657;
// loc("cirgen/components/u32.cpp":123:6)
auto x1659 = x1639 - x1658;
// loc("cirgen/components/u32.cpp":123:6)
if (x1659 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][191 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1636);
reg = x1636;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][192 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1637);
reg = x1637;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][193 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1638);
reg = x1638;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][194 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1639);
reg = x1639;
}
{
// loc("cirgen/components/u32.cpp":113:20)
auto x1660 = Fp(x1622.asUInt32() & x1636.asUInt32());
// loc("cirgen/components/u32.cpp":113:20)
auto x1661 = Fp(x1623.asUInt32() & x1637.asUInt32());
// loc("cirgen/components/u32.cpp":113:20)
auto x1662 = Fp(x1624.asUInt32() & x1638.asUInt32());
// loc("cirgen/components/u32.cpp":113:20)
auto x1663 = Fp(x1625.asUInt32() & x1639.asUInt32());
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][195 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1660);
reg = x1660;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][196 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1661);
reg = x1661;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][197 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1662);
reg = x1662;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][198 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1663);
reg = x1663;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1664 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x1664 != Fp::invalid());
// loc("cirgen/components/u32.cpp":105:20)
auto x1665 = x1664 * x1622;
// loc("cirgen/components/u32.cpp":105:20)
auto x1666 = x1664 * x1623;
// loc("cirgen/components/u32.cpp":105:20)
auto x1667 = x1664 * x1624;
// loc("cirgen/components/u32.cpp":105:20)
auto x1668 = x1664 * x1625;
// loc("cirgen/components/u32.cpp":89:20)
auto x1669 = x1665 + x97;
// loc("cirgen/components/u32.cpp":89:20)
auto x1670 = x1666 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x1671 = x1667 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x1672 = x1668 + x98;
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1673 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x1673 != Fp::invalid());
// loc("cirgen/components/u32.cpp":105:20)
auto x1674 = x1673 * x1636;
// loc("cirgen/components/u32.cpp":105:20)
auto x1675 = x1673 * x1637;
// loc("cirgen/components/u32.cpp":105:20)
auto x1676 = x1673 * x1638;
// loc("cirgen/components/u32.cpp":105:20)
auto x1677 = x1673 * x1639;
// loc("cirgen/components/u32.cpp":89:20)
auto x1678 = x1669 + x1674;
// loc("cirgen/components/u32.cpp":89:20)
auto x1679 = x1670 + x1675;
// loc("cirgen/components/u32.cpp":89:20)
auto x1680 = x1671 + x1676;
// loc("cirgen/components/u32.cpp":89:20)
auto x1681 = x1672 + x1677;
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg4"("./cirgen/compiler/edsl/component.h":85:27))
auto x1682 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x1682 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/U32Reg1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1683 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x1683 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/U32Reg1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1684 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x1684 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/U32Reg1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1685 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x1685 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/U32Reg1/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1686 = args[2][198 * steps + ((cycle - 0) & mask)];
assert(x1686 != Fp::invalid());
// loc("cirgen/components/u32.cpp":105:20)
auto x1687 = x1682 * x1683;
// loc("cirgen/components/u32.cpp":105:20)
auto x1688 = x1682 * x1684;
// loc("cirgen/components/u32.cpp":105:20)
auto x1689 = x1682 * x1685;
// loc("cirgen/components/u32.cpp":105:20)
auto x1690 = x1682 * x1686;
// loc("cirgen/components/u32.cpp":89:20)
auto x1691 = x1678 + x1687;
// loc("cirgen/components/u32.cpp":89:20)
auto x1692 = x1679 + x1688;
// loc("cirgen/components/u32.cpp":89:20)
auto x1693 = x1680 + x1689;
// loc("cirgen/components/u32.cpp":89:20)
auto x1694 = x1681 + x1690;
// loc("cirgen/components/u32.cpp":146:29)
auto x1695 = x1692 * x97;
// loc("cirgen/components/u32.cpp":146:15)
auto x1696 = x1691 + x1695;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1697 = Fp(x1696.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1697);
reg = x1697;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1698 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x1698 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1699 = x1696 - x1698;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1700 = x1699 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1701 = Fp(x1700.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1701);
reg = x1701;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1702 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x1702 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1703 = x1700 - x1702;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1704 = x1703 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1704);
reg = x1704;
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/U32Normalize/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1705 = args[2][86 * steps + ((cycle - 0) & mask)];
assert(x1705 != Fp::invalid());
// loc("cirgen/components/u32.cpp":148:16)
auto x1706 = x1705 + x1693;
// loc("cirgen/components/u32.cpp":148:41)
auto x1707 = x1694 * x97;
// loc("cirgen/components/u32.cpp":148:16)
auto x1708 = x1706 + x1707;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1709 = Fp(x1708.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1709);
reg = x1709;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1710 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x1710 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1711 = x1708 - x1710;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1712 = x1711 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1713 = Fp(x1712.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1713);
reg = x1713;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1714 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x1714 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1715 = x1712 - x1714;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1716 = x1715 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1716);
reg = x1716;
}
{
// loc("cirgen/components/u32.cpp":120:18)
auto x1717 = Fp(x1714.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x1718 = x1717 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][199 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1718);
reg = x1718;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x1719 = Fp(x1714.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x1720 = x1719 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1720);
reg = x1720;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/TopBit2/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1721 = args[2][199 * steps + ((cycle - 0) & mask)];
assert(x1721 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x1722 = x1721 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x1723 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x1723 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x1724 = x1723 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x1725 = x1722 + x1724;
// loc("cirgen/components/u32.cpp":123:6)
auto x1726 = x1714 - x1725;
// loc("cirgen/components/u32.cpp":123:6)
if (x1726 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
// loc("cirgen/circuit/rv32im/compute.cpp":69:23)
auto x1727 = x102 - x1654;
// loc("cirgen/circuit/rv32im/compute.cpp":69:17)
auto x1728 = x1644 * x1727;
// loc("cirgen/circuit/rv32im/compute.cpp":69:34)
auto x1729 = x102 - x1721;
// loc("cirgen/circuit/rv32im/compute.cpp":69:17)
auto x1730 = x1728 * x1729;
// loc("cirgen/circuit/rv32im/compute.cpp":69:45)
auto x1731 = x102 - x1644;
// loc("cirgen/circuit/rv32im/compute.cpp":69:44)
auto x1732 = x1731 * x1654;
// loc("cirgen/circuit/rv32im/compute.cpp":69:44)
auto x1733 = x1732 * x1721;
// loc("cirgen/circuit/rv32im/compute.cpp":69:17)
auto x1734 = x1730 + x1733;
// loc("cirgen/circuit/rv32im/compute.cpp":69:3)
{
auto& reg = args[2][200 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1734);
reg = x1734;
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1735 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x1735 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":71:11)
auto x1736 = x1735 + x1721;
// loc("cirgen/circuit/rv32im/compute.cpp":71:27)
auto x1737 = x1735 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":71:27)
auto x1738 = x1737 * x1721;
// loc("cirgen/circuit/rv32im/compute.cpp":71:11)
auto x1739 = x1736 - x1738;
// loc("cirgen/circuit/rv32im/compute.cpp":71:3)
{
auto& reg = args[2][201 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1739);
reg = x1739;
}
// loc("cirgen/components/u32.cpp":137:26)
auto x1740 = x1702 * x97;
// loc("cirgen/components/u32.cpp":137:12)
auto x1741 = x1698 + x1740;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x1742 = (x1741 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][202 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1742);
reg = x1742;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x1743 = inv(x1741);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][203 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1743);
reg = x1743;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/IsZeroU32/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1744 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x1744 != Fp::invalid());
if (x1744 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x1741 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x1745 = x102 - x1744;
if (x1745 != 0) {
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/IsZeroU32/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1746 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x1746 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x1747 = x1741 * x1746;
// loc("cirgen/components/iszero.cpp":15:26)
auto x1748 = x1747 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x1748 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("cirgen/components/u32.cpp":138:27)
auto x1749 = x1714 * x97;
// loc("cirgen/components/u32.cpp":138:13)
auto x1750 = x1710 + x1749;
// loc("cirgen/components/u32.cpp":138:47)
auto x1751 = x1745 * x87;
// loc("cirgen/components/u32.cpp":138:13)
auto x1752 = x1750 + x1751;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x1753 = (x1752 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1753);
reg = x1753;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x1754 = inv(x1752);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1754);
reg = x1754;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/IsZeroU32/IsZero1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1755 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x1755 != Fp::invalid());
if (x1755 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x1752 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x1756 = x102 - x1755;
if (x1756 != 0) {
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/IsZeroU32/IsZero1/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1757 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x1757 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x1758 = x1752 * x1757;
// loc("cirgen/components/iszero.cpp":15:26)
auto x1759 = x1758 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x1759 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1760 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x1760 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/ALU/U32Normalize/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1761 = args[2][87 * steps + ((cycle - 0) & mask)];
assert(x1761 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":97:10)
auto x1762 = x102 - x1761;
host_args.at(0) = x1698;
host_args.at(1) = x1702;
host_args.at(2) = x1710;
host_args.at(3) = x1714;
host_args.at(4) = x1755;
host_args.at(5) = x1760;
host_args.at(6) = x1762;
host(ctx, "log", " ALU output = %w, EQ:%u, LT:%u, LTU:%u", host_args.data(), 7, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x1763 = x1429 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":45:25)
auto x1764 = x1432 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x1765 = x1763 + x1764;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x1766 = x1765 + x1435;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x1767 = (x1766 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1767);
reg = x1767;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x1768 = inv(x1766);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1768);
reg = x1768;
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1769 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x1769 != Fp::invalid());
if (x1769 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x1766 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x1770 = x102 - x1769;
if (x1770 != 0) {
// loc("Top/Mux/4/Mux/1/ComputeCycle/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1771 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x1771 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x1772 = x1766 * x1771;
// loc("cirgen/components/iszero.cpp":15:26)
auto x1773 = x1772 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x1773 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("cirgen/circuit/rv32im/compute.cpp":160:13)
auto x1774 = x603 + x85;
// loc("cirgen/components/u32.cpp":62:25)
auto x1775 = x1606 * x97;
// loc("cirgen/components/u32.cpp":62:13)
auto x1776 = x1605 + x1775;
// loc("cirgen/components/u32.cpp":62:49)
auto x1777 = x1607 * x87;
// loc("cirgen/components/u32.cpp":62:13)
auto x1778 = x1776 + x1777;
// loc("cirgen/components/u32.cpp":65:17)
auto x1779 = x1608 * x54;
// loc("cirgen/components/u32.cpp":65:16)
auto x1780 = x1779 * x53;
// loc("cirgen/components/u32.cpp":65:10)
auto x1781 = x1778 + x1780;
// loc("cirgen/circuit/rv32im/compute.cpp":161:14)
auto x1782 = x603 + x1781;
// loc("cirgen/circuit/rv32im/compute.cpp":168:13)
auto x1783 = x1755 * x1782;
// loc("cirgen/circuit/rv32im/compute.cpp":168:35)
auto x1784 = x1756 * x1774;
// loc("cirgen/circuit/rv32im/compute.cpp":168:13)
auto x1785 = x1783 + x1784;
// loc("cirgen/circuit/rv32im/compute.cpp":169:13)
auto x1786 = x1755 * x1774;
// loc("cirgen/circuit/rv32im/compute.cpp":169:34)
auto x1787 = x1756 * x1782;
// loc("cirgen/circuit/rv32im/compute.cpp":169:13)
auto x1788 = x1786 + x1787;
// loc("cirgen/circuit/rv32im/compute.cpp":170:13)
auto x1789 = x1760 * x1782;
// loc("cirgen/circuit/rv32im/compute.cpp":170:36)
auto x1790 = x102 - x1760;
// loc("cirgen/circuit/rv32im/compute.cpp":170:35)
auto x1791 = x1790 * x1774;
// loc("cirgen/circuit/rv32im/compute.cpp":170:13)
auto x1792 = x1789 + x1791;
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg"("./cirgen/circuit/rv32im/rv32im.inl":46:69))
auto x1793 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x1793 != Fp::invalid());
if (x1793 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":46:69)
auto x1794 = x1437 - x51;
// loc("./cirgen/circuit/rv32im/rv32im.inl":46:69)
if (x1794 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:46");
// loc("./cirgen/circuit/rv32im/rv32im.inl":46:69)
auto x1795 = x1426 - x85;
// loc("./cirgen/circuit/rv32im/rv32im.inl":46:69)
if (x1795 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:46");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1796 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x1797 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1798 = x1796 + x1797;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1799 = x1798 + x1595;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1800 = x1390 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x1801 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1802 = x1800 + x1801;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1803 = x1802 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x1804 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1799);
reg = x1799;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1803);
reg = x1803;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1804);
reg = x1804;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1804);
reg = x1804;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":43:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":44:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":45:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x57);
reg = x57;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1805 = x1774 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1806 = Fp(x1805.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1806);
reg = x1806;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1807 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1807 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1808 = x1805 - x1807;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1809 = x1808 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1810 = Fp(x1809.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1810);
reg = x1810;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1811 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1811 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1812 = x1809 - x1811;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1813 = x1812 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1814 = Fp(x1813.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1814);
reg = x1814;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1815 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1815 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1816 = x1813 - x1815;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1817 = x1816 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1818 = Fp(x1817.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1818);
reg = x1818;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1819 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1819 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1820 = x1817 - x1819;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1821 = x1820 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1821);
reg = x1821;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1822 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1822 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1823 = x102 - x1822;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1824 = x1822 * x1823;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1824);
reg = x1824;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1825 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1825 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1826 = x99 - x1822;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1827 = x1825 * x1826;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1827 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1828 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1828 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":46:69)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1828);
reg = x1828;
}
if (x1770 != 0) {
host_args.at(0) = x1766;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":46:69)
auto x1829 = x1766 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1698);
reg = x1698;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1702);
reg = x1702;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1710);
reg = x1710;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1714);
reg = x1714;
}
{
host_args.at(0) = x1829;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1830 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1830 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1831 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1831 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1832 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1832 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1833 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1833 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1829);
reg = x1829;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1348);
reg = x1348;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1830);
reg = x1830;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1831);
reg = x1831;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1832);
reg = x1832;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1833);
reg = x1833;
}
}
if (x1769 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg1"("./cirgen/circuit/rv32im/rv32im.inl":47:69))
auto x1834 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x1834 != Fp::invalid());
if (x1834 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":47:69)
auto x1835 = x1437 - x51;
// loc("./cirgen/circuit/rv32im/rv32im.inl":47:69)
if (x1835 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:47");
// loc("./cirgen/circuit/rv32im/rv32im.inl":47:69)
auto x1836 = x1426 - x79;
// loc("./cirgen/circuit/rv32im/rv32im.inl":47:69)
if (x1836 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:47");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1837 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x1838 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1839 = x1837 + x1838;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1840 = x1839 + x1595;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1841 = x1390 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x1842 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1843 = x1841 + x1842;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1844 = x1843 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x1845 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1840);
reg = x1840;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1844);
reg = x1844;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1845);
reg = x1845;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1845);
reg = x1845;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":38:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":39:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":40:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1846 = x1774 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1847 = Fp(x1846.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1847);
reg = x1847;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1848 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1848 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1849 = x1846 - x1848;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1850 = x1849 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1851 = Fp(x1850.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1851);
reg = x1851;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1852 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1852 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1853 = x1850 - x1852;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1854 = x1853 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1855 = Fp(x1854.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1855);
reg = x1855;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1856 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1856 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1857 = x1854 - x1856;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1858 = x1857 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1859 = Fp(x1858.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1859);
reg = x1859;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1860 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1860 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1861 = x1858 - x1860;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1862 = x1861 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1862);
reg = x1862;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1863 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1863 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1864 = x102 - x1863;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1865 = x1863 * x1864;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1865);
reg = x1865;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1866 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1866 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1867 = x99 - x1863;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1868 = x1866 * x1867;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1868 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1869 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1869 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":47:69)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1869);
reg = x1869;
}
if (x1770 != 0) {
host_args.at(0) = x1766;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":47:69)
auto x1870 = x1766 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1698);
reg = x1698;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1702);
reg = x1702;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1710);
reg = x1710;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1714);
reg = x1714;
}
{
host_args.at(0) = x1870;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1871 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1871 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1872 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1872 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1873 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1873 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1874 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1874 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1870);
reg = x1870;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1348);
reg = x1348;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1871);
reg = x1871;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1872);
reg = x1872;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1873);
reg = x1873;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1874);
reg = x1874;
}
}
if (x1769 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg2"("./cirgen/circuit/rv32im/rv32im.inl":48:69))
auto x1875 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x1875 != Fp::invalid());
if (x1875 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":48:69)
auto x1876 = x1437 - x51;
// loc("./cirgen/circuit/rv32im/rv32im.inl":48:69)
if (x1876 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:48");
// loc("./cirgen/circuit/rv32im/rv32im.inl":48:69)
auto x1877 = x1426 - x78;
// loc("./cirgen/circuit/rv32im/rv32im.inl":48:69)
if (x1877 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:48");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1878 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x1879 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1880 = x1878 + x1879;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1881 = x1880 + x1595;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1882 = x1390 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x1883 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1884 = x1882 + x1883;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1885 = x1884 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x1886 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1881);
reg = x1881;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1885);
reg = x1885;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1886);
reg = x1886;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1886);
reg = x1886;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":33:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":35:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x79);
reg = x79;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1887 = x1774 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1888 = Fp(x1887.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1888);
reg = x1888;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1889 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1889 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1890 = x1887 - x1889;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1891 = x1890 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1892 = Fp(x1891.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1892);
reg = x1892;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1893 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1893 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1894 = x1891 - x1893;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1895 = x1894 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1896 = Fp(x1895.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1896);
reg = x1896;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1897 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1897 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1898 = x1895 - x1897;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1899 = x1898 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1900 = Fp(x1899.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1900);
reg = x1900;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1901 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1901 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1902 = x1899 - x1901;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1903 = x1902 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1903);
reg = x1903;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1904 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1904 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1905 = x102 - x1904;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1906 = x1904 * x1905;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1906);
reg = x1906;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1907 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1907 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1908 = x99 - x1904;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1909 = x1907 * x1908;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1909 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1910 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1910 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":48:69)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1910);
reg = x1910;
}
if (x1770 != 0) {
host_args.at(0) = x1766;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":48:69)
auto x1911 = x1766 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1698);
reg = x1698;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1702);
reg = x1702;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1710);
reg = x1710;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1714);
reg = x1714;
}
{
host_args.at(0) = x1911;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1912 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1912 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1913 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1913 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1914 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1914 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1915 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1915 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1911);
reg = x1911;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1348);
reg = x1348;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1912);
reg = x1912;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1913);
reg = x1913;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1914);
reg = x1914;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1915);
reg = x1915;
}
}
if (x1769 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg3"("./cirgen/circuit/rv32im/rv32im.inl":49:68))
auto x1916 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x1916 != Fp::invalid());
if (x1916 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":49:68)
auto x1917 = x1437 - x51;
// loc("./cirgen/circuit/rv32im/rv32im.inl":49:68)
if (x1917 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:49");
// loc("./cirgen/circuit/rv32im/rv32im.inl":49:68)
auto x1918 = x1426 - x99;
// loc("./cirgen/circuit/rv32im/rv32im.inl":49:68)
if (x1918 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:49");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1919 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x1920 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1921 = x1919 + x1920;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1922 = x1921 + x1595;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1923 = x1390 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x1924 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1925 = x1923 + x1924;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1926 = x1925 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x1927 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1922);
reg = x1922;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1926);
reg = x1926;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1927);
reg = x1927;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1927);
reg = x1927;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1928 = x1774 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1929 = Fp(x1928.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1929);
reg = x1929;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1930 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1930 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1931 = x1928 - x1930;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1932 = x1931 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1933 = Fp(x1932.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1933);
reg = x1933;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1934 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1934 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1935 = x1932 - x1934;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1936 = x1935 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1937 = Fp(x1936.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1937);
reg = x1937;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1938 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1938 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1939 = x1936 - x1938;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1940 = x1939 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1941 = Fp(x1940.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1941);
reg = x1941;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1942 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1942 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1943 = x1940 - x1942;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1944 = x1943 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1944);
reg = x1944;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1945 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1945 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1946 = x102 - x1945;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1947 = x1945 * x1946;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1947);
reg = x1947;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1948 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1948 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1949 = x99 - x1945;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1950 = x1948 * x1949;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1950 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1951 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1951 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":49:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1951);
reg = x1951;
}
if (x1770 != 0) {
host_args.at(0) = x1766;
host_args.at(1) = x1760;
host_args.at(2) = x101;
host_args.at(3) = x101;
host_args.at(4) = x101;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":49:68)
auto x1952 = x1766 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1760);
reg = x1760;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
{
host_args.at(0) = x1952;
host_args.at(1) = x1760;
host_args.at(2) = x101;
host_args.at(3) = x101;
host_args.at(4) = x101;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1953 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1953 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1954 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1954 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1955 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1955 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1956 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1956 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1952);
reg = x1952;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1348);
reg = x1348;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1953);
reg = x1953;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1954);
reg = x1954;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1955);
reg = x1955;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1956);
reg = x1956;
}
}
if (x1769 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg4"("./cirgen/circuit/rv32im/rv32im.inl":50:68))
auto x1957 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x1957 != Fp::invalid());
if (x1957 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":50:68)
auto x1958 = x1437 - x51;
// loc("./cirgen/circuit/rv32im/rv32im.inl":50:68)
if (x1958 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:50");
// loc("./cirgen/circuit/rv32im/rv32im.inl":50:68)
auto x1959 = x1426 - x84;
// loc("./cirgen/circuit/rv32im/rv32im.inl":50:68)
if (x1959 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:50");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1960 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x1961 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1962 = x1960 + x1961;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x1963 = x1962 + x1595;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1964 = x1390 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x1965 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1966 = x1964 + x1965;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x1967 = x1966 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x1968 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1963);
reg = x1963;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1967);
reg = x1967;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1968);
reg = x1968;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1968);
reg = x1968;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x1969 = x1774 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1970 = Fp(x1969.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1970);
reg = x1970;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1971 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x1971 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1972 = x1969 - x1971;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1973 = x1972 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1974 = Fp(x1973.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1974);
reg = x1974;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x1975 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x1975 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1976 = x1973 - x1975;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1977 = x1976 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x1978 = Fp(x1977.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1978);
reg = x1978;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x1979 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x1979 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x1980 = x1977 - x1979;
// loc("cirgen/components/bytes.cpp":83:10)
auto x1981 = x1980 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x1982 = Fp(x1981.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1982);
reg = x1982;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1983 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x1983 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x1984 = x1981 - x1983;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x1985 = x1984 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1985);
reg = x1985;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1986 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x1986 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x1987 = x102 - x1986;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x1988 = x1986 * x1987;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1988);
reg = x1988;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x1989 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x1989 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x1990 = x99 - x1986;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x1991 = x1989 * x1990;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x1991 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x1992 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x1992 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":50:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1992);
reg = x1992;
}
if (x1770 != 0) {
host_args.at(0) = x1766;
host_args.at(1) = x1762;
host_args.at(2) = x101;
host_args.at(3) = x101;
host_args.at(4) = x101;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":50:68)
auto x1993 = x1766 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1762);
reg = x1762;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
{
host_args.at(0) = x1993;
host_args.at(1) = x1762;
host_args.at(2) = x101;
host_args.at(3) = x101;
host_args.at(4) = x101;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x1994 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x1994 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x1995 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x1995 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x1996 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x1996 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x1997 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x1997 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1993);
reg = x1993;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1348);
reg = x1348;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1994);
reg = x1994;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1995);
reg = x1995;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1996);
reg = x1996;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1997);
reg = x1997;
}
}
if (x1769 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg5"("./cirgen/circuit/rv32im/rv32im.inl":51:68))
auto x1998 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x1998 != Fp::invalid());
if (x1998 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":51:68)
auto x1999 = x1437 - x49;
// loc("./cirgen/circuit/rv32im/rv32im.inl":51:68)
if (x1999 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:51");
// loc("./cirgen/circuit/rv32im/rv32im.inl":51:68)
if (x1426 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:51");
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2000 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x2001 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2002 = x2000 + x2001;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2003 = x2002 + x1763;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2004 = x2003 + x1764;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2005 = x1390 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x2006 = x1435 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2007 = x2005 + x2006;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x2008 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2009 = x2007 + x2008;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2010 = x2009 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x2011 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2004);
reg = x2004;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2010);
reg = x2010;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2011);
reg = x2011;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2011);
reg = x2011;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x2012 = x1785 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2013 = Fp(x2012.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2013);
reg = x2013;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2014 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x2014 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2015 = x2012 - x2014;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2016 = x2015 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2017 = Fp(x2016.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2017);
reg = x2017;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2018 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x2018 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2019 = x2016 - x2018;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2020 = x2019 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2021 = Fp(x2020.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2021);
reg = x2021;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2022 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x2022 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2023 = x2020 - x2022;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2024 = x2023 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x2025 = Fp(x2024.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2025);
reg = x2025;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2026 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x2026 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x2027 = x2024 - x2026;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x2028 = x2027 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2028);
reg = x2028;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2029 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x2029 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x2030 = x102 - x2029;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x2031 = x2029 * x2030;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2031);
reg = x2031;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2032 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x2032 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x2033 = x99 - x2029;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x2034 = x2032 * x2033;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x2034 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x2035 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x2035 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":51:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2035);
reg = x2035;
}
if (x101 != 0) {
host_args.at(0) = x1766;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":51:68)
auto x2036 = x1766 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1698);
reg = x1698;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1702);
reg = x1702;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1710);
reg = x1710;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1714);
reg = x1714;
}
{
host_args.at(0) = x2036;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2037 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x2037 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2038 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x2038 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2039 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x2039 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2040 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x2040 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2036);
reg = x2036;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1348);
reg = x1348;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2037);
reg = x2037;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2038);
reg = x2038;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2039);
reg = x2039;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2040);
reg = x2040;
}
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":51:68)
auto x2041 = x1769 + x102;
if (x2041 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg6"("./cirgen/circuit/rv32im/rv32im.inl":52:68))
auto x2042 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x2042 != Fp::invalid());
if (x2042 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":52:68)
auto x2043 = x1437 - x49;
// loc("./cirgen/circuit/rv32im/rv32im.inl":52:68)
if (x2043 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:52");
// loc("./cirgen/circuit/rv32im/rv32im.inl":52:68)
auto x2044 = x1426 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":52:68)
if (x2044 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:52");
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2045 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x2046 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2047 = x2045 + x2046;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2048 = x2047 + x1763;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2049 = x2048 + x1764;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2050 = x1390 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x2051 = x1435 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2052 = x2050 + x2051;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x2053 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2054 = x2052 + x2053;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2055 = x2054 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x2056 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2049);
reg = x2049;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2055);
reg = x2055;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2056);
reg = x2056;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2056);
reg = x2056;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x2057 = x1788 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2058 = Fp(x2057.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2058);
reg = x2058;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2059 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x2059 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2060 = x2057 - x2059;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2061 = x2060 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2062 = Fp(x2061.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2062);
reg = x2062;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2063 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x2063 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2064 = x2061 - x2063;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2065 = x2064 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2066 = Fp(x2065.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2066);
reg = x2066;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2067 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x2067 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2068 = x2065 - x2067;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2069 = x2068 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x2070 = Fp(x2069.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2070);
reg = x2070;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2071 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x2071 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x2072 = x2069 - x2071;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x2073 = x2072 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2073);
reg = x2073;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2074 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x2074 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x2075 = x102 - x2074;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x2076 = x2074 * x2075;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2076);
reg = x2076;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2077 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x2077 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x2078 = x99 - x2074;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x2079 = x2077 * x2078;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x2079 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x2080 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x2080 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":52:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2080);
reg = x2080;
}
if (x101 != 0) {
host_args.at(0) = x1766;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":52:68)
auto x2081 = x1766 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1698);
reg = x1698;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1702);
reg = x1702;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1710);
reg = x1710;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1714);
reg = x1714;
}
{
host_args.at(0) = x2081;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2082 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x2082 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2083 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x2083 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2084 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x2084 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2085 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x2085 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2081);
reg = x2081;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1348);
reg = x1348;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2082);
reg = x2082;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2083);
reg = x2083;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2084);
reg = x2084;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2085);
reg = x2085;
}
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":52:68)
auto x2086 = x1769 + x102;
if (x2086 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/OneHot/Reg7"("./cirgen/circuit/rv32im/rv32im.inl":53:68))
auto x2087 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x2087 != Fp::invalid());
if (x2087 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":53:68)
auto x2088 = x1437 - x49;
// loc("./cirgen/circuit/rv32im/rv32im.inl":53:68)
if (x2088 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:53");
// loc("./cirgen/circuit/rv32im/rv32im.inl":53:68)
auto x2089 = x1426 - x85;
// loc("./cirgen/circuit/rv32im/rv32im.inl":53:68)
if (x2089 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:53");
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2090 = x1397 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x2091 = x1400 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2092 = x2090 + x2091;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2093 = x2092 + x1763;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2094 = x2093 + x1764;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2095 = x1390 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x2096 = x1435 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2097 = x2095 + x2096;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x2098 = x1392 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2099 = x2097 + x2098;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2100 = x2099 + x1394;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x2101 = x1390 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2094);
reg = x2094;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2100);
reg = x2100;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2101);
reg = x2101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2101);
reg = x2101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x2102 = x1792 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2103 = Fp(x2102.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2103);
reg = x2103;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2104 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x2104 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2105 = x2102 - x2104;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2106 = x2105 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2107 = Fp(x2106.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2107);
reg = x2107;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2108 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x2108 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2109 = x2106 - x2108;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2110 = x2109 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2111 = Fp(x2110.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2111);
reg = x2111;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2112 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x2112 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2113 = x2110 - x2112;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2114 = x2113 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x2115 = Fp(x2114.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2115);
reg = x2115;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2116 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x2116 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x2117 = x2114 - x2116;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x2118 = x2117 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2118);
reg = x2118;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2119 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x2119 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x2120 = x102 - x2119;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x2121 = x2119 * x2120;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2121);
reg = x2121;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2122 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x2122 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x2123 = x99 - x2119;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x2124 = x2122 * x2123;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x2124 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/1/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x2125 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x2125 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":53:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2125);
reg = x2125;
}
if (x101 != 0) {
host_args.at(0) = x1766;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":53:68)
auto x2126 = x1766 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1698);
reg = x1698;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1702);
reg = x1702;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1710);
reg = x1710;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1714);
reg = x1714;
}
{
host_args.at(0) = x2126;
host_args.at(1) = x1698;
host_args.at(2) = x1702;
host_args.at(3) = x1710;
host_args.at(4) = x1714;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2127 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x2127 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2128 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x2128 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2129 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x2129 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2130 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x2130 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2126);
reg = x2126;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x1348);
reg = x1348;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2127);
reg = x2127;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2128);
reg = x2128;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2129);
reg = x2129;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2130);
reg = x2130;
}
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":53:68)
auto x2131 = x1769 + x102;
if (x2131 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
}
// loc("Top/Mux/4/OneHot/Reg2"("./cirgen/components/mux.h":37:25))
auto x2132 = args[2][96 * steps + ((cycle - 0) & mask)];
assert(x2132 != Fp::invalid());
if (x2132 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2133 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x2133 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":112:41)
auto x2134 = x603 * x83;
{
host_args.at(0) = x2134;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x2135 = host_outs.at(0);
auto x2136 = host_outs.at(1);
auto x2137 = host_outs.at(2);
auto x2138 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2135);
reg = x2135;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2136);
reg = x2136;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2137);
reg = x2137;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2138);
reg = x2138;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2139 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x2139 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2140 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x2140 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2141 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x2141 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2142 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x2142 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2134);
reg = x2134;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2133);
reg = x2133;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2139);
reg = x2139;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2140);
reg = x2140;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2141);
reg = x2141;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2142);
reg = x2142;
}
{
// loc("cirgen/circuit/rv32im/decode.cpp":11:16)
auto x2143 = Fp(x2142.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":11:15)
auto x2144 = x2143 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2144);
reg = x2144;
}
// loc("cirgen/circuit/rv32im/decode.cpp":12:17)
auto x2145 = Fp(x2142.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":12:16)
auto x2146 = x2145 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2146);
reg = x2146;
}
// loc("cirgen/circuit/rv32im/decode.cpp":13:16)
auto x2147 = Fp(x2142.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":13:15)
auto x2148 = x2147 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2148);
reg = x2148;
}
// loc("cirgen/circuit/rv32im/decode.cpp":14:16)
auto x2149 = Fp(x2142.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":14:15)
auto x2150 = x2149 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2150);
reg = x2150;
}
// loc("cirgen/circuit/rv32im/decode.cpp":15:17)
auto x2151 = Fp(x2142.asUInt32() & x79.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":15:16)
auto x2152 = x2151 * x63;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][78 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2152);
reg = x2152;
}
// loc("cirgen/circuit/rv32im/decode.cpp":16:17)
auto x2153 = Fp(x2142.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2153);
reg = x2153;
}
// loc("cirgen/circuit/rv32im/decode.cpp":17:17)
auto x2154 = Fp(x2141.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":17:16)
auto x2155 = x2154 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2155);
reg = x2155;
}
// loc("cirgen/circuit/rv32im/decode.cpp":18:18)
auto x2156 = Fp(x2141.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":18:17)
auto x2157 = x2156 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2157);
reg = x2157;
}
// loc("cirgen/circuit/rv32im/decode.cpp":19:17)
auto x2158 = Fp(x2141.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":19:16)
auto x2159 = x2158 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2159);
reg = x2159;
}
// loc("cirgen/circuit/rv32im/decode.cpp":20:18)
auto x2160 = Fp(x2141.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":20:17)
auto x2161 = x2160 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2161);
reg = x2161;
}
// loc("cirgen/circuit/rv32im/decode.cpp":21:18)
auto x2162 = Fp(x2141.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2162);
reg = x2162;
}
// loc("cirgen/circuit/rv32im/decode.cpp":22:17)
auto x2163 = Fp(x2140.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":22:16)
auto x2164 = x2163 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2164);
reg = x2164;
}
// loc("cirgen/circuit/rv32im/decode.cpp":23:19)
auto x2165 = Fp(x2140.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":23:18)
auto x2166 = x2165 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2166);
reg = x2166;
}
// loc("cirgen/circuit/rv32im/decode.cpp":24:20)
auto x2167 = Fp(x2140.asUInt32() & x60.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":24:19)
auto x2168 = x2167 * x65;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2168);
reg = x2168;
}
// loc("cirgen/circuit/rv32im/decode.cpp":25:17)
auto x2169 = Fp(x2140.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":25:16)
auto x2170 = x2169 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2170);
reg = x2170;
}
// loc("cirgen/circuit/rv32im/decode.cpp":26:17)
auto x2171 = Fp(x2140.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2171);
reg = x2171;
}
// loc("cirgen/circuit/rv32im/decode.cpp":27:16)
auto x2172 = Fp(x2139.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":27:15)
auto x2173 = x2172 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][169 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2173);
reg = x2173;
}
// loc("cirgen/circuit/rv32im/decode.cpp":28:18)
auto x2174 = Fp(x2139.asUInt32() & x59.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":28:5)
{
auto& reg = args[2][170 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2174);
reg = x2174;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2175 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x2175 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x2176 = x2175 * x62;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2177 = args[2][79 * steps + ((cycle - 0) & mask)];
assert(x2177 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x2178 = x2177 * x66;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2179 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x2179 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:25)
auto x2180 = x2179 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x2181 = x2178 + x2180;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2182 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x2182 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:39)
auto x2183 = x2182 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x2184 = x2181 + x2183;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2185 = args[2][78 * steps + ((cycle - 0) & mask)];
assert(x2185 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x2186 = x2184 + x2185;
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x2187 = x2176 + x2186;
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x2188 = x2187 * x99;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2189 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x2189 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x2190 = x2188 + x2189;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
auto x2191 = x2142 - x2190;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
if (x2191 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:30");
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2192 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x2192 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x2193 = x2192 * x77;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Twit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2194 = args[2][80 * steps + ((cycle - 0) & mask)];
assert(x2194 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:37)
auto x2195 = x2194 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x2196 = x2193 + x2195;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2197 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x2197 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x2198 = x2196 + x2197;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x2199 = x2198 * x66;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Twit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2200 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x2200 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:69)
auto x2201 = x2200 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x2202 = x2199 + x2201;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Twit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2203 = args[2][81 * steps + ((cycle - 0) & mask)];
assert(x2203 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x2204 = x2202 + x2203;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
auto x2205 = x2141 - x2204;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
if (x2205 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:31");
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2206 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x2206 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x2207 = x2206 * x71;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2208 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x2208 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x2209 = x2208 * x85;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Twit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2210 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x2210 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x2211 = x2209 + x2210;
// loc("cirgen/circuit/rv32im/decode.cpp":32:36)
auto x2212 = x2211 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x2213 = x2207 + x2212;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2214 = args[2][85 * steps + ((cycle - 0) & mask)];
assert(x2214 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:53)
auto x2215 = x2214 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x2216 = x2213 + x2215;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2217 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x2217 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x2218 = x2216 + x2217;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
auto x2219 = x2140 - x2218;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
if (x2219 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:32");
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2220 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x2220 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x2221 = x2220 * x71;
// loc("Top/Mux/4/Mux/2/ComputeCycle/Decoder/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2222 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x2222 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x2223 = x2221 + x2222;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
auto x2224 = x2139 - x2223;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
if (x2224 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:33");
{
host_args.at(0) = x2139;
host_args.at(1) = x2140;
host_args.at(2) = x2141;
host_args.at(3) = x2142;
host(ctx, "getMinor", "", host_args.data(), 4, host_outs.data(), 1);
auto x2225 = host_outs.at(0);
{
// loc("./cirgen/components/onehot.h":35:26)
auto x2226 = (x2225 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][171 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2226);
reg = x2226;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2227 = x2225 - x102;
// loc("./cirgen/components/onehot.h":35:26)
auto x2228 = (x2227 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][172 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2228);
reg = x2228;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2229 = x2225 - x99;
// loc("./cirgen/components/onehot.h":35:26)
auto x2230 = (x2229 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2230);
reg = x2230;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2231 = x2225 - x84;
// loc("./cirgen/components/onehot.h":35:26)
auto x2232 = (x2231 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][174 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2232);
reg = x2232;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2233 = x2225 - x85;
// loc("./cirgen/components/onehot.h":35:26)
auto x2234 = (x2233 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][175 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2234);
reg = x2234;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2235 = x2225 - x80;
// loc("./cirgen/components/onehot.h":35:26)
auto x2236 = (x2235 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2236);
reg = x2236;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2237 = x2225 - x79;
// loc("./cirgen/components/onehot.h":35:26)
auto x2238 = (x2237 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2238);
reg = x2238;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2239 = x2225 - x78;
// loc("./cirgen/components/onehot.h":35:26)
auto x2240 = (x2239 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2240);
reg = x2240;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2241 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x2241 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2242 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x2242 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2243 = x2242 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x2244 = x2241 + x2243;
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2245 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x2245 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2246 = x2245 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x2247 = x2244 + x2246;
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2248 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x2248 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2249 = x2248 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x2250 = x2247 + x2249;
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2251 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x2251 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2252 = x2251 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x2253 = x2250 + x2252;
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2254 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x2254 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2255 = x2254 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x2256 = x2253 + x2255;
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2257 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x2257 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2258 = x2257 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x2259 = x2256 + x2258;
// loc("./cirgen/components/onehot.h":38:8)
auto x2260 = x2259 - x2225;
// loc("./cirgen/components/onehot.h":38:8)
if (x2260 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
{
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg"("./cirgen/circuit/rv32im/rv32im.inl":54:68))
auto x2261 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x2261 != Fp::invalid());
if (x2261 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2262 = x2182 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x2263 = x2185 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2264 = x2262 + x2263;
// loc("cirgen/circuit/rv32im/decode.cpp":88:36)
auto x2265 = x2214 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2266 = x2264 + x2265;
// loc("cirgen/circuit/rv32im/decode.cpp":88:51)
auto x2267 = x2217 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2268 = x2266 + x2267;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2269 = x2175 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x2270 = x2220 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2271 = x2269 + x2270;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x2272 = x2177 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2273 = x2271 + x2272;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2274 = x2273 + x2179;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x2275 = x2175 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2268);
reg = x2268;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2274);
reg = x2274;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2275);
reg = x2275;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2275);
reg = x2275;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg1"("./cirgen/circuit/rv32im/rv32im.inl":55:68))
auto x2276 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x2276 != Fp::invalid());
if (x2276 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2277 = x2182 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x2278 = x2185 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2279 = x2277 + x2278;
// loc("cirgen/circuit/rv32im/decode.cpp":88:36)
auto x2280 = x2214 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2281 = x2279 + x2280;
// loc("cirgen/circuit/rv32im/decode.cpp":88:51)
auto x2282 = x2217 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2283 = x2281 + x2282;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2284 = x2175 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x2285 = x2220 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2286 = x2284 + x2285;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x2287 = x2177 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2288 = x2286 + x2287;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2289 = x2288 + x2179;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x2290 = x2175 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2283);
reg = x2283;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2289);
reg = x2289;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2290);
reg = x2290;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2290);
reg = x2290;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg2"("./cirgen/circuit/rv32im/rv32im.inl":56:68))
auto x2291 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x2291 != Fp::invalid());
if (x2291 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2292 = x2182 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x2293 = x2185 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2294 = x2292 + x2293;
// loc("cirgen/circuit/rv32im/decode.cpp":88:36)
auto x2295 = x2214 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2296 = x2294 + x2295;
// loc("cirgen/circuit/rv32im/decode.cpp":88:51)
auto x2297 = x2217 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2298 = x2296 + x2297;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2299 = x2175 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x2300 = x2220 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2301 = x2299 + x2300;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x2302 = x2177 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2303 = x2301 + x2302;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2304 = x2303 + x2179;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x2305 = x2175 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2298);
reg = x2298;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2304);
reg = x2304;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2305);
reg = x2305;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2305);
reg = x2305;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg3"("./cirgen/circuit/rv32im/rv32im.inl":57:68))
auto x2306 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x2306 != Fp::invalid());
if (x2306 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":106:7)
auto x2307 = x2182 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":106:21)
auto x2308 = x2185 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":106:7)
auto x2309 = x2307 + x2308;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2310 = x2189 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2311 = x2310 + x2198;
// loc("cirgen/circuit/rv32im/decode.cpp":106:7)
auto x2312 = x2309 + x2311;
// loc("cirgen/circuit/rv32im/decode.cpp":106:7)
auto x2313 = x2312 - x2197;
// loc("cirgen/circuit/rv32im/decode.cpp":107:39)
auto x2314 = x2197 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":107:7)
auto x2315 = x2213 + x2314;
// loc("cirgen/circuit/rv32im/decode.cpp":107:54)
auto x2316 = x2177 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":107:7)
auto x2317 = x2315 + x2316;
// loc("cirgen/circuit/rv32im/decode.cpp":107:7)
auto x2318 = x2317 + x2179;
// loc("cirgen/circuit/rv32im/decode.cpp":108:7)
auto x2319 = x2175 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":108:7)
auto x2320 = x2319 + x2201;
// loc("cirgen/circuit/rv32im/decode.cpp":108:7)
auto x2321 = x2320 + x2203;
// loc("cirgen/circuit/rv32im/decode.cpp":109:7)
auto x2322 = x2175 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2313);
reg = x2313;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2318);
reg = x2318;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2321);
reg = x2321;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2322);
reg = x2322;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":23:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":24:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":25:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg4"("./cirgen/circuit/rv32im/rv32im.inl":58:68))
auto x2323 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x2323 != Fp::invalid());
if (x2323 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2324 = x2182 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x2325 = x2185 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2326 = x2324 + x2325;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2327 = x2189 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2328 = x2327 + x2198;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2329 = x2326 + x2328;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2330 = x2175 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x2331 = x2177 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2332 = x2330 + x2331;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2333 = x2332 + x2179;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x2334 = x2175 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2329);
reg = x2329;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2333);
reg = x2333;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2334);
reg = x2334;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2334);
reg = x2334;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":23:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":24:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":25:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg5"("./cirgen/circuit/rv32im/rv32im.inl":59:68))
auto x2335 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x2335 != Fp::invalid());
if (x2335 != 0) {
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2213);
reg = x2213;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2204);
reg = x2204;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2190);
reg = x2190;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":48:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":49:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":50:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg6"("./cirgen/circuit/rv32im/rv32im.inl":60:68))
auto x2336 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x2336 != Fp::invalid());
if (x2336 != 0) {
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2213);
reg = x2213;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2204);
reg = x2204;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2190);
reg = x2190;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":23:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":24:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":25:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
}
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x2337 = x2200 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":37:26)
auto x2338 = x2203 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x2339 = x2337 + x2338;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x2340 = x2339 + x2206;
// loc("cirgen/circuit/rv32im/compute.cpp":134:39)
auto x2341 = x2340 + x55;
{
host_args.at(0) = x2341;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x2342 = host_outs.at(0);
auto x2343 = host_outs.at(1);
auto x2344 = host_outs.at(2);
auto x2345 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2342);
reg = x2342;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2343);
reg = x2343;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2344);
reg = x2344;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2345);
reg = x2345;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2346 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x2346 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2347 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x2347 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2348 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x2348 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2349 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x2349 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2341);
reg = x2341;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2133);
reg = x2133;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2346);
reg = x2346;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2347);
reg = x2347;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2348);
reg = x2348;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2349);
reg = x2349;
}
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2350 = x2189 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2351 = x2350 + x2198;
// loc("cirgen/circuit/rv32im/compute.cpp":135:39)
auto x2352 = x2351 + x55;
{
host_args.at(0) = x2352;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x2353 = host_outs.at(0);
auto x2354 = host_outs.at(1);
auto x2355 = host_outs.at(2);
auto x2356 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2353);
reg = x2353;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2354);
reg = x2354;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2355);
reg = x2355;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2356);
reg = x2356;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2357 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x2357 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2358 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x2358 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2359 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x2359 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2360 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x2360 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2352);
reg = x2352;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2133);
reg = x2133;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2357);
reg = x2357;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2358);
reg = x2358;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2359);
reg = x2359;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2360);
reg = x2360;
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2361 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x2361 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2362 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x2362 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2363 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x2363 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2364 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x2364 != Fp::invalid());
host_args.at(0) = x2361;
host_args.at(1) = x2362;
host_args.at(2) = x2363;
host_args.at(3) = x2364;
host_args.at(4) = x2340;
host_args.at(5) = x2346;
host_args.at(6) = x2347;
host_args.at(7) = x2348;
host_args.at(8) = x2349;
host_args.at(9) = x2351;
host_args.at(10) = x2357;
host_args.at(11) = x2358;
host_args.at(12) = x2359;
host_args.at(13) = x2360;
host(ctx, "log", " imm=%w, rs1=x%u -> %w, rs2=x%u -> %w", host_args.data(), 14, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2365 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x2365 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":145:17)
auto x2366 = x102 - x2365;
// loc("cirgen/components/u32.cpp":105:20)
auto x2367 = x2366 * x2346;
// loc("cirgen/components/u32.cpp":105:20)
auto x2368 = x2366 * x2347;
// loc("cirgen/components/u32.cpp":105:20)
auto x2369 = x2366 * x2348;
// loc("cirgen/components/u32.cpp":105:20)
auto x2370 = x2366 * x2349;
// loc("cirgen/circuit/rv32im/body.cpp":35:52)
auto x2371 = x600 * x85;
// loc("cirgen/circuit/rv32im/body.cpp":35:41)
auto x2372 = x597 + x2371;
// loc("cirgen/components/u32.cpp":97:20)
auto x2373 = x590 - x85;
// loc("cirgen/components/u32.cpp":105:20)
auto x2374 = x2365 * x2373;
// loc("cirgen/components/u32.cpp":105:20)
auto x2375 = x2365 * x591;
// loc("cirgen/components/u32.cpp":105:20)
auto x2376 = x2365 * x594;
// loc("cirgen/components/u32.cpp":105:20)
auto x2377 = x2365 * x2372;
// loc("cirgen/components/u32.cpp":89:20)
auto x2378 = x2367 + x2374;
// loc("cirgen/components/u32.cpp":89:20)
auto x2379 = x2368 + x2375;
// loc("cirgen/components/u32.cpp":89:20)
auto x2380 = x2369 + x2376;
// loc("cirgen/components/u32.cpp":89:20)
auto x2381 = x2370 + x2377;
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2382 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x2382 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":147:17)
auto x2383 = x102 - x2382;
// loc("cirgen/components/u32.cpp":105:20)
auto x2384 = x2383 * x2357;
// loc("cirgen/components/u32.cpp":105:20)
auto x2385 = x2383 * x2358;
// loc("cirgen/components/u32.cpp":105:20)
auto x2386 = x2383 * x2359;
// loc("cirgen/components/u32.cpp":105:20)
auto x2387 = x2383 * x2360;
// loc("cirgen/components/u32.cpp":105:20)
auto x2388 = x2382 * x2361;
// loc("cirgen/components/u32.cpp":105:20)
auto x2389 = x2382 * x2362;
// loc("cirgen/components/u32.cpp":105:20)
auto x2390 = x2382 * x2363;
// loc("cirgen/components/u32.cpp":105:20)
auto x2391 = x2382 * x2364;
// loc("cirgen/components/u32.cpp":89:20)
auto x2392 = x2384 + x2388;
// loc("cirgen/components/u32.cpp":89:20)
auto x2393 = x2385 + x2389;
// loc("cirgen/components/u32.cpp":89:20)
auto x2394 = x2386 + x2390;
// loc("cirgen/components/u32.cpp":89:20)
auto x2395 = x2387 + x2391;
host_args.at(0) = x2378;
host_args.at(1) = x2379;
host_args.at(2) = x2380;
host_args.at(3) = x2381;
host_args.at(4) = x2392;
host_args.at(5) = x2393;
host_args.at(6) = x2394;
host_args.at(7) = x2395;
host(ctx, "log", " inA = %w, inB = %w", host_args.data(), 8, host_outs.data(), 0);
{
// loc("cirgen/components/u32.cpp":120:18)
auto x2396 = Fp(x2381.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x2397 = x2396 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2397);
reg = x2397;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x2398 = Fp(x2381.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x2399 = x2398 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2399);
reg = x2399;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/TopBit/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2400 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x2400 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x2401 = x2400 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x2402 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x2402 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x2403 = x2402 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x2404 = x2401 + x2403;
// loc("cirgen/components/u32.cpp":123:6)
auto x2405 = x2381 - x2404;
// loc("cirgen/components/u32.cpp":123:6)
if (x2405 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
{
// loc("cirgen/components/u32.cpp":120:18)
auto x2406 = Fp(x2395.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x2407 = x2406 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][190 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2407);
reg = x2407;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x2408 = Fp(x2395.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x2409 = x2408 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2409);
reg = x2409;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/TopBit1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2410 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x2410 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x2411 = x2410 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("cirgen/components/bytes.cpp":78:10))
auto x2412 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x2412 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x2413 = x2412 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x2414 = x2411 + x2413;
// loc("cirgen/components/u32.cpp":123:6)
auto x2415 = x2395 - x2414;
// loc("cirgen/components/u32.cpp":123:6)
if (x2415 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][191 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2392);
reg = x2392;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][192 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2393);
reg = x2393;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][193 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2394);
reg = x2394;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][194 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2395);
reg = x2395;
}
{
// loc("cirgen/components/u32.cpp":113:20)
auto x2416 = Fp(x2378.asUInt32() & x2392.asUInt32());
// loc("cirgen/components/u32.cpp":113:20)
auto x2417 = Fp(x2379.asUInt32() & x2393.asUInt32());
// loc("cirgen/components/u32.cpp":113:20)
auto x2418 = Fp(x2380.asUInt32() & x2394.asUInt32());
// loc("cirgen/components/u32.cpp":113:20)
auto x2419 = Fp(x2381.asUInt32() & x2395.asUInt32());
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][195 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2416);
reg = x2416;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][196 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2417);
reg = x2417;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][197 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2418);
reg = x2418;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][198 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2419);
reg = x2419;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2420 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x2420 != Fp::invalid());
// loc("cirgen/components/u32.cpp":105:20)
auto x2421 = x2420 * x2378;
// loc("cirgen/components/u32.cpp":105:20)
auto x2422 = x2420 * x2379;
// loc("cirgen/components/u32.cpp":105:20)
auto x2423 = x2420 * x2380;
// loc("cirgen/components/u32.cpp":105:20)
auto x2424 = x2420 * x2381;
// loc("cirgen/components/u32.cpp":89:20)
auto x2425 = x2421 + x97;
// loc("cirgen/components/u32.cpp":89:20)
auto x2426 = x2422 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x2427 = x2423 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x2428 = x2424 + x98;
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2429 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x2429 != Fp::invalid());
// loc("cirgen/components/u32.cpp":105:20)
auto x2430 = x2429 * x2392;
// loc("cirgen/components/u32.cpp":105:20)
auto x2431 = x2429 * x2393;
// loc("cirgen/components/u32.cpp":105:20)
auto x2432 = x2429 * x2394;
// loc("cirgen/components/u32.cpp":105:20)
auto x2433 = x2429 * x2395;
// loc("cirgen/components/u32.cpp":89:20)
auto x2434 = x2425 + x2430;
// loc("cirgen/components/u32.cpp":89:20)
auto x2435 = x2426 + x2431;
// loc("cirgen/components/u32.cpp":89:20)
auto x2436 = x2427 + x2432;
// loc("cirgen/components/u32.cpp":89:20)
auto x2437 = x2428 + x2433;
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg4"("./cirgen/compiler/edsl/component.h":85:27))
auto x2438 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x2438 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/U32Reg1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2439 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x2439 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/U32Reg1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2440 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x2440 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/U32Reg1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2441 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x2441 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/U32Reg1/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2442 = args[2][198 * steps + ((cycle - 0) & mask)];
assert(x2442 != Fp::invalid());
// loc("cirgen/components/u32.cpp":105:20)
auto x2443 = x2438 * x2439;
// loc("cirgen/components/u32.cpp":105:20)
auto x2444 = x2438 * x2440;
// loc("cirgen/components/u32.cpp":105:20)
auto x2445 = x2438 * x2441;
// loc("cirgen/components/u32.cpp":105:20)
auto x2446 = x2438 * x2442;
// loc("cirgen/components/u32.cpp":89:20)
auto x2447 = x2434 + x2443;
// loc("cirgen/components/u32.cpp":89:20)
auto x2448 = x2435 + x2444;
// loc("cirgen/components/u32.cpp":89:20)
auto x2449 = x2436 + x2445;
// loc("cirgen/components/u32.cpp":89:20)
auto x2450 = x2437 + x2446;
// loc("cirgen/components/u32.cpp":146:29)
auto x2451 = x2448 * x97;
// loc("cirgen/components/u32.cpp":146:15)
auto x2452 = x2447 + x2451;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2453 = Fp(x2452.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2453);
reg = x2453;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2454 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x2454 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2455 = x2452 - x2454;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2456 = x2455 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2457 = Fp(x2456.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2457);
reg = x2457;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2458 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x2458 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2459 = x2456 - x2458;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2460 = x2459 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2460);
reg = x2460;
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/U32Normalize/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2461 = args[2][86 * steps + ((cycle - 0) & mask)];
assert(x2461 != Fp::invalid());
// loc("cirgen/components/u32.cpp":148:16)
auto x2462 = x2461 + x2449;
// loc("cirgen/components/u32.cpp":148:41)
auto x2463 = x2450 * x97;
// loc("cirgen/components/u32.cpp":148:16)
auto x2464 = x2462 + x2463;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2465 = Fp(x2464.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2465);
reg = x2465;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2466 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x2466 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2467 = x2464 - x2466;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2468 = x2467 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2469 = Fp(x2468.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2469);
reg = x2469;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2470 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x2470 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2471 = x2468 - x2470;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2472 = x2471 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2472);
reg = x2472;
}
{
// loc("cirgen/components/u32.cpp":120:18)
auto x2473 = Fp(x2470.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x2474 = x2473 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][199 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2474);
reg = x2474;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x2475 = Fp(x2470.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x2476 = x2475 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2476);
reg = x2476;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/TopBit2/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2477 = args[2][199 * steps + ((cycle - 0) & mask)];
assert(x2477 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x2478 = x2477 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x2479 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x2479 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x2480 = x2479 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x2481 = x2478 + x2480;
// loc("cirgen/components/u32.cpp":123:6)
auto x2482 = x2470 - x2481;
// loc("cirgen/components/u32.cpp":123:6)
if (x2482 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
// loc("cirgen/circuit/rv32im/compute.cpp":69:23)
auto x2483 = x102 - x2410;
// loc("cirgen/circuit/rv32im/compute.cpp":69:17)
auto x2484 = x2400 * x2483;
// loc("cirgen/circuit/rv32im/compute.cpp":69:34)
auto x2485 = x102 - x2477;
// loc("cirgen/circuit/rv32im/compute.cpp":69:17)
auto x2486 = x2484 * x2485;
// loc("cirgen/circuit/rv32im/compute.cpp":69:45)
auto x2487 = x102 - x2400;
// loc("cirgen/circuit/rv32im/compute.cpp":69:44)
auto x2488 = x2487 * x2410;
// loc("cirgen/circuit/rv32im/compute.cpp":69:44)
auto x2489 = x2488 * x2477;
// loc("cirgen/circuit/rv32im/compute.cpp":69:17)
auto x2490 = x2486 + x2489;
// loc("cirgen/circuit/rv32im/compute.cpp":69:3)
{
auto& reg = args[2][200 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2490);
reg = x2490;
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2491 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x2491 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":71:11)
auto x2492 = x2491 + x2477;
// loc("cirgen/circuit/rv32im/compute.cpp":71:27)
auto x2493 = x2491 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":71:27)
auto x2494 = x2493 * x2477;
// loc("cirgen/circuit/rv32im/compute.cpp":71:11)
auto x2495 = x2492 - x2494;
// loc("cirgen/circuit/rv32im/compute.cpp":71:3)
{
auto& reg = args[2][201 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2495);
reg = x2495;
}
// loc("cirgen/components/u32.cpp":137:26)
auto x2496 = x2458 * x97;
// loc("cirgen/components/u32.cpp":137:12)
auto x2497 = x2454 + x2496;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x2498 = (x2497 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][202 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2498);
reg = x2498;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x2499 = inv(x2497);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][203 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2499);
reg = x2499;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/IsZeroU32/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2500 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x2500 != Fp::invalid());
if (x2500 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x2497 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x2501 = x102 - x2500;
if (x2501 != 0) {
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/IsZeroU32/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2502 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x2502 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x2503 = x2497 * x2502;
// loc("cirgen/components/iszero.cpp":15:26)
auto x2504 = x2503 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x2504 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("cirgen/components/u32.cpp":138:27)
auto x2505 = x2470 * x97;
// loc("cirgen/components/u32.cpp":138:13)
auto x2506 = x2466 + x2505;
// loc("cirgen/components/u32.cpp":138:47)
auto x2507 = x2501 * x87;
// loc("cirgen/components/u32.cpp":138:13)
auto x2508 = x2506 + x2507;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x2509 = (x2508 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2509);
reg = x2509;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x2510 = inv(x2508);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2510);
reg = x2510;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/IsZeroU32/IsZero1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2511 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x2511 != Fp::invalid());
if (x2511 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x2508 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x2512 = x102 - x2511;
if (x2512 != 0) {
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/IsZeroU32/IsZero1/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2513 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x2513 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x2514 = x2508 * x2513;
// loc("cirgen/components/iszero.cpp":15:26)
auto x2515 = x2514 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x2515 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2516 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x2516 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/ALU/U32Normalize/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2517 = args[2][87 * steps + ((cycle - 0) & mask)];
assert(x2517 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":97:10)
auto x2518 = x102 - x2517;
host_args.at(0) = x2454;
host_args.at(1) = x2458;
host_args.at(2) = x2466;
host_args.at(3) = x2470;
host_args.at(4) = x2511;
host_args.at(5) = x2516;
host_args.at(6) = x2518;
host(ctx, "log", " ALU output = %w, EQ:%u, LT:%u, LTU:%u", host_args.data(), 7, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x2519 = x2214 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":45:25)
auto x2520 = x2217 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x2521 = x2519 + x2520;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x2522 = x2521 + x2220;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x2523 = (x2522 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2523);
reg = x2523;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x2524 = inv(x2522);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2524);
reg = x2524;
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2525 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x2525 != Fp::invalid());
if (x2525 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x2522 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x2526 = x102 - x2525;
if (x2526 != 0) {
// loc("Top/Mux/4/Mux/2/ComputeCycle/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2527 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x2527 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x2528 = x2522 * x2527;
// loc("cirgen/components/iszero.cpp":15:26)
auto x2529 = x2528 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x2529 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("cirgen/circuit/rv32im/compute.cpp":160:13)
auto x2530 = x603 + x85;
// loc("cirgen/components/u32.cpp":62:25)
auto x2531 = x2362 * x97;
// loc("cirgen/components/u32.cpp":62:13)
auto x2532 = x2361 + x2531;
// loc("cirgen/components/u32.cpp":62:49)
auto x2533 = x2363 * x87;
// loc("cirgen/components/u32.cpp":62:13)
auto x2534 = x2532 + x2533;
// loc("cirgen/components/u32.cpp":65:17)
auto x2535 = x2364 * x54;
// loc("cirgen/components/u32.cpp":65:16)
auto x2536 = x2535 * x53;
// loc("cirgen/components/u32.cpp":65:10)
auto x2537 = x2534 + x2536;
// loc("cirgen/circuit/rv32im/compute.cpp":161:14)
auto x2538 = x603 + x2537;
// loc("cirgen/circuit/rv32im/compute.cpp":166:57)
auto x2539 = x2466 * x87;
// loc("cirgen/circuit/rv32im/compute.cpp":166:13)
auto x2540 = x2497 + x2539;
// loc("cirgen/circuit/rv32im/compute.cpp":167:14)
auto x2541 = x2470 * x86;
// loc("cirgen/circuit/rv32im/compute.cpp":166:13)
auto x2542 = x2540 + x2541;
// loc("cirgen/circuit/rv32im/compute.cpp":171:13)
auto x2543 = x2516 * x2530;
// loc("cirgen/circuit/rv32im/compute.cpp":171:35)
auto x2544 = x102 - x2516;
// loc("cirgen/circuit/rv32im/compute.cpp":171:34)
auto x2545 = x2544 * x2538;
// loc("cirgen/circuit/rv32im/compute.cpp":171:13)
auto x2546 = x2543 + x2545;
// loc("cirgen/circuit/rv32im/compute.cpp":172:14)
auto x2547 = x2518 * x2538;
// loc("cirgen/circuit/rv32im/compute.cpp":172:38)
auto x2548 = x102 - x2518;
// loc("cirgen/circuit/rv32im/compute.cpp":172:37)
auto x2549 = x2548 * x2530;
// loc("cirgen/circuit/rv32im/compute.cpp":172:14)
auto x2550 = x2547 + x2549;
// loc("cirgen/circuit/rv32im/compute.cpp":173:14)
auto x2551 = x2518 * x2530;
// loc("cirgen/circuit/rv32im/compute.cpp":173:36)
auto x2552 = x2548 * x2538;
// loc("cirgen/circuit/rv32im/compute.cpp":173:14)
auto x2553 = x2551 + x2552;
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg"("./cirgen/circuit/rv32im/rv32im.inl":54:68))
auto x2554 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x2554 != Fp::invalid());
if (x2554 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":54:68)
auto x2555 = x2222 - x49;
// loc("./cirgen/circuit/rv32im/rv32im.inl":54:68)
if (x2555 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:54");
// loc("./cirgen/circuit/rv32im/rv32im.inl":54:68)
auto x2556 = x2211 - x80;
// loc("./cirgen/circuit/rv32im/rv32im.inl":54:68)
if (x2556 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:54");
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2557 = x2182 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x2558 = x2185 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2559 = x2557 + x2558;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2560 = x2559 + x2519;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2561 = x2560 + x2520;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2562 = x2175 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x2563 = x2220 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2564 = x2562 + x2563;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x2565 = x2177 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2566 = x2564 + x2565;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2567 = x2566 + x2179;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x2568 = x2175 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2561);
reg = x2561;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2567);
reg = x2567;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2568);
reg = x2568;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2568);
reg = x2568;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x2569 = x2546 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2570 = Fp(x2569.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2570);
reg = x2570;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2571 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x2571 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2572 = x2569 - x2571;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2573 = x2572 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2574 = Fp(x2573.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2574);
reg = x2574;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2575 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x2575 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2576 = x2573 - x2575;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2577 = x2576 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2578 = Fp(x2577.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2578);
reg = x2578;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2579 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x2579 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2580 = x2577 - x2579;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2581 = x2580 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x2582 = Fp(x2581.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2582);
reg = x2582;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2583 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x2583 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x2584 = x2581 - x2583;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x2585 = x2584 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2585);
reg = x2585;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2586 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x2586 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x2587 = x102 - x2586;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x2588 = x2586 * x2587;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2588);
reg = x2588;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2589 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x2589 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x2590 = x99 - x2586;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x2591 = x2589 * x2590;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x2591 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x2592 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x2592 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":54:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2592);
reg = x2592;
}
if (x101 != 0) {
host_args.at(0) = x2522;
host_args.at(1) = x2454;
host_args.at(2) = x2458;
host_args.at(3) = x2466;
host_args.at(4) = x2470;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":54:68)
auto x2593 = x2522 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2454);
reg = x2454;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2458);
reg = x2458;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2466);
reg = x2466;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2470);
reg = x2470;
}
{
host_args.at(0) = x2593;
host_args.at(1) = x2454;
host_args.at(2) = x2458;
host_args.at(3) = x2466;
host_args.at(4) = x2470;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2594 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x2594 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2595 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x2595 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2596 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x2596 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2597 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x2597 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2593);
reg = x2593;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2133);
reg = x2133;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2594);
reg = x2594;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2595);
reg = x2595;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2596);
reg = x2596;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2597);
reg = x2597;
}
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":54:68)
auto x2598 = x2525 + x102;
if (x2598 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg1"("./cirgen/circuit/rv32im/rv32im.inl":55:68))
auto x2599 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x2599 != Fp::invalid());
if (x2599 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":55:68)
auto x2600 = x2222 - x49;
// loc("./cirgen/circuit/rv32im/rv32im.inl":55:68)
if (x2600 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:55");
// loc("./cirgen/circuit/rv32im/rv32im.inl":55:68)
auto x2601 = x2211 - x79;
// loc("./cirgen/circuit/rv32im/rv32im.inl":55:68)
if (x2601 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:55");
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2602 = x2182 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x2603 = x2185 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2604 = x2602 + x2603;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2605 = x2604 + x2519;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2606 = x2605 + x2520;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2607 = x2175 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x2608 = x2220 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2609 = x2607 + x2608;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x2610 = x2177 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2611 = x2609 + x2610;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2612 = x2611 + x2179;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x2613 = x2175 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2606);
reg = x2606;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2612);
reg = x2612;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2613);
reg = x2613;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2613);
reg = x2613;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x2614 = x2550 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2615 = Fp(x2614.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2615);
reg = x2615;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2616 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x2616 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2617 = x2614 - x2616;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2618 = x2617 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2619 = Fp(x2618.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2619);
reg = x2619;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2620 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x2620 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2621 = x2618 - x2620;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2622 = x2621 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2623 = Fp(x2622.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2623);
reg = x2623;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2624 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x2624 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2625 = x2622 - x2624;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2626 = x2625 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x2627 = Fp(x2626.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2627);
reg = x2627;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2628 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x2628 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x2629 = x2626 - x2628;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x2630 = x2629 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2630);
reg = x2630;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2631 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x2631 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x2632 = x102 - x2631;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x2633 = x2631 * x2632;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2633);
reg = x2633;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2634 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x2634 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x2635 = x99 - x2631;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x2636 = x2634 * x2635;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x2636 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x2637 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x2637 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":55:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2637);
reg = x2637;
}
if (x101 != 0) {
host_args.at(0) = x2522;
host_args.at(1) = x2454;
host_args.at(2) = x2458;
host_args.at(3) = x2466;
host_args.at(4) = x2470;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":55:68)
auto x2638 = x2522 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2454);
reg = x2454;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2458);
reg = x2458;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2466);
reg = x2466;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2470);
reg = x2470;
}
{
host_args.at(0) = x2638;
host_args.at(1) = x2454;
host_args.at(2) = x2458;
host_args.at(3) = x2466;
host_args.at(4) = x2470;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2639 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x2639 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2640 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x2640 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2641 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x2641 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2642 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x2642 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2638);
reg = x2638;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2133);
reg = x2133;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2639);
reg = x2639;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2640);
reg = x2640;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2641);
reg = x2641;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2642);
reg = x2642;
}
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":55:68)
auto x2643 = x2525 + x102;
if (x2643 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg2"("./cirgen/circuit/rv32im/rv32im.inl":56:68))
auto x2644 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x2644 != Fp::invalid());
if (x2644 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":56:68)
auto x2645 = x2222 - x49;
// loc("./cirgen/circuit/rv32im/rv32im.inl":56:68)
if (x2645 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:56");
// loc("./cirgen/circuit/rv32im/rv32im.inl":56:68)
auto x2646 = x2211 - x78;
// loc("./cirgen/circuit/rv32im/rv32im.inl":56:68)
if (x2646 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:56");
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2647 = x2182 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":88:21)
auto x2648 = x2185 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2649 = x2647 + x2648;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2650 = x2649 + x2519;
// loc("cirgen/circuit/rv32im/decode.cpp":88:7)
auto x2651 = x2650 + x2520;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2652 = x2175 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":89:21)
auto x2653 = x2220 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2654 = x2652 + x2653;
// loc("cirgen/circuit/rv32im/decode.cpp":89:35)
auto x2655 = x2177 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2656 = x2654 + x2655;
// loc("cirgen/circuit/rv32im/decode.cpp":89:7)
auto x2657 = x2656 + x2179;
// loc("cirgen/circuit/rv32im/decode.cpp":90:7)
auto x2658 = x2175 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2651);
reg = x2651;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2657);
reg = x2657;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2658);
reg = x2658;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2658);
reg = x2658;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":29:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x58);
reg = x58;
}
// loc("cirgen/circuit/rv32im/compute.cpp":30:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x2659 = x2553 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2660 = Fp(x2659.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2660);
reg = x2660;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2661 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x2661 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2662 = x2659 - x2661;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2663 = x2662 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2664 = Fp(x2663.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2664);
reg = x2664;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2665 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x2665 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2666 = x2663 - x2665;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2667 = x2666 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2668 = Fp(x2667.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2668);
reg = x2668;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2669 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x2669 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2670 = x2667 - x2669;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2671 = x2670 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x2672 = Fp(x2671.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2672);
reg = x2672;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2673 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x2673 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x2674 = x2671 - x2673;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x2675 = x2674 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2675);
reg = x2675;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2676 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x2676 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x2677 = x102 - x2676;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x2678 = x2676 * x2677;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2678);
reg = x2678;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2679 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x2679 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x2680 = x99 - x2676;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x2681 = x2679 * x2680;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x2681 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x2682 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x2682 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":56:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2682);
reg = x2682;
}
if (x101 != 0) {
host_args.at(0) = x2522;
host_args.at(1) = x2454;
host_args.at(2) = x2458;
host_args.at(3) = x2466;
host_args.at(4) = x2470;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":56:68)
auto x2683 = x2522 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2454);
reg = x2454;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2458);
reg = x2458;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2466);
reg = x2466;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2470);
reg = x2470;
}
{
host_args.at(0) = x2683;
host_args.at(1) = x2454;
host_args.at(2) = x2458;
host_args.at(3) = x2466;
host_args.at(4) = x2470;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2684 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x2684 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2685 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x2685 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2686 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x2686 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2687 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x2687 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2683);
reg = x2683;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2133);
reg = x2133;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2684);
reg = x2684;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2685);
reg = x2685;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2686);
reg = x2686;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2687);
reg = x2687;
}
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":56:68)
auto x2688 = x2525 + x102;
if (x2688 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg3"("./cirgen/circuit/rv32im/rv32im.inl":57:68))
auto x2689 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x2689 != Fp::invalid());
if (x2689 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":57:68)
auto x2690 = x2222 - x48;
// loc("./cirgen/circuit/rv32im/rv32im.inl":57:68)
if (x2690 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:57");
// loc("cirgen/circuit/rv32im/decode.cpp":106:7)
auto x2691 = x2182 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":106:21)
auto x2692 = x2185 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":106:7)
auto x2693 = x2691 + x2692;
// loc("cirgen/circuit/rv32im/decode.cpp":106:7)
auto x2694 = x2693 + x2351;
// loc("cirgen/circuit/rv32im/decode.cpp":106:7)
auto x2695 = x2694 - x2197;
// loc("cirgen/circuit/rv32im/decode.cpp":107:39)
auto x2696 = x2197 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":107:7)
auto x2697 = x2213 + x2696;
// loc("cirgen/circuit/rv32im/decode.cpp":107:54)
auto x2698 = x2177 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":107:7)
auto x2699 = x2697 + x2698;
// loc("cirgen/circuit/rv32im/decode.cpp":107:7)
auto x2700 = x2699 + x2179;
// loc("cirgen/circuit/rv32im/decode.cpp":108:7)
auto x2701 = x2175 * x50;
// loc("cirgen/circuit/rv32im/decode.cpp":108:7)
auto x2702 = x2701 + x2201;
// loc("cirgen/circuit/rv32im/decode.cpp":108:7)
auto x2703 = x2702 + x2203;
// loc("cirgen/circuit/rv32im/decode.cpp":109:7)
auto x2704 = x2175 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2695);
reg = x2695;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2700);
reg = x2700;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2703);
reg = x2703;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2704);
reg = x2704;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":23:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":24:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":25:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x2705 = x2538 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2706 = Fp(x2705.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2706);
reg = x2706;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2707 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x2707 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2708 = x2705 - x2707;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2709 = x2708 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2710 = Fp(x2709.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2710);
reg = x2710;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2711 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x2711 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2712 = x2709 - x2711;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2713 = x2712 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2714 = Fp(x2713.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2714);
reg = x2714;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2715 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x2715 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2716 = x2713 - x2715;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2717 = x2716 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x2718 = Fp(x2717.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2718);
reg = x2718;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2719 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x2719 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x2720 = x2717 - x2719;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x2721 = x2720 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2721);
reg = x2721;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2722 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x2722 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x2723 = x102 - x2722;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x2724 = x2722 * x2723;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2724);
reg = x2724;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2725 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x2725 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x2726 = x99 - x2722;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x2727 = x2725 * x2726;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x2727 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x2728 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x2728 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":57:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2728);
reg = x2728;
}
if (x2526 != 0) {
host_args.at(0) = x2522;
host_args.at(1) = x590;
host_args.at(2) = x591;
host_args.at(3) = x594;
host_args.at(4) = x2372;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":57:68)
auto x2729 = x2522 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x590);
reg = x590;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x591);
reg = x591;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x594);
reg = x594;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2372);
reg = x2372;
}
{
host_args.at(0) = x2729;
host_args.at(1) = x590;
host_args.at(2) = x591;
host_args.at(3) = x594;
host_args.at(4) = x2372;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2730 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x2730 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2731 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x2731 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2732 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x2732 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2733 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x2733 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2729);
reg = x2729;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2133);
reg = x2133;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2730);
reg = x2730;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2731);
reg = x2731;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2732);
reg = x2732;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2733);
reg = x2733;
}
}
if (x2525 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg4"("./cirgen/circuit/rv32im/rv32im.inl":58:68))
auto x2734 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x2734 != Fp::invalid());
if (x2734 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":58:68)
auto x2735 = x2222 - x47;
// loc("./cirgen/circuit/rv32im/rv32im.inl":58:68)
if (x2735 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:58");
// loc("./cirgen/circuit/rv32im/rv32im.inl":58:68)
if (x2211 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:58");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2736 = x2182 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x2737 = x2185 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2738 = x2736 + x2737;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2739 = x2738 + x2351;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2740 = x2175 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x2741 = x2177 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2742 = x2740 + x2741;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2743 = x2742 + x2179;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x2744 = x2175 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2739);
reg = x2739;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2743);
reg = x2743;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2744);
reg = x2744;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2744);
reg = x2744;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":23:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":24:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":25:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x2745 = x2542 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2746 = Fp(x2745.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2746);
reg = x2746;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2747 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x2747 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2748 = x2745 - x2747;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2749 = x2748 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2750 = Fp(x2749.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2750);
reg = x2750;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2751 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x2751 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2752 = x2749 - x2751;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2753 = x2752 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2754 = Fp(x2753.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2754);
reg = x2754;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2755 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x2755 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2756 = x2753 - x2755;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2757 = x2756 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x2758 = Fp(x2757.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2758);
reg = x2758;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2759 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x2759 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x2760 = x2757 - x2759;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x2761 = x2760 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2761);
reg = x2761;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2762 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x2762 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x2763 = x102 - x2762;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x2764 = x2762 * x2763;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2764);
reg = x2764;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2765 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x2765 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x2766 = x99 - x2762;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x2767 = x2765 * x2766;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x2767 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x2768 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x2768 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":58:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2768);
reg = x2768;
}
if (x2526 != 0) {
host_args.at(0) = x2522;
host_args.at(1) = x590;
host_args.at(2) = x591;
host_args.at(3) = x594;
host_args.at(4) = x2372;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":58:68)
auto x2769 = x2522 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x590);
reg = x590;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x591);
reg = x591;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x594);
reg = x594;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2372);
reg = x2372;
}
{
host_args.at(0) = x2769;
host_args.at(1) = x590;
host_args.at(2) = x591;
host_args.at(3) = x594;
host_args.at(4) = x2372;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2770 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x2770 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2771 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x2771 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2772 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x2772 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2773 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x2773 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2769);
reg = x2769;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2133);
reg = x2133;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2770);
reg = x2770;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2771);
reg = x2771;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2772);
reg = x2772;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2773);
reg = x2773;
}
}
if (x2525 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg5"("./cirgen/circuit/rv32im/rv32im.inl":59:68))
auto x2774 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x2774 != Fp::invalid());
if (x2774 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":59:68)
auto x2775 = x2222 - x46;
// loc("./cirgen/circuit/rv32im/rv32im.inl":59:68)
if (x2775 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:59");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2213);
reg = x2213;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2204);
reg = x2204;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2190);
reg = x2190;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":48:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":49:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":50:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x2776 = x2530 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2777 = Fp(x2776.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2777);
reg = x2777;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2778 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x2778 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2779 = x2776 - x2778;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2780 = x2779 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2781 = Fp(x2780.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2781);
reg = x2781;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2782 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x2782 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2783 = x2780 - x2782;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2784 = x2783 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2785 = Fp(x2784.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2785);
reg = x2785;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2786 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x2786 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2787 = x2784 - x2786;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2788 = x2787 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x2789 = Fp(x2788.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2789);
reg = x2789;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2790 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x2790 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x2791 = x2788 - x2790;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x2792 = x2791 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2792);
reg = x2792;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2793 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x2793 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x2794 = x102 - x2793;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x2795 = x2793 * x2794;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2795);
reg = x2795;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2796 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x2796 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x2797 = x99 - x2793;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x2798 = x2796 * x2797;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x2798 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x2799 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x2799 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":59:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2799);
reg = x2799;
}
if (x2526 != 0) {
host_args.at(0) = x2522;
host_args.at(1) = x2454;
host_args.at(2) = x2458;
host_args.at(3) = x2466;
host_args.at(4) = x2470;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":59:68)
auto x2800 = x2522 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2454);
reg = x2454;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2458);
reg = x2458;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2466);
reg = x2466;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2470);
reg = x2470;
}
{
host_args.at(0) = x2800;
host_args.at(1) = x2454;
host_args.at(2) = x2458;
host_args.at(3) = x2466;
host_args.at(4) = x2470;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2801 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x2801 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2802 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x2802 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2803 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x2803 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2804 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x2804 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2800);
reg = x2800;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2133);
reg = x2133;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2801);
reg = x2801;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2802);
reg = x2802;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2803);
reg = x2803;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2804);
reg = x2804;
}
}
if (x2525 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/OneHot/Reg6"("./cirgen/circuit/rv32im/rv32im.inl":60:68))
auto x2805 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x2805 != Fp::invalid());
if (x2805 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":60:68)
auto x2806 = x2222 - x45;
// loc("./cirgen/circuit/rv32im/rv32im.inl":60:68)
if (x2806 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:60");
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2213);
reg = x2213;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2204);
reg = x2204;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2190);
reg = x2190;
}
// loc("cirgen/circuit/rv32im/compute.cpp":19:3)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":20:3)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":23:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":24:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/compute.cpp":25:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/compute.cpp":53:3)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x2807 = x2530 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2808 = Fp(x2807.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2808);
reg = x2808;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2809 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x2809 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2810 = x2807 - x2809;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2811 = x2810 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2812 = Fp(x2811.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2812);
reg = x2812;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x2813 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x2813 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2814 = x2811 - x2813;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2815 = x2814 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x2816 = Fp(x2815.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2816);
reg = x2816;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x2817 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x2817 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x2818 = x2815 - x2817;
// loc("cirgen/components/bytes.cpp":83:10)
auto x2819 = x2818 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x2820 = Fp(x2819.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2820);
reg = x2820;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2821 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x2821 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x2822 = x2819 - x2821;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x2823 = x2822 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2823);
reg = x2823;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2824 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x2824 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x2825 = x102 - x2824;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x2826 = x2824 * x2825;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2826);
reg = x2826;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2827 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x2827 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x2828 = x99 - x2824;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x2829 = x2827 * x2828;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x2829 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/2/ComputeCycle/ComputeControl/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x2830 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x2830 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":60:68)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2830);
reg = x2830;
}
if (x2526 != 0) {
host_args.at(0) = x2522;
host_args.at(1) = x2454;
host_args.at(2) = x2458;
host_args.at(3) = x2466;
host_args.at(4) = x2470;
host(ctx, "log", " Writing to rd=x%u, val = %w", host_args.data(), 5, host_outs.data(), 0);
// loc("./cirgen/circuit/rv32im/rv32im.inl":60:68)
auto x2831 = x2522 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2454);
reg = x2454;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2458);
reg = x2458;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2466);
reg = x2466;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2470);
reg = x2470;
}
{
host_args.at(0) = x2831;
host_args.at(1) = x2454;
host_args.at(2) = x2458;
host_args.at(3) = x2466;
host_args.at(4) = x2470;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2832 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x2832 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2833 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x2833 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2834 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x2834 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2835 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x2835 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2831);
reg = x2831;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2133);
reg = x2133;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2832);
reg = x2832;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2833);
reg = x2833;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2834);
reg = x2834;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2835);
reg = x2835;
}
}
if (x2525 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
}
// loc("Top/Mux/4/OneHot/Reg3"("./cirgen/components/mux.h":37:25))
auto x2836 = args[2][97 * steps + ((cycle - 0) & mask)];
assert(x2836 != Fp::invalid());
if (x2836 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2837 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x2837 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":20:41)
auto x2838 = x603 * x83;
{
host_args.at(0) = x2838;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x2839 = host_outs.at(0);
auto x2840 = host_outs.at(1);
auto x2841 = host_outs.at(2);
auto x2842 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2839);
reg = x2839;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2840);
reg = x2840;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2841);
reg = x2841;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2842);
reg = x2842;
}
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2843 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x2843 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x2844 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x2844 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x2845 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x2845 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x2846 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x2846 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2838);
reg = x2838;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2843);
reg = x2843;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2844);
reg = x2844;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2845);
reg = x2845;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2846);
reg = x2846;
}
{
// loc("cirgen/circuit/rv32im/decode.cpp":11:16)
auto x2847 = Fp(x2846.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":11:15)
auto x2848 = x2847 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2848);
reg = x2848;
}
// loc("cirgen/circuit/rv32im/decode.cpp":12:17)
auto x2849 = Fp(x2846.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":12:16)
auto x2850 = x2849 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2850);
reg = x2850;
}
// loc("cirgen/circuit/rv32im/decode.cpp":13:16)
auto x2851 = Fp(x2846.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":13:15)
auto x2852 = x2851 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2852);
reg = x2852;
}
// loc("cirgen/circuit/rv32im/decode.cpp":14:16)
auto x2853 = Fp(x2846.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":14:15)
auto x2854 = x2853 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2854);
reg = x2854;
}
// loc("cirgen/circuit/rv32im/decode.cpp":15:17)
auto x2855 = Fp(x2846.asUInt32() & x79.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":15:16)
auto x2856 = x2855 * x63;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2856);
reg = x2856;
}
// loc("cirgen/circuit/rv32im/decode.cpp":16:17)
auto x2857 = Fp(x2846.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2857);
reg = x2857;
}
// loc("cirgen/circuit/rv32im/decode.cpp":17:17)
auto x2858 = Fp(x2845.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":17:16)
auto x2859 = x2858 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2859);
reg = x2859;
}
// loc("cirgen/circuit/rv32im/decode.cpp":18:18)
auto x2860 = Fp(x2845.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":18:17)
auto x2861 = x2860 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2861);
reg = x2861;
}
// loc("cirgen/circuit/rv32im/decode.cpp":19:17)
auto x2862 = Fp(x2845.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":19:16)
auto x2863 = x2862 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2863);
reg = x2863;
}
// loc("cirgen/circuit/rv32im/decode.cpp":20:18)
auto x2864 = Fp(x2845.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":20:17)
auto x2865 = x2864 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2865);
reg = x2865;
}
// loc("cirgen/circuit/rv32im/decode.cpp":21:18)
auto x2866 = Fp(x2845.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2866);
reg = x2866;
}
// loc("cirgen/circuit/rv32im/decode.cpp":22:17)
auto x2867 = Fp(x2844.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":22:16)
auto x2868 = x2867 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2868);
reg = x2868;
}
// loc("cirgen/circuit/rv32im/decode.cpp":23:19)
auto x2869 = Fp(x2844.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":23:18)
auto x2870 = x2869 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2870);
reg = x2870;
}
// loc("cirgen/circuit/rv32im/decode.cpp":24:20)
auto x2871 = Fp(x2844.asUInt32() & x60.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":24:19)
auto x2872 = x2871 * x65;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2872);
reg = x2872;
}
// loc("cirgen/circuit/rv32im/decode.cpp":25:17)
auto x2873 = Fp(x2844.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":25:16)
auto x2874 = x2873 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2874);
reg = x2874;
}
// loc("cirgen/circuit/rv32im/decode.cpp":26:17)
auto x2875 = Fp(x2844.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2875);
reg = x2875;
}
// loc("cirgen/circuit/rv32im/decode.cpp":27:16)
auto x2876 = Fp(x2843.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":27:15)
auto x2877 = x2876 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2877);
reg = x2877;
}
// loc("cirgen/circuit/rv32im/decode.cpp":28:18)
auto x2878 = Fp(x2843.asUInt32() & x59.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2878);
reg = x2878;
}
}
// loc("Top/Mux/4/Mux/3/Decoder/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2879 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x2879 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x2880 = x2879 * x62;
// loc("Top/Mux/4/Mux/3/Decoder/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2881 = args[2][80 * steps + ((cycle - 0) & mask)];
assert(x2881 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x2882 = x2881 * x66;
// loc("Top/Mux/4/Mux/3/Decoder/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2883 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x2883 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:25)
auto x2884 = x2883 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x2885 = x2882 + x2884;
// loc("Top/Mux/4/Mux/3/Decoder/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2886 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x2886 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:39)
auto x2887 = x2886 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x2888 = x2885 + x2887;
// loc("Top/Mux/4/Mux/3/Decoder/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2889 = args[2][79 * steps + ((cycle - 0) & mask)];
assert(x2889 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x2890 = x2888 + x2889;
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x2891 = x2880 + x2890;
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x2892 = x2891 * x99;
// loc("Top/Mux/4/Mux/3/Decoder/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2893 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x2893 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x2894 = x2892 + x2893;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
auto x2895 = x2846 - x2894;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
if (x2895 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:30");
// loc("Top/Mux/4/Mux/3/Decoder/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2896 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x2896 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x2897 = x2896 * x77;
// loc("Top/Mux/4/Mux/3/Decoder/Twit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2898 = args[2][81 * steps + ((cycle - 0) & mask)];
assert(x2898 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:37)
auto x2899 = x2898 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x2900 = x2897 + x2899;
// loc("Top/Mux/4/Mux/3/Decoder/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2901 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x2901 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x2902 = x2900 + x2901;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x2903 = x2902 * x66;
// loc("Top/Mux/4/Mux/3/Decoder/Twit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2904 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x2904 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:69)
auto x2905 = x2904 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x2906 = x2903 + x2905;
// loc("Top/Mux/4/Mux/3/Decoder/Twit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2907 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x2907 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x2908 = x2906 + x2907;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
auto x2909 = x2845 - x2908;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
if (x2909 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:31");
// loc("Top/Mux/4/Mux/3/Decoder/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2910 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x2910 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x2911 = x2910 * x71;
// loc("Top/Mux/4/Mux/3/Decoder/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2912 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x2912 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x2913 = x2912 * x85;
// loc("Top/Mux/4/Mux/3/Decoder/Twit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2914 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x2914 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x2915 = x2913 + x2914;
// loc("cirgen/circuit/rv32im/decode.cpp":32:36)
auto x2916 = x2915 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x2917 = x2911 + x2916;
// loc("Top/Mux/4/Mux/3/Decoder/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2918 = args[2][86 * steps + ((cycle - 0) & mask)];
assert(x2918 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:53)
auto x2919 = x2918 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x2920 = x2917 + x2919;
// loc("Top/Mux/4/Mux/3/Decoder/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2921 = args[2][85 * steps + ((cycle - 0) & mask)];
assert(x2921 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x2922 = x2920 + x2921;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
auto x2923 = x2844 - x2922;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
if (x2923 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:32");
// loc("Top/Mux/4/Mux/3/Decoder/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x2924 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x2924 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x2925 = x2924 * x71;
// loc("Top/Mux/4/Mux/3/Decoder/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2926 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x2926 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x2927 = x2925 + x2926;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
auto x2928 = x2843 - x2927;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
if (x2928 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:33");
{
host_args.at(0) = x2843;
host_args.at(1) = x2844;
host_args.at(2) = x2845;
host_args.at(3) = x2846;
host(ctx, "getMinor", "", host_args.data(), 4, host_outs.data(), 1);
auto x2929 = host_outs.at(0);
{
// loc("./cirgen/components/onehot.h":35:26)
auto x2930 = (x2929 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][190 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2930);
reg = x2930;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2931 = x2929 - x102;
// loc("./cirgen/components/onehot.h":35:26)
auto x2932 = (x2931 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][191 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2932);
reg = x2932;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2933 = x2929 - x99;
// loc("./cirgen/components/onehot.h":35:26)
auto x2934 = (x2933 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][192 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2934);
reg = x2934;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2935 = x2929 - x84;
// loc("./cirgen/components/onehot.h":35:26)
auto x2936 = (x2935 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][193 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2936);
reg = x2936;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2937 = x2929 - x85;
// loc("./cirgen/components/onehot.h":35:26)
auto x2938 = (x2937 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][194 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2938);
reg = x2938;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2939 = x2929 - x80;
// loc("./cirgen/components/onehot.h":35:26)
auto x2940 = (x2939 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][195 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2940);
reg = x2940;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2941 = x2929 - x79;
// loc("./cirgen/components/onehot.h":35:26)
auto x2942 = (x2941 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][196 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2942);
reg = x2942;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x2943 = x2929 - x78;
// loc("./cirgen/components/onehot.h":35:26)
auto x2944 = (x2943 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][197 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2944);
reg = x2944;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2945 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x2945 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2946 = args[2][192 * steps + ((cycle - 0) & mask)];
assert(x2946 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2947 = x2946 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x2948 = x2945 + x2947;
// loc("Top/Mux/4/Mux/3/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2949 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x2949 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2950 = x2949 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x2951 = x2948 + x2950;
// loc("Top/Mux/4/Mux/3/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2952 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x2952 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2953 = x2952 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x2954 = x2951 + x2953;
// loc("Top/Mux/4/Mux/3/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2955 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x2955 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2956 = x2955 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x2957 = x2954 + x2956;
// loc("Top/Mux/4/Mux/3/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2958 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x2958 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2959 = x2958 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x2960 = x2957 + x2959;
// loc("Top/Mux/4/Mux/3/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x2961 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x2961 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x2962 = x2961 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x2963 = x2960 + x2962;
// loc("./cirgen/components/onehot.h":38:8)
auto x2964 = x2963 - x2929;
// loc("./cirgen/components/onehot.h":38:8)
if (x2964 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
{
// loc("Top/Mux/4/Mux/3/OneHot/Reg"("./cirgen/circuit/rv32im/rv32im.inl":76:46))
auto x2965 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x2965 != Fp::invalid());
if (x2965 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2966 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x2967 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2968 = x2966 + x2967;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2969 = x2893 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2970 = x2969 + x2902;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2971 = x2968 + x2970;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2972 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x2973 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2974 = x2972 + x2973;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2975 = x2974 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x2976 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2971);
reg = x2971;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2975);
reg = x2975;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2976);
reg = x2976;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2976);
reg = x2976;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg1"("./cirgen/circuit/rv32im/rv32im.inl":77:46))
auto x2977 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x2977 != Fp::invalid());
if (x2977 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2978 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x2979 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2980 = x2978 + x2979;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2981 = x2893 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2982 = x2981 + x2902;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2983 = x2980 + x2982;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2984 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x2985 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2986 = x2984 + x2985;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2987 = x2986 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x2988 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2983);
reg = x2983;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2987);
reg = x2987;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2988);
reg = x2988;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2988);
reg = x2988;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg2"("./cirgen/circuit/rv32im/rv32im.inl":78:46))
auto x2989 = args[2][192 * steps + ((cycle - 0) & mask)];
assert(x2989 != Fp::invalid());
if (x2989 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2990 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x2991 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2992 = x2990 + x2991;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2993 = x2893 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x2994 = x2993 + x2902;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x2995 = x2992 + x2994;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2996 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x2997 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2998 = x2996 + x2997;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x2999 = x2998 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x3000 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2995);
reg = x2995;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2999);
reg = x2999;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3000);
reg = x3000;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3000);
reg = x3000;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg3"("./cirgen/circuit/rv32im/rv32im.inl":79:46))
auto x3001 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x3001 != Fp::invalid());
if (x3001 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3002 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x3003 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3004 = x3002 + x3003;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x3005 = x2893 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x3006 = x3005 + x2902;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3007 = x3004 + x3006;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3008 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x3009 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3010 = x3008 + x3009;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3011 = x3010 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x3012 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3007);
reg = x3007;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3011);
reg = x3011;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3012);
reg = x3012;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3012);
reg = x3012;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg4"("./cirgen/circuit/rv32im/rv32im.inl":80:46))
auto x3013 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x3013 != Fp::invalid());
if (x3013 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3014 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x3015 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3016 = x3014 + x3015;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x3017 = x2893 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x3018 = x3017 + x2902;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3019 = x3016 + x3018;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3020 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x3021 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3022 = x3020 + x3021;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3023 = x3022 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x3024 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3019);
reg = x3019;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3023);
reg = x3023;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3024);
reg = x3024;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3024);
reg = x3024;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg5"("./cirgen/circuit/rv32im/rv32im.inl":81:46))
auto x3025 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x3025 != Fp::invalid());
if (x3025 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3026 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":79:21)
auto x3027 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3028 = x3026 + x3027;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3029 = x2918 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":45:25)
auto x3030 = x2921 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3031 = x3029 + x3030;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3032 = x3031 + x2924;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3033 = x3028 + x3032;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3034 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":80:21)
auto x3035 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3036 = x3034 + x3035;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3037 = x3036 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":81:7)
auto x3038 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3033);
reg = x3033;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3037);
reg = x3037;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3038);
reg = x3038;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3038);
reg = x3038;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg6"("./cirgen/circuit/rv32im/rv32im.inl":82:46))
auto x3039 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x3039 != Fp::invalid());
if (x3039 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3040 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":79:21)
auto x3041 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3042 = x3040 + x3041;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3043 = x2918 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":45:25)
auto x3044 = x2921 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3045 = x3043 + x3044;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3046 = x3045 + x2924;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3047 = x3042 + x3046;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3048 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":80:21)
auto x3049 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3050 = x3048 + x3049;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3051 = x3050 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":81:7)
auto x3052 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3047);
reg = x3047;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3051);
reg = x3051;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3052);
reg = x3052;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3052);
reg = x3052;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg7"("./cirgen/circuit/rv32im/rv32im.inl":83:46))
auto x3053 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x3053 != Fp::invalid());
if (x3053 != 0) {
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3054 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":79:21)
auto x3055 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3056 = x3054 + x3055;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3057 = x2918 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":45:25)
auto x3058 = x2921 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3059 = x3057 + x3058;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3060 = x3059 + x2924;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3061 = x3056 + x3060;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3062 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":80:21)
auto x3063 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3064 = x3062 + x3063;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3065 = x3064 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":81:7)
auto x3066 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3061);
reg = x3061;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3065);
reg = x3065;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3066);
reg = x3066;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3066);
reg = x3066;
}
}
}
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x3067 = x2904 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":37:26)
auto x3068 = x2907 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x3069 = x3067 + x3068;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x3070 = x3069 + x2910;
// loc("cirgen/circuit/rv32im/memio.cpp":38:39)
auto x3071 = x3070 + x55;
{
host_args.at(0) = x3071;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x3072 = host_outs.at(0);
auto x3073 = host_outs.at(1);
auto x3074 = host_outs.at(2);
auto x3075 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3072);
reg = x3072;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3073);
reg = x3073;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3074);
reg = x3074;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3075);
reg = x3075;
}
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3076 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x3076 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3077 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x3077 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3078 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x3078 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3079 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x3079 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3071);
reg = x3071;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3076);
reg = x3076;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3077);
reg = x3077;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3078);
reg = x3078;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3079);
reg = x3079;
}
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x3080 = x2893 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x3081 = x3080 + x2902;
// loc("cirgen/circuit/rv32im/memio.cpp":39:39)
auto x3082 = x3081 + x55;
{
host_args.at(0) = x3082;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x3083 = host_outs.at(0);
auto x3084 = host_outs.at(1);
auto x3085 = host_outs.at(2);
auto x3086 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3083);
reg = x3083;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3084);
reg = x3084;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3085);
reg = x3085;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3086);
reg = x3086;
}
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3087 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x3087 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3088 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x3088 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3089 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x3089 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3090 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x3090 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3082);
reg = x3082;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3087);
reg = x3087;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3088);
reg = x3088;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3089);
reg = x3089;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3090);
reg = x3090;
}
// loc("Top/Mux/4/Mux/3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3091 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x3091 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3092 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x3092 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3093 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x3093 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3094 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x3094 != Fp::invalid());
host_args.at(0) = x3091;
host_args.at(1) = x3092;
host_args.at(2) = x3093;
host_args.at(3) = x3094;
host_args.at(4) = x3070;
host_args.at(5) = x3076;
host_args.at(6) = x3077;
host_args.at(7) = x3078;
host_args.at(8) = x3079;
host_args.at(9) = x3081;
host_args.at(10) = x3087;
host_args.at(11) = x3088;
host_args.at(12) = x3089;
host_args.at(13) = x3090;
host(ctx, "log", " imm=%w, rs1=x%u -> %w, rs2=x%u -> %w", host_args.data(), 14, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3095 = x2918 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":45:25)
auto x3096 = x2921 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3097 = x3095 + x3096;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3098 = x3097 + x2924;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x3099 = (x3098 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][198 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3099);
reg = x3099;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x3100 = inv(x3098);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][199 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3100);
reg = x3100;
}
}
// loc("Top/Mux/4/Mux/3/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3101 = args[2][198 * steps + ((cycle - 0) & mask)];
assert(x3101 != Fp::invalid());
if (x3101 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x3098 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x3102 = x102 - x3101;
if (x3102 != 0) {
// loc("Top/Mux/4/Mux/3/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3103 = args[2][199 * steps + ((cycle - 0) & mask)];
assert(x3103 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x3104 = x3098 * x3103;
// loc("cirgen/components/iszero.cpp":15:26)
auto x3105 = x3104 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x3105 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
{
// loc("cirgen/circuit/rv32im/memio.cpp":48:17)
auto x3106 = x3076 + x3091;
// loc("cirgen/circuit/rv32im/memio.cpp":49:18)
auto x3107 = Fp(x3106.asUInt32() & x84.asUInt32());
{
// loc("./cirgen/components/onehot.h":35:26)
auto x3108 = (x3107 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][200 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3108);
reg = x3108;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x3109 = x3107 - x102;
// loc("./cirgen/components/onehot.h":35:26)
auto x3110 = (x3109 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][201 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3110);
reg = x3110;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x3111 = x3107 - x99;
// loc("./cirgen/components/onehot.h":35:26)
auto x3112 = (x3111 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][202 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3112);
reg = x3112;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x3113 = x3107 - x84;
// loc("./cirgen/components/onehot.h":35:26)
auto x3114 = (x3113 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][203 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3114);
reg = x3114;
}
}
// loc("Top/Mux/4/Mux/3/OneHot1/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3115 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x3115 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/OneHot1/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3116 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x3116 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x3117 = x3116 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x3118 = x3115 + x3117;
// loc("Top/Mux/4/Mux/3/OneHot1/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3119 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x3119 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x3120 = x3119 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x3121 = x3118 + x3120;
// loc("./cirgen/components/onehot.h":38:8)
auto x3122 = x3121 - x3107;
// loc("./cirgen/components/onehot.h":38:8)
if (x3122 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
// loc("cirgen/circuit/rv32im/memio.cpp":50:20)
auto x3123 = Fp(x3106.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/memio.cpp":50:19)
auto x3124 = x3123 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3125 = Fp(x3124.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3125);
reg = x3125;
}
}
// loc("cirgen/circuit/rv32im/memio.cpp":51:15)
auto x3126 = x3106 - x3121;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3127 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x3127 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":51:33)
auto x3128 = x3127 * x97;
// loc("cirgen/circuit/rv32im/memio.cpp":51:15)
auto x3129 = x3126 - x3128;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3129);
reg = x3129;
}
// loc("cirgen/circuit/rv32im/memio.cpp":53:22)
auto x3130 = x3129 * x83;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3130);
reg = x3130;
}
// loc("cirgen/circuit/rv32im/memio.cpp":54:17)
auto x3131 = x3077 + x3092;
// loc("cirgen/circuit/rv32im/memio.cpp":54:17)
auto x3132 = x3131 + x3127;
// loc("cirgen/circuit/rv32im/memio.cpp":55:24)
auto x3133 = Fp(x3132.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3133);
reg = x3133;
}
// loc("cirgen/circuit/rv32im/memio.cpp":56:25)
auto x3134 = Fp(x3132.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/memio.cpp":56:24)
auto x3135 = x3134 * x96;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3135);
reg = x3135;
}
// loc("cirgen/circuit/rv32im/memio.cpp":57:17)
auto x3136 = x3078 + x3093;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x3137 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x3137 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":57:17)
auto x3138 = x3136 + x3137;
// loc("cirgen/circuit/rv32im/memio.cpp":58:24)
auto x3139 = Fp(x3138.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3139);
reg = x3139;
}
// loc("cirgen/circuit/rv32im/memio.cpp":59:25)
auto x3140 = Fp(x3138.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/memio.cpp":59:24)
auto x3141 = x3140 * x96;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3141);
reg = x3141;
}
// loc("cirgen/circuit/rv32im/memio.cpp":60:17)
auto x3142 = x3079 + x3094;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3143 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x3143 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":60:17)
auto x3144 = x3142 + x3143;
// loc("cirgen/circuit/rv32im/memio.cpp":61:23)
auto x3145 = Fp(x3144.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3145);
reg = x3145;
}
// loc("cirgen/circuit/rv32im/memio.cpp":62:24)
auto x3146 = Fp(x3144.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/memio.cpp":62:23)
auto x3147 = x3146 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3147);
reg = x3147;
}
// loc("cirgen/circuit/rv32im/memio.cpp":63:20)
auto x3148 = Fp(x3144.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/memio.cpp":63:19)
auto x3149 = x3148 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3150 = Fp(x3149.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3150);
reg = x3150;
}
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3151 = args[2][32 * steps + ((cycle - 0) & mask)];
assert(x3151 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x3152 = args[2][35 * steps + ((cycle - 0) & mask)];
assert(x3152 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":66:16)
auto x3153 = x3152 * x85;
// loc("cirgen/circuit/rv32im/memio.cpp":66:6)
auto x3154 = x3151 - x3153;
// loc("cirgen/circuit/rv32im/memio.cpp":66:6)
if (x3154 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/memio.cpp:66");
// loc("cirgen/circuit/rv32im/memio.cpp":68:6)
auto x3155 = x3076 + x3091;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3156 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x3156 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":68:35)
auto x3157 = x3156 * x97;
// loc("cirgen/circuit/rv32im/memio.cpp":68:35)
auto x3158 = x3157 + x3151;
// loc("Top/Mux/4/Mux/3/OneHot1/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3159 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x3159 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/OneHot1/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3160 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x3160 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x3161 = x3160 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x3162 = x3159 + x3161;
// loc("Top/Mux/4/Mux/3/OneHot1/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3163 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x3163 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x3164 = x3163 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x3165 = x3162 + x3164;
// loc("cirgen/circuit/rv32im/memio.cpp":68:35)
auto x3166 = x3158 + x3165;
// loc("cirgen/circuit/rv32im/memio.cpp":68:6)
auto x3167 = x3155 - x3166;
// loc("cirgen/circuit/rv32im/memio.cpp":68:6)
if (x3167 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/memio.cpp:68");
// loc("cirgen/circuit/rv32im/memio.cpp":70:6)
auto x3168 = x3077 + x3092;
// loc("cirgen/circuit/rv32im/memio.cpp":70:6)
auto x3169 = x3168 + x3156;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x3170 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x3170 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":70:46)
auto x3171 = x3170 * x97;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x3172 = args[2][33 * steps + ((cycle - 0) & mask)];
assert(x3172 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":70:46)
auto x3173 = x3171 + x3172;
// loc("cirgen/circuit/rv32im/memio.cpp":70:6)
auto x3174 = x3169 - x3173;
// loc("cirgen/circuit/rv32im/memio.cpp":70:6)
if (x3174 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/memio.cpp:70");
// loc("cirgen/circuit/rv32im/memio.cpp":72:6)
auto x3175 = x3078 + x3093;
// loc("cirgen/circuit/rv32im/memio.cpp":72:6)
auto x3176 = x3175 + x3170;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3177 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x3177 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":72:46)
auto x3178 = x3177 * x97;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3179 = args[2][34 * steps + ((cycle - 0) & mask)];
assert(x3179 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":72:46)
auto x3180 = x3178 + x3179;
// loc("cirgen/circuit/rv32im/memio.cpp":72:6)
auto x3181 = x3176 - x3180;
// loc("cirgen/circuit/rv32im/memio.cpp":72:6)
if (x3181 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/memio.cpp:72");
// loc("cirgen/circuit/rv32im/memio.cpp":74:6)
auto x3182 = x3079 + x3094;
// loc("cirgen/circuit/rv32im/memio.cpp":74:6)
auto x3183 = x3182 + x3177;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x3184 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x3184 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":74:46)
auto x3185 = x3184 * x97;
// loc("Top/Mux/4/Mux/3/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3186 = args[2][88 * steps + ((cycle - 0) & mask)];
assert(x3186 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":74:63)
auto x3187 = x3186 * x85;
// loc("cirgen/circuit/rv32im/memio.cpp":74:46)
auto x3188 = x3185 + x3187;
// loc("Top/Mux/4/Mux/3/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3189 = args[2][87 * steps + ((cycle - 0) & mask)];
assert(x3189 != Fp::invalid());
// loc("cirgen/circuit/rv32im/memio.cpp":74:46)
auto x3190 = x3188 + x3189;
// loc("cirgen/circuit/rv32im/memio.cpp":74:6)
auto x3191 = x3183 - x3190;
// loc("cirgen/circuit/rv32im/memio.cpp":74:6)
if (x3191 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/memio.cpp:74");
// loc("cirgen/circuit/rv32im/memio.cpp":77:15)
auto x3192 = x102 - x3186;
// loc("cirgen/circuit/rv32im/memio.cpp":77:7)
auto x3193 = x3186 * x3192;
// loc("cirgen/circuit/rv32im/memio.cpp":77:28)
auto x3194 = x99 - x3186;
// loc("cirgen/circuit/rv32im/memio.cpp":77:7)
auto x3195 = x3193 * x3194;
// loc("cirgen/circuit/rv32im/memio.cpp":77:7)
if (x3195 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/memio.cpp:77");
// loc("cirgen/circuit/rv32im/memio.cpp":80:14)
auto x3196 = x3186 * x86;
// loc("cirgen/circuit/rv32im/memio.cpp":80:41)
auto x3197 = x3189 * x44;
// loc("cirgen/circuit/rv32im/memio.cpp":80:14)
auto x3198 = x3196 + x3197;
// loc("cirgen/circuit/rv32im/memio.cpp":80:68)
auto x3199 = x3179 * x43;
// loc("cirgen/circuit/rv32im/memio.cpp":80:14)
auto x3200 = x3198 + x3199;
// loc("cirgen/circuit/rv32im/memio.cpp":81:14)
auto x3201 = x3172 * x62;
// loc("cirgen/circuit/rv32im/memio.cpp":80:14)
auto x3202 = x3200 + x3201;
// loc("cirgen/circuit/rv32im/memio.cpp":80:14)
auto x3203 = x3202 + x3152;
{
host_args.at(0) = x3203;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x3204 = host_outs.at(0);
auto x3205 = host_outs.at(1);
auto x3206 = host_outs.at(2);
auto x3207 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3204);
reg = x3204;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3205);
reg = x3205;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3206);
reg = x3206;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3207);
reg = x3207;
}
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3208 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x3208 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3209 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x3209 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3210 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x3210 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3211 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x3211 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3203);
reg = x3203;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3208);
reg = x3208;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3209);
reg = x3209;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3210);
reg = x3210;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3211);
reg = x3211;
}
host_args.at(0) = x3203;
host_args.at(1) = x3165;
host_args.at(2) = x3208;
host_args.at(3) = x3209;
host_args.at(4) = x3210;
host_args.at(5) = x3211;
host(ctx, "log", " Addr = 0x%x, lowBits = %u, loaded = %w", host_args.data(), 6, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/memio.cpp":85:17)
auto x3212 = x603 + x85;
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x3213 = x3212 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3214 = Fp(x3213.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3214);
reg = x3214;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x3215 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x3215 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3216 = x3213 - x3215;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3217 = x3216 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3218 = Fp(x3217.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3218);
reg = x3218;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x3219 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x3219 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3220 = x3217 - x3219;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3221 = x3220 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3222 = Fp(x3221.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3222);
reg = x3222;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x3223 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x3223 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3224 = x3221 - x3223;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3225 = x3224 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x3226 = Fp(x3225.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3226);
reg = x3226;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3227 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x3227 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x3228 = x3225 - x3227;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x3229 = x3228 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3229);
reg = x3229;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3230 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x3230 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x3231 = x102 - x3230;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x3232 = x3230 * x3231;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3232);
reg = x3232;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3233 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x3233 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x3234 = x99 - x3230;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x3235 = x3233 * x3234;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x3235 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("cirgen/circuit/rv32im/memio.cpp":86:3)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg"("./cirgen/circuit/rv32im/rv32im.inl":76:46))
auto x3236 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x3236 != Fp::invalid());
if (x3236 != 0) {
if (x101 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":76:46))
auto x3237 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3237 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3238 = x3237 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
if (x3238 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:76");
}
if (x101 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":76:46))
auto x3239 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3239 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3240 = x3239 + x3160;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3241 = x3240 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
if (x3241 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:76");
}
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":76:46))
auto x3242 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3242 != Fp::invalid());
if (x3242 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3243 = Fp(x3208.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3243);
reg = x3243;
}
}
}
if (x3159 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3244 = Fp(x3209.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3244);
reg = x3244;
}
}
}
if (x3160 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3245 = Fp(x3210.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3245);
reg = x3245;
}
}
}
if (x3163 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3246 = Fp(x3211.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3246);
reg = x3246;
}
}
}
{
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3247 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x3247 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3248 = Fp(x3247.asUInt32() & x71.asUInt32());
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3249 = x3248 * x70;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3249);
reg = x3249;
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3250 = Fp(x3247.asUInt32() & x59.asUInt32());
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3251 = x3250 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3251);
reg = x3251;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x3252 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x3252 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3253 = x102 - x3252;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3254 = x3252 * x3253;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
if (x3254 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:76");
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3255 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x3255 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3256 = x3252 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3257 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x3257 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3258 = x3257 * x63;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3259 = x3256 + x3258;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3260 = x3255 - x3259;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
if (x3260 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:76");
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3261 = x3252 * x98;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3262 = x3242 * x3208;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3263 = x3159 * x3209;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3264 = x3262 + x3263;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3265 = x3160 * x3210;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3266 = x3264 + x3265;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3267 = x3163 * x3211;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3268 = x3266 + x3267;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3268);
reg = x3268;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3261);
reg = x3261;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3261);
reg = x3261;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3261);
reg = x3261;
}
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3269 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x3269 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3270 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x3270 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3271 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x3271 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3272 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x3272 != Fp::invalid());
host_args.at(0) = x3261;
host_args.at(1) = x3269;
host_args.at(2) = x3270;
host_args.at(3) = x3271;
host_args.at(4) = x3272;
host(ctx, "log", " fillByte = %x, extended: %w", host_args.data(), 5, host_outs.data(), 0);
if (x3102 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3273 = x3098 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3269);
reg = x3269;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3270);
reg = x3270;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3271);
reg = x3271;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3272);
reg = x3272;
}
{
host_args.at(0) = x3273;
host_args.at(1) = x3269;
host_args.at(2) = x3270;
host_args.at(3) = x3271;
host_args.at(4) = x3272;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3274 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x3274 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3275 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x3275 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3276 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x3276 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3277 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x3277 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3273);
reg = x3273;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3274);
reg = x3274;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3275);
reg = x3275;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3276);
reg = x3276;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3277);
reg = x3277;
}
}
if (x3101 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
auto x3278 = x2926 - x84;
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
if (x3278 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:76");
// loc("./cirgen/circuit/rv32im/rv32im.inl":76:46)
if (x2915 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:76");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3279 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x3280 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3281 = x3279 + x3280;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3282 = x3281 + x3081;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3283 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x3284 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3285 = x3283 + x3284;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3286 = x3285 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x3287 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3282);
reg = x3282;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3286);
reg = x3286;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3287);
reg = x3287;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3287);
reg = x3287;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg1"("./cirgen/circuit/rv32im/rv32im.inl":77:46))
auto x3288 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x3288 != Fp::invalid());
if (x3288 != 0) {
if (x101 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":77:46))
auto x3289 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3289 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3290 = x3289 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
if (x3290 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:77");
}
if (x102 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":77:46))
auto x3291 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3291 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3292 = x3291 + x3160;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3293 = x3292 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
if (x3293 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:77");
}
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":77:46))
auto x3294 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3294 != Fp::invalid());
if (x3294 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3295 = Fp(x3209.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3295);
reg = x3295;
}
}
}
if (x3160 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3296 = Fp(x3211.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3296);
reg = x3296;
}
}
}
{
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3297 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x3297 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3298 = Fp(x3297.asUInt32() & x71.asUInt32());
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3299 = x3298 * x70;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3299);
reg = x3299;
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3300 = Fp(x3297.asUInt32() & x59.asUInt32());
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3301 = x3300 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3301);
reg = x3301;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x3302 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x3302 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3303 = x102 - x3302;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3304 = x3302 * x3303;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
if (x3304 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:77");
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3305 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x3305 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3306 = x3302 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3307 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x3307 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3308 = x3307 * x63;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3309 = x3306 + x3308;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3310 = x3305 - x3309;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
if (x3310 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:77");
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3311 = x3302 * x98;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3312 = x3294 * x3208;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3313 = x3160 * x3210;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3314 = x3312 + x3313;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3315 = x3294 * x3209;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3316 = x3160 * x3211;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3317 = x3315 + x3316;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3314);
reg = x3314;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3317);
reg = x3317;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3311);
reg = x3311;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3311);
reg = x3311;
}
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3318 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x3318 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3319 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x3319 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3320 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x3320 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3321 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x3321 != Fp::invalid());
host_args.at(0) = x3311;
host_args.at(1) = x3318;
host_args.at(2) = x3319;
host_args.at(3) = x3320;
host_args.at(4) = x3321;
host(ctx, "log", " fillByte = %x, extended: %w", host_args.data(), 5, host_outs.data(), 0);
if (x3102 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3322 = x3098 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3318);
reg = x3318;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3319);
reg = x3319;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3320);
reg = x3320;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3321);
reg = x3321;
}
{
host_args.at(0) = x3322;
host_args.at(1) = x3318;
host_args.at(2) = x3319;
host_args.at(3) = x3320;
host_args.at(4) = x3321;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3323 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x3323 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3324 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x3324 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3325 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x3325 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3326 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x3326 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3322);
reg = x3322;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3323);
reg = x3323;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3324);
reg = x3324;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3325);
reg = x3325;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3326);
reg = x3326;
}
}
if (x3101 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3327 = x2926 - x84;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
if (x3327 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:77");
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
auto x3328 = x2915 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":77:46)
if (x3328 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:77");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3329 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x3330 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3331 = x3329 + x3330;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3332 = x3331 + x3081;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3333 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x3334 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3335 = x3333 + x3334;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3336 = x3335 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x3337 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3332);
reg = x3332;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3336);
reg = x3336;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3337);
reg = x3337;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3337);
reg = x3337;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg2"("./cirgen/circuit/rv32im/rv32im.inl":78:46))
auto x3338 = args[2][192 * steps + ((cycle - 0) & mask)];
assert(x3338 != Fp::invalid());
if (x3338 != 0) {
if (x102 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":78:46))
auto x3339 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3339 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3340 = x3339 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
if (x3340 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:78");
}
if (x101 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":78:46))
auto x3341 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3341 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3342 = x3341 + x3160;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3343 = x3342 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
if (x3343 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:78");
}
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":78:46))
auto x3344 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3344 != Fp::invalid());
if (x3344 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3345 = Fp(x3211.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3345);
reg = x3345;
}
}
}
{
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3346 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x3346 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3347 = Fp(x3346.asUInt32() & x71.asUInt32());
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3348 = x3347 * x70;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3348);
reg = x3348;
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3349 = Fp(x3346.asUInt32() & x59.asUInt32());
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3350 = x3349 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3350);
reg = x3350;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x3351 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x3351 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3352 = x102 - x3351;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3353 = x3351 * x3352;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
if (x3353 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:78");
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3354 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x3354 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3355 = x3351 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3356 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x3356 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3357 = x3356 * x63;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3358 = x3355 + x3357;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3359 = x3354 - x3358;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
if (x3359 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:78");
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3360 = x3344 * x3208;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3361 = x3344 * x3209;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3362 = x3344 * x3210;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3363 = x3344 * x3211;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3360);
reg = x3360;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3361);
reg = x3361;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3362);
reg = x3362;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3363);
reg = x3363;
}
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3364 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x3364 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3365 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x3365 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3366 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x3366 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3367 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x3367 != Fp::invalid());
host_args.at(0) = x101;
host_args.at(1) = x3364;
host_args.at(2) = x3365;
host_args.at(3) = x3366;
host_args.at(4) = x3367;
host(ctx, "log", " fillByte = %x, extended: %w", host_args.data(), 5, host_outs.data(), 0);
if (x3102 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3368 = x3098 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3364);
reg = x3364;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3365);
reg = x3365;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3366);
reg = x3366;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3367);
reg = x3367;
}
{
host_args.at(0) = x3368;
host_args.at(1) = x3364;
host_args.at(2) = x3365;
host_args.at(3) = x3366;
host_args.at(4) = x3367;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3369 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x3369 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3370 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x3370 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3371 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x3371 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3372 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x3372 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3368);
reg = x3368;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3369);
reg = x3369;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3370);
reg = x3370;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3371);
reg = x3371;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3372);
reg = x3372;
}
}
if (x3101 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3373 = x2926 - x84;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
if (x3373 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:78");
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
auto x3374 = x2915 - x99;
// loc("./cirgen/circuit/rv32im/rv32im.inl":78:46)
if (x3374 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:78");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3375 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x3376 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3377 = x3375 + x3376;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3378 = x3377 + x3081;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3379 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x3380 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3381 = x3379 + x3380;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3382 = x3381 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x3383 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3378);
reg = x3378;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3382);
reg = x3382;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3383);
reg = x3383;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3383);
reg = x3383;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg3"("./cirgen/circuit/rv32im/rv32im.inl":79:46))
auto x3384 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x3384 != Fp::invalid());
if (x3384 != 0) {
if (x101 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":79:46))
auto x3385 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3385 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3386 = x3385 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
if (x3386 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:79");
}
if (x101 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":79:46))
auto x3387 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3387 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3388 = x3387 + x3160;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3389 = x3388 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
if (x3389 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:79");
}
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":79:46))
auto x3390 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3390 != Fp::invalid());
if (x3390 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3391 = Fp(x3208.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3391);
reg = x3391;
}
}
}
if (x3159 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3392 = Fp(x3209.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3392);
reg = x3392;
}
}
}
if (x3160 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3393 = Fp(x3210.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3393);
reg = x3393;
}
}
}
if (x3163 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3394 = Fp(x3211.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3394);
reg = x3394;
}
}
}
{
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3395 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x3395 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3396 = Fp(x3395.asUInt32() & x71.asUInt32());
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3397 = x3396 * x70;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3397);
reg = x3397;
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3398 = Fp(x3395.asUInt32() & x59.asUInt32());
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3399 = x3398 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3399);
reg = x3399;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x3400 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x3400 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3401 = x102 - x3400;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3402 = x3400 * x3401;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
if (x3402 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:79");
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3403 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x3403 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3404 = x3400 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3405 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x3405 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3406 = x3405 * x63;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3407 = x3404 + x3406;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3408 = x3403 - x3407;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
if (x3408 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:79");
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3409 = x3390 * x3208;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3410 = x3159 * x3209;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3411 = x3409 + x3410;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3412 = x3160 * x3210;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3413 = x3411 + x3412;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3414 = x3163 * x3211;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3415 = x3413 + x3414;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3415);
reg = x3415;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3416 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x3416 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3417 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x3417 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3418 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x3418 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3419 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x3419 != Fp::invalid());
host_args.at(0) = x101;
host_args.at(1) = x3416;
host_args.at(2) = x3417;
host_args.at(3) = x3418;
host_args.at(4) = x3419;
host(ctx, "log", " fillByte = %x, extended: %w", host_args.data(), 5, host_outs.data(), 0);
if (x3102 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3420 = x3098 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3416);
reg = x3416;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3417);
reg = x3417;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3418);
reg = x3418;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3419);
reg = x3419;
}
{
host_args.at(0) = x3420;
host_args.at(1) = x3416;
host_args.at(2) = x3417;
host_args.at(3) = x3418;
host_args.at(4) = x3419;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3421 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x3421 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3422 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x3422 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3423 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x3423 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3424 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x3424 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3420);
reg = x3420;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3421);
reg = x3421;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3422);
reg = x3422;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3423);
reg = x3423;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3424);
reg = x3424;
}
}
if (x3101 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3425 = x2926 - x84;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
if (x3425 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:79");
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
auto x3426 = x2915 - x85;
// loc("./cirgen/circuit/rv32im/rv32im.inl":79:46)
if (x3426 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:79");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3427 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x3428 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3429 = x3427 + x3428;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3430 = x3429 + x3081;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3431 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x3432 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3433 = x3431 + x3432;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3434 = x3433 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x3435 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3430);
reg = x3430;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3434);
reg = x3434;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3435);
reg = x3435;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3435);
reg = x3435;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg4"("./cirgen/circuit/rv32im/rv32im.inl":80:46))
auto x3436 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x3436 != Fp::invalid());
if (x3436 != 0) {
if (x101 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":80:46))
auto x3437 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3437 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3438 = x3437 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
if (x3438 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:80");
}
if (x102 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":80:46))
auto x3439 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3439 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3440 = x3439 + x3160;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3441 = x3440 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
if (x3441 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:80");
}
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":80:46))
auto x3442 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3442 != Fp::invalid());
if (x3442 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3443 = Fp(x3209.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3443);
reg = x3443;
}
}
}
if (x3160 != 0) {
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3444 = Fp(x3211.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3444);
reg = x3444;
}
}
}
{
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3445 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x3445 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3446 = Fp(x3445.asUInt32() & x71.asUInt32());
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3447 = x3446 * x70;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3447);
reg = x3447;
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3448 = Fp(x3445.asUInt32() & x59.asUInt32());
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3449 = x3448 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3449);
reg = x3449;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x3450 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x3450 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3451 = x102 - x3450;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3452 = x3450 * x3451;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
if (x3452 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:80");
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3453 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x3453 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3454 = x3450 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3455 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x3455 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3456 = x3455 * x63;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3457 = x3454 + x3456;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3458 = x3453 - x3457;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
if (x3458 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:80");
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3459 = x3442 * x3208;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3460 = x3160 * x3210;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3461 = x3459 + x3460;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3462 = x3442 * x3209;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3463 = x3160 * x3211;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3464 = x3462 + x3463;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3461);
reg = x3461;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3464);
reg = x3464;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3465 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x3465 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3466 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x3466 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3467 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x3467 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/U32Reg1/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3468 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x3468 != Fp::invalid());
host_args.at(0) = x101;
host_args.at(1) = x3465;
host_args.at(2) = x3466;
host_args.at(3) = x3467;
host_args.at(4) = x3468;
host(ctx, "log", " fillByte = %x, extended: %w", host_args.data(), 5, host_outs.data(), 0);
if (x3102 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3469 = x3098 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3465);
reg = x3465;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3466);
reg = x3466;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3467);
reg = x3467;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3468);
reg = x3468;
}
{
host_args.at(0) = x3469;
host_args.at(1) = x3465;
host_args.at(2) = x3466;
host_args.at(3) = x3467;
host_args.at(4) = x3468;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3470 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x3470 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3471 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x3471 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3472 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x3472 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3473 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x3473 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3469);
reg = x3469;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3470);
reg = x3470;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3471);
reg = x3471;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3472);
reg = x3472;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3473);
reg = x3473;
}
}
if (x3101 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3474 = x2926 - x84;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
if (x3474 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:80");
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
auto x3475 = x2915 - x80;
// loc("./cirgen/circuit/rv32im/rv32im.inl":80:46)
if (x3475 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:80");
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3476 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x3477 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3478 = x3476 + x3477;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3479 = x3478 + x3081;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3480 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":71:21)
auto x3481 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3482 = x3480 + x3481;
// loc("cirgen/circuit/rv32im/decode.cpp":71:7)
auto x3483 = x3482 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":72:7)
auto x3484 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3479);
reg = x3479;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3483);
reg = x3483;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3484);
reg = x3484;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3484);
reg = x3484;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg5"("./cirgen/circuit/rv32im/rv32im.inl":81:46))
auto x3485 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x3485 != Fp::invalid());
if (x3485 != 0) {
if (x101 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":81:46))
auto x3486 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3486 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3487 = x3486 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
if (x3487 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:81");
}
if (x101 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":81:46))
auto x3488 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3488 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3489 = x3488 + x3160;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3490 = x3489 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
if (x3490 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:81");
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":81:46))
auto x3491 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3491 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3492 = x3491 * x3087;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3493 = x102 - x3491;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3494 = x3493 * x3208;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3495 = x3492 + x3494;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3496 = x3159 * x3087;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3497 = x102 - x3159;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3498 = x3497 * x3209;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3499 = x3496 + x3498;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3500 = x3160 * x3087;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3501 = x102 - x3160;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3502 = x3501 * x3210;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3503 = x3500 + x3502;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3504 = x3163 * x3087;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3505 = x102 - x3163;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3506 = x3505 * x3211;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3507 = x3504 + x3506;
host_args.at(0) = x3495;
host_args.at(1) = x3499;
host_args.at(2) = x3503;
host_args.at(3) = x3507;
host(ctx, "log", " writeVal = %w", host_args.data(), 4, host_outs.data(), 0);
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3495);
reg = x3495;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3499);
reg = x3499;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3503);
reg = x3503;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3507);
reg = x3507;
}
{
host_args.at(0) = x3203;
host_args.at(1) = x3495;
host_args.at(2) = x3499;
host_args.at(3) = x3503;
host_args.at(4) = x3507;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3508 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x3508 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3509 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x3509 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3510 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x3510 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3511 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x3511 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3203);
reg = x3203;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3508);
reg = x3508;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3509);
reg = x3509;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3510);
reg = x3510;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3511);
reg = x3511;
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
auto x3512 = x2926 - x42;
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
if (x3512 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:81");
// loc("./cirgen/circuit/rv32im/rv32im.inl":81:46)
if (x2915 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:81");
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3513 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":79:21)
auto x3514 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3515 = x3513 + x3514;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3516 = x3515 + x3098;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3517 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":80:21)
auto x3518 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3519 = x3517 + x3518;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3520 = x3519 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":81:7)
auto x3521 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3516);
reg = x3516;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3520);
reg = x3520;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3521);
reg = x3521;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3521);
reg = x3521;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg6"("./cirgen/circuit/rv32im/rv32im.inl":82:46))
auto x3522 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x3522 != Fp::invalid());
if (x3522 != 0) {
if (x101 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":82:46))
auto x3523 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3523 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3524 = x3523 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
if (x3524 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:82");
}
if (x102 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":82:46))
auto x3525 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3525 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3526 = x3525 + x3160;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3527 = x3526 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
if (x3527 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:82");
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":82:46))
auto x3528 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3528 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3529 = x3528 * x3087;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3530 = x102 - x3528;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3531 = x3530 * x3208;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3532 = x3529 + x3531;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3533 = x3160 * x3087;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3534 = x102 - x3160;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3535 = x3534 * x3210;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3536 = x3533 + x3535;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3537 = x3528 * x3088;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3538 = x3530 * x3209;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3539 = x3537 + x3538;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3540 = x3160 * x3088;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3541 = x3534 * x3211;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3542 = x3540 + x3541;
host_args.at(0) = x3532;
host_args.at(1) = x3539;
host_args.at(2) = x3536;
host_args.at(3) = x3542;
host(ctx, "log", " writeVal = %w", host_args.data(), 4, host_outs.data(), 0);
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3532);
reg = x3532;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3539);
reg = x3539;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3536);
reg = x3536;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3542);
reg = x3542;
}
{
host_args.at(0) = x3203;
host_args.at(1) = x3532;
host_args.at(2) = x3539;
host_args.at(3) = x3536;
host_args.at(4) = x3542;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3543 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x3543 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3544 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x3544 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3545 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x3545 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3546 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x3546 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3203);
reg = x3203;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3543);
reg = x3543;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3544);
reg = x3544;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3545);
reg = x3545;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3546);
reg = x3546;
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3547 = x2926 - x42;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
if (x3547 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:82");
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
auto x3548 = x2915 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":82:46)
if (x3548 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:82");
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3549 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":79:21)
auto x3550 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3551 = x3549 + x3550;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3552 = x3551 + x3098;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3553 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":80:21)
auto x3554 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3555 = x3553 + x3554;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3556 = x3555 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":81:7)
auto x3557 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3552);
reg = x3552;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3556);
reg = x3556;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3557);
reg = x3557;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3557);
reg = x3557;
}
}
// loc("Top/Mux/4/Mux/3/OneHot/Reg7"("./cirgen/circuit/rv32im/rv32im.inl":83:46))
auto x3558 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x3558 != Fp::invalid());
if (x3558 != 0) {
if (x102 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":83:46))
auto x3559 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3559 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3560 = x3559 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
if (x3560 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:83");
}
if (x101 != 0) {
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":83:46))
auto x3561 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3561 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3562 = x3561 + x3160;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3563 = x3562 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
if (x3563 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:83");
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("Top/Mux/4/Mux/3/OneHot1/Reg"("./cirgen/circuit/rv32im/rv32im.inl":83:46))
auto x3564 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3564 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3565 = x3564 * x3087;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3566 = x102 - x3564;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3567 = x3566 * x3208;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3568 = x3565 + x3567;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3569 = x3564 * x3088;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3570 = x3566 * x3209;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3571 = x3569 + x3570;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3572 = x3564 * x3089;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3573 = x3566 * x3210;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3574 = x3572 + x3573;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3575 = x3564 * x3090;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3576 = x3566 * x3211;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3577 = x3575 + x3576;
host_args.at(0) = x3568;
host_args.at(1) = x3571;
host_args.at(2) = x3574;
host_args.at(3) = x3577;
host(ctx, "log", " writeVal = %w", host_args.data(), 4, host_outs.data(), 0);
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3568);
reg = x3568;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3571);
reg = x3571;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3574);
reg = x3574;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3577);
reg = x3577;
}
{
host_args.at(0) = x3203;
host_args.at(1) = x3568;
host_args.at(2) = x3571;
host_args.at(3) = x3574;
host_args.at(4) = x3577;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3578 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x3578 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3579 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x3579 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3580 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x3580 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3581 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x3581 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3203);
reg = x3203;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2837);
reg = x2837;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3578);
reg = x3578;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3579);
reg = x3579;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3580);
reg = x3580;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3581);
reg = x3581;
}
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3582 = x2926 - x42;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
if (x3582 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:83");
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
auto x3583 = x2915 - x99;
// loc("./cirgen/circuit/rv32im/rv32im.inl":83:46)
if (x3583 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:83");
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3584 = x2886 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":79:21)
auto x3585 = x2889 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3586 = x3584 + x3585;
// loc("cirgen/circuit/rv32im/decode.cpp":79:7)
auto x3587 = x3586 + x3098;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3588 = x2879 * x56;
// loc("cirgen/circuit/rv32im/decode.cpp":80:21)
auto x3589 = x2881 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3590 = x3588 + x3589;
// loc("cirgen/circuit/rv32im/decode.cpp":80:7)
auto x3591 = x3590 + x2883;
// loc("cirgen/circuit/rv32im/decode.cpp":81:7)
auto x3592 = x2879 * x98;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3587);
reg = x3587;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3591);
reg = x3591;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3592);
reg = x3592;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3592);
reg = x3592;
}
}
}
// loc("Top/Mux/4/OneHot/Reg4"("./cirgen/components/mux.h":37:25))
auto x3593 = args[2][98 * steps + ((cycle - 0) & mask)];
assert(x3593 != Fp::invalid());
if (x3593 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3594 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x3594 != Fp::invalid());
// loc("cirgen/circuit/rv32im/multiply.cpp":20:41)
auto x3595 = x603 * x83;
{
host_args.at(0) = x3595;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x3596 = host_outs.at(0);
auto x3597 = host_outs.at(1);
auto x3598 = host_outs.at(2);
auto x3599 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3596);
reg = x3596;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3597);
reg = x3597;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3598);
reg = x3598;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3599);
reg = x3599;
}
}
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3600 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x3600 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3601 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x3601 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3602 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x3602 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3603 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x3603 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3595);
reg = x3595;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3594);
reg = x3594;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3600);
reg = x3600;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3601);
reg = x3601;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3602);
reg = x3602;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3603);
reg = x3603;
}
{
// loc("cirgen/circuit/rv32im/decode.cpp":11:16)
auto x3604 = Fp(x3603.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":11:15)
auto x3605 = x3604 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3605);
reg = x3605;
}
// loc("cirgen/circuit/rv32im/decode.cpp":12:17)
auto x3606 = Fp(x3603.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":12:16)
auto x3607 = x3606 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3607);
reg = x3607;
}
// loc("cirgen/circuit/rv32im/decode.cpp":13:16)
auto x3608 = Fp(x3603.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":13:15)
auto x3609 = x3608 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3609);
reg = x3609;
}
// loc("cirgen/circuit/rv32im/decode.cpp":14:16)
auto x3610 = Fp(x3603.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":14:15)
auto x3611 = x3610 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3611);
reg = x3611;
}
// loc("cirgen/circuit/rv32im/decode.cpp":15:17)
auto x3612 = Fp(x3603.asUInt32() & x79.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":15:16)
auto x3613 = x3612 * x63;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3613);
reg = x3613;
}
// loc("cirgen/circuit/rv32im/decode.cpp":16:17)
auto x3614 = Fp(x3603.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3614);
reg = x3614;
}
// loc("cirgen/circuit/rv32im/decode.cpp":17:17)
auto x3615 = Fp(x3602.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":17:16)
auto x3616 = x3615 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3616);
reg = x3616;
}
// loc("cirgen/circuit/rv32im/decode.cpp":18:18)
auto x3617 = Fp(x3602.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":18:17)
auto x3618 = x3617 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3618);
reg = x3618;
}
// loc("cirgen/circuit/rv32im/decode.cpp":19:17)
auto x3619 = Fp(x3602.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":19:16)
auto x3620 = x3619 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3620);
reg = x3620;
}
// loc("cirgen/circuit/rv32im/decode.cpp":20:18)
auto x3621 = Fp(x3602.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":20:17)
auto x3622 = x3621 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3622);
reg = x3622;
}
// loc("cirgen/circuit/rv32im/decode.cpp":21:18)
auto x3623 = Fp(x3602.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3623);
reg = x3623;
}
// loc("cirgen/circuit/rv32im/decode.cpp":22:17)
auto x3624 = Fp(x3601.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":22:16)
auto x3625 = x3624 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3625);
reg = x3625;
}
// loc("cirgen/circuit/rv32im/decode.cpp":23:19)
auto x3626 = Fp(x3601.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":23:18)
auto x3627 = x3626 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3627);
reg = x3627;
}
// loc("cirgen/circuit/rv32im/decode.cpp":24:20)
auto x3628 = Fp(x3601.asUInt32() & x60.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":24:19)
auto x3629 = x3628 * x65;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3629);
reg = x3629;
}
// loc("cirgen/circuit/rv32im/decode.cpp":25:17)
auto x3630 = Fp(x3601.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":25:16)
auto x3631 = x3630 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3631);
reg = x3631;
}
// loc("cirgen/circuit/rv32im/decode.cpp":26:17)
auto x3632 = Fp(x3601.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3632);
reg = x3632;
}
// loc("cirgen/circuit/rv32im/decode.cpp":27:16)
auto x3633 = Fp(x3600.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":27:15)
auto x3634 = x3633 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3634);
reg = x3634;
}
// loc("cirgen/circuit/rv32im/decode.cpp":28:18)
auto x3635 = Fp(x3600.asUInt32() & x59.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":28:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3635);
reg = x3635;
}
}
// loc("Top/Mux/4/Mux/4/Decoder/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3636 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x3636 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x3637 = x3636 * x62;
// loc("Top/Mux/4/Mux/4/Decoder/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3638 = args[2][80 * steps + ((cycle - 0) & mask)];
assert(x3638 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x3639 = x3638 * x66;
// loc("Top/Mux/4/Mux/4/Decoder/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3640 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x3640 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:25)
auto x3641 = x3640 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x3642 = x3639 + x3641;
// loc("Top/Mux/4/Mux/4/Decoder/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3643 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x3643 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:39)
auto x3644 = x3643 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x3645 = x3642 + x3644;
// loc("Top/Mux/4/Mux/4/Decoder/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3646 = args[2][79 * steps + ((cycle - 0) & mask)];
assert(x3646 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x3647 = x3645 + x3646;
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x3648 = x3637 + x3647;
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x3649 = x3648 * x99;
// loc("Top/Mux/4/Mux/4/Decoder/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3650 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x3650 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x3651 = x3649 + x3650;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
auto x3652 = x3603 - x3651;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
if (x3652 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:30");
// loc("Top/Mux/4/Mux/4/Decoder/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3653 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x3653 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x3654 = x3653 * x77;
// loc("Top/Mux/4/Mux/4/Decoder/Twit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3655 = args[2][81 * steps + ((cycle - 0) & mask)];
assert(x3655 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:37)
auto x3656 = x3655 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x3657 = x3654 + x3656;
// loc("Top/Mux/4/Mux/4/Decoder/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3658 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x3658 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x3659 = x3657 + x3658;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x3660 = x3659 * x66;
// loc("Top/Mux/4/Mux/4/Decoder/Twit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3661 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x3661 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:69)
auto x3662 = x3661 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x3663 = x3660 + x3662;
// loc("Top/Mux/4/Mux/4/Decoder/Twit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3664 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x3664 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x3665 = x3663 + x3664;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
auto x3666 = x3602 - x3665;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
if (x3666 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:31");
// loc("Top/Mux/4/Mux/4/Decoder/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3667 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x3667 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x3668 = x3667 * x71;
// loc("Top/Mux/4/Mux/4/Decoder/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3669 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x3669 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x3670 = x3669 * x85;
// loc("Top/Mux/4/Mux/4/Decoder/Twit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3671 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x3671 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x3672 = x3670 + x3671;
// loc("cirgen/circuit/rv32im/decode.cpp":32:36)
auto x3673 = x3672 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x3674 = x3668 + x3673;
// loc("Top/Mux/4/Mux/4/Decoder/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3675 = args[2][86 * steps + ((cycle - 0) & mask)];
assert(x3675 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:53)
auto x3676 = x3675 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x3677 = x3674 + x3676;
// loc("Top/Mux/4/Mux/4/Decoder/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3678 = args[2][85 * steps + ((cycle - 0) & mask)];
assert(x3678 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x3679 = x3677 + x3678;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
auto x3680 = x3601 - x3679;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
if (x3680 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:32");
// loc("Top/Mux/4/Mux/4/Decoder/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3681 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x3681 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x3682 = x3681 * x71;
// loc("Top/Mux/4/Mux/4/Decoder/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3683 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x3683 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x3684 = x3682 + x3683;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
auto x3685 = x3600 - x3684;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
if (x3685 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:33");
{
host_args.at(0) = x3600;
host_args.at(1) = x3601;
host_args.at(2) = x3602;
host_args.at(3) = x3603;
host(ctx, "getMinor", "", host_args.data(), 4, host_outs.data(), 1);
auto x3686 = host_outs.at(0);
{
// loc("./cirgen/components/onehot.h":35:26)
auto x3687 = (x3686 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3687);
reg = x3687;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x3688 = x3686 - x102;
// loc("./cirgen/components/onehot.h":35:26)
auto x3689 = (x3688 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3689);
reg = x3689;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x3690 = x3686 - x99;
// loc("./cirgen/components/onehot.h":35:26)
auto x3691 = (x3690 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3691);
reg = x3691;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x3692 = x3686 - x84;
// loc("./cirgen/components/onehot.h":35:26)
auto x3693 = (x3692 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3693);
reg = x3693;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x3694 = x3686 - x85;
// loc("./cirgen/components/onehot.h":35:26)
auto x3695 = (x3694 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][190 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3695);
reg = x3695;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x3696 = x3686 - x80;
// loc("./cirgen/components/onehot.h":35:26)
auto x3697 = (x3696 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][191 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3697);
reg = x3697;
}
}
// loc("Top/Mux/4/Mux/4/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3698 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x3698 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3699 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x3699 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x3700 = x3699 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x3701 = x3698 + x3700;
// loc("Top/Mux/4/Mux/4/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3702 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x3702 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x3703 = x3702 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x3704 = x3701 + x3703;
// loc("Top/Mux/4/Mux/4/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3705 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x3705 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x3706 = x3705 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x3707 = x3704 + x3706;
// loc("Top/Mux/4/Mux/4/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3708 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x3708 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x3709 = x3708 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x3710 = x3707 + x3709;
// loc("./cirgen/components/onehot.h":38:8)
auto x3711 = x3710 - x3686;
// loc("./cirgen/components/onehot.h":38:8)
if (x3711 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
host_args.at(0) = x101;
host_args.at(1) = x101;
host_args.at(2) = x101;
host_args.at(3) = x101;
host_args.at(4) = x101;
host(ctx, "log", " useImm=%u, usePo2=%u, signedA=%u, signedB=%u, useHigh=%u", host_args.data(), 5, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/4/OneHot/Reg1"("./cirgen/circuit/rv32im/rv32im.inl":102:49))
auto x3712 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x3712 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/OneHot/Reg2"("./cirgen/circuit/rv32im/rv32im.inl":103:49))
auto x3713 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x3713 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":103:49)
auto x3714 = x3712 + x3713;
// loc("Top/Mux/4/Mux/4/OneHot/Reg3"("./cirgen/circuit/rv32im/rv32im.inl":104:49))
auto x3715 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x3715 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":104:49)
auto x3716 = x3714 + x3715;
// loc("Top/Mux/4/Mux/4/OneHot/Reg4"("./cirgen/circuit/rv32im/rv32im.inl":105:49))
auto x3717 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x3717 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/OneHot/Reg5"("./cirgen/circuit/rv32im/rv32im.inl":106:49))
auto x3718 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x3718 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":106:49)
auto x3719 = x3717 + x3718;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x3720 = x3661 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":37:26)
auto x3721 = x3664 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x3722 = x3720 + x3721;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x3723 = x3722 + x3667;
// loc("cirgen/circuit/rv32im/multiply.cpp":54:39)
auto x3724 = x3723 + x55;
{
host_args.at(0) = x3724;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x3725 = host_outs.at(0);
auto x3726 = host_outs.at(1);
auto x3727 = host_outs.at(2);
auto x3728 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3725);
reg = x3725;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3726);
reg = x3726;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3727);
reg = x3727;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3728);
reg = x3728;
}
}
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3729 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x3729 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3730 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x3730 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3731 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x3731 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3732 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x3732 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3724);
reg = x3724;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3594);
reg = x3594;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3729);
reg = x3729;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3730);
reg = x3730;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3731);
reg = x3731;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3732);
reg = x3732;
}
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x3733 = x3650 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x3734 = x3733 + x3659;
// loc("cirgen/circuit/rv32im/multiply.cpp":55:39)
auto x3735 = x3734 + x55;
{
host_args.at(0) = x3735;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x3736 = host_outs.at(0);
auto x3737 = host_outs.at(1);
auto x3738 = host_outs.at(2);
auto x3739 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3736);
reg = x3736;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3737);
reg = x3737;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3738);
reg = x3738;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3739);
reg = x3739;
}
}
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3740 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x3740 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3741 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x3741 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3742 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x3742 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3743 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x3743 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3735);
reg = x3735;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3594);
reg = x3594;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3740);
reg = x3740;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3741);
reg = x3741;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3742);
reg = x3742;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3743);
reg = x3743;
}
host_args.at(0) = x3723;
host_args.at(1) = x3729;
host_args.at(2) = x3730;
host_args.at(3) = x3731;
host_args.at(4) = x3732;
host_args.at(5) = x3734;
host_args.at(6) = x3740;
host_args.at(7) = x3741;
host_args.at(8) = x3742;
host_args.at(9) = x3743;
host(ctx, "log", " rs1=x%u -> %w, rs2=x%u -> %w", host_args.data(), 10, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3744 = x3643 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x3745 = x3646 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3746 = x3744 + x3745;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x3747 = x3746 + x3734;
// loc("cirgen/components/u32.cpp":105:20)
auto x3748 = x3718 * x3747;
// loc("cirgen/circuit/rv32im/multiply.cpp":61:35)
auto x3749 = x102 - x3718;
// loc("cirgen/components/u32.cpp":105:20)
auto x3750 = x3749 * x3740;
// loc("cirgen/components/u32.cpp":89:20)
auto x3751 = x3748 + x3750;
{
// loc("cirgen/circuit/rv32im/multiply.cpp":63:16)
auto x3752 = Fp(x3751.asUInt32() & x41.asUInt32());
// loc("cirgen/circuit/rv32im/multiply.cpp":63:15)
auto x3753 = x3752 * x61;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3753);
reg = x3753;
}
// loc("cirgen/circuit/rv32im/multiply.cpp":64:16)
auto x3754 = Fp(x3751.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/multiply.cpp":64:15)
auto x3755 = x3754 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][192 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3755);
reg = x3755;
}
// loc("cirgen/circuit/rv32im/multiply.cpp":65:14)
auto x3756 = Fp(x3751.asUInt32() & x40.asUInt32());
{
// loc("cirgen/components/u32.cpp":187:21)
auto x3757 = Fp(x3756.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][193 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3757);
reg = x3757;
}
// loc("cirgen/components/u32.cpp":187:21)
auto x3758 = Fp(x3756.asUInt32() & x99.asUInt32());
// loc("cirgen/components/u32.cpp":187:20)
auto x3759 = x3758 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][194 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3759);
reg = x3759;
}
// loc("cirgen/components/u32.cpp":187:21)
auto x3760 = Fp(x3756.asUInt32() & x85.asUInt32());
// loc("cirgen/components/u32.cpp":187:20)
auto x3761 = x3760 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][195 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3761);
reg = x3761;
}
// loc("cirgen/components/u32.cpp":187:21)
auto x3762 = Fp(x3756.asUInt32() & x77.asUInt32());
// loc("cirgen/components/u32.cpp":187:20)
auto x3763 = x3762 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][196 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3763);
reg = x3763;
}
// loc("cirgen/components/u32.cpp":187:21)
auto x3764 = Fp(x3756.asUInt32() & x66.asUInt32());
// loc("cirgen/components/u32.cpp":187:20)
auto x3765 = x3764 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][197 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3765);
reg = x3765;
}
// loc("Top/Mux/4/Mux/4/U32Po2/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3766 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x3766 != Fp::invalid());
// loc("cirgen/components/u32.cpp":189:21)
auto x3767 = x3766 * x39;
// loc("cirgen/components/u32.cpp":189:17)
auto x3768 = x3767 + x102;
// loc("Top/Mux/4/Mux/4/U32Po2/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3769 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x3769 != Fp::invalid());
// loc("cirgen/components/u32.cpp":189:42)
auto x3770 = x3769 * x84;
// loc("cirgen/components/u32.cpp":189:38)
auto x3771 = x3770 + x102;
// loc("cirgen/components/u32.cpp":189:16)
auto x3772 = x3768 * x3771;
// loc("Top/Mux/4/Mux/4/U32Po2/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3773 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x3773 != Fp::invalid());
// loc("cirgen/components/u32.cpp":189:58)
auto x3774 = x3773 + x102;
// loc("cirgen/components/u32.cpp":189:16)
auto x3775 = x3772 * x3774;
// loc("Top/Mux/4/Mux/4/U32Po2/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3776 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x3776 != Fp::invalid());
// loc("cirgen/components/u32.cpp":190:15)
auto x3777 = x3776 * x99;
// loc("Top/Mux/4/Mux/4/U32Po2/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3778 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x3778 != Fp::invalid());
// loc("cirgen/components/u32.cpp":190:15)
auto x3779 = x3777 + x3778;
// loc("cirgen/components/u32.cpp":192:13)
auto x3780 = (x3779 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/u32.cpp":192:9)
auto x3781 = x3780 * x3775;
// loc("cirgen/components/u32.cpp":192:34)
auto x3782 = x3779 - x102;
// loc("cirgen/components/u32.cpp":192:34)
auto x3783 = (x3782 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/u32.cpp":192:30)
auto x3784 = x3783 * x3775;
// loc("cirgen/components/u32.cpp":192:55)
auto x3785 = x3779 - x99;
// loc("cirgen/components/u32.cpp":192:55)
auto x3786 = (x3785 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/u32.cpp":192:51)
auto x3787 = x3786 * x3775;
// loc("cirgen/components/u32.cpp":192:76)
auto x3788 = x3779 - x84;
// loc("cirgen/components/u32.cpp":192:76)
auto x3789 = (x3788 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/u32.cpp":192:72)
auto x3790 = x3789 * x3775;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][198 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3781);
reg = x3781;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][199 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3784);
reg = x3784;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][200 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3787);
reg = x3787;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][201 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3790);
reg = x3790;
}
}
// loc("Top/Mux/4/Mux/4/U32Po2/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3791 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x3791 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/U32Po2/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3792 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x3792 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x3793 = x3792 * x99;
// loc("cirgen/components/u32.cpp":201:11)
auto x3794 = x3791 + x3793;
// loc("Top/Mux/4/Mux/4/U32Po2/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3795 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x3795 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x3796 = x3795 * x85;
// loc("cirgen/components/u32.cpp":201:11)
auto x3797 = x3794 + x3796;
// loc("Top/Mux/4/Mux/4/U32Po2/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3798 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x3798 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x3799 = x3798 * x77;
// loc("cirgen/components/u32.cpp":201:11)
auto x3800 = x3797 + x3799;
// loc("Top/Mux/4/Mux/4/U32Po2/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3801 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x3801 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x3802 = x3801 * x66;
// loc("cirgen/components/u32.cpp":201:11)
auto x3803 = x3800 + x3802;
// loc("cirgen/components/u32.cpp":195:6)
auto x3804 = x3803 - x3756;
// loc("cirgen/components/u32.cpp":195:6)
if (x3804 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:195");
}
// loc("Top/Mux/4/Mux/4/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3805 = args[2][87 * steps + ((cycle - 0) & mask)];
assert(x3805 != Fp::invalid());
// loc("cirgen/circuit/rv32im/multiply.cpp":67:23)
auto x3806 = x3805 * x62;
// loc("Top/Mux/4/Mux/4/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3807 = args[2][192 * steps + ((cycle - 0) & mask)];
assert(x3807 != Fp::invalid());
// loc("cirgen/circuit/rv32im/multiply.cpp":67:37)
auto x3808 = x3807 * x68;
// loc("cirgen/circuit/rv32im/multiply.cpp":67:23)
auto x3809 = x3806 + x3808;
// loc("Top/Mux/4/Mux/4/U32Po2/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3810 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x3810 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/U32Po2/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3811 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x3811 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x3812 = x3811 * x99;
// loc("cirgen/components/u32.cpp":201:11)
auto x3813 = x3810 + x3812;
// loc("Top/Mux/4/Mux/4/U32Po2/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3814 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x3814 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x3815 = x3814 * x85;
// loc("cirgen/components/u32.cpp":201:11)
auto x3816 = x3813 + x3815;
// loc("Top/Mux/4/Mux/4/U32Po2/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3817 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x3817 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x3818 = x3817 * x77;
// loc("cirgen/components/u32.cpp":201:11)
auto x3819 = x3816 + x3818;
// loc("Top/Mux/4/Mux/4/U32Po2/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3820 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x3820 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x3821 = x3820 * x66;
// loc("cirgen/components/u32.cpp":201:11)
auto x3822 = x3819 + x3821;
// loc("cirgen/circuit/rv32im/multiply.cpp":67:23)
auto x3823 = x3809 + x3822;
// loc("cirgen/circuit/rv32im/multiply.cpp":67:6)
auto x3824 = x3751 - x3823;
// loc("cirgen/circuit/rv32im/multiply.cpp":67:6)
if (x3824 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/multiply.cpp:67");
// loc("Top/Mux/4/Mux/4/U32Po2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3825 = args[2][198 * steps + ((cycle - 0) & mask)];
assert(x3825 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/U32Po2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x3826 = args[2][199 * steps + ((cycle - 0) & mask)];
assert(x3826 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/U32Po2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x3827 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x3827 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/U32Po2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x3828 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x3828 != Fp::invalid());
// loc("cirgen/components/u32.cpp":105:20)
auto x3829 = x3719 * x3825;
// loc("cirgen/components/u32.cpp":105:20)
auto x3830 = x3719 * x3826;
// loc("cirgen/components/u32.cpp":105:20)
auto x3831 = x3719 * x3827;
// loc("cirgen/components/u32.cpp":105:20)
auto x3832 = x3719 * x3828;
// loc("cirgen/circuit/rv32im/multiply.cpp":70:42)
auto x3833 = x102 - x3719;
// loc("cirgen/components/u32.cpp":105:20)
auto x3834 = x3833 * x3740;
// loc("cirgen/components/u32.cpp":105:20)
auto x3835 = x3833 * x3741;
// loc("cirgen/components/u32.cpp":105:20)
auto x3836 = x3833 * x3742;
// loc("cirgen/components/u32.cpp":105:20)
auto x3837 = x3833 * x3743;
// loc("cirgen/components/u32.cpp":89:20)
auto x3838 = x3829 + x3834;
// loc("cirgen/components/u32.cpp":89:20)
auto x3839 = x3830 + x3835;
// loc("cirgen/components/u32.cpp":89:20)
auto x3840 = x3831 + x3836;
// loc("cirgen/components/u32.cpp":89:20)
auto x3841 = x3832 + x3837;
{
// loc("cirgen/components/u32.cpp":120:18)
auto x3842 = Fp(x3732.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x3843 = x3842 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][202 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3843);
reg = x3843;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x3844 = Fp(x3732.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x3845 = x3844 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3845);
reg = x3845;
}
}
// loc("Top/Mux/4/Mux/4/U32Mul/TopBit/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3846 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x3846 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x3847 = x3846 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("cirgen/components/bytes.cpp":78:10))
auto x3848 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x3848 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x3849 = x3848 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x3850 = x3847 + x3849;
// loc("cirgen/components/u32.cpp":123:6)
auto x3851 = x3732 - x3850;
// loc("cirgen/components/u32.cpp":123:6)
if (x3851 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
{
// loc("cirgen/components/u32.cpp":120:18)
auto x3852 = Fp(x3841.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x3853 = x3852 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][203 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3853);
reg = x3853;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x3854 = Fp(x3841.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x3855 = x3854 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3855);
reg = x3855;
}
}
// loc("Top/Mux/4/Mux/4/U32Mul/TopBit1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3856 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x3856 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x3857 = x3856 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x3858 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x3858 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x3859 = x3858 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x3860 = x3857 + x3859;
// loc("cirgen/components/u32.cpp":123:6)
auto x3861 = x3841 - x3860;
// loc("cirgen/components/u32.cpp":123:6)
if (x3861 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
// loc("cirgen/components/u32.cpp":213:13)
auto x3862 = x3712 * x3856;
// loc("cirgen/components/u32.cpp":213:3)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3862);
reg = x3862;
}
// loc("cirgen/components/u32.cpp":214:13)
auto x3863 = x3714 * x3846;
// loc("cirgen/components/u32.cpp":214:3)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3863);
reg = x3863;
}
// loc("cirgen/components/u32.cpp":229:31)
auto x3864 = x3729 * x3838;
// loc("cirgen/components/u32.cpp":229:31)
auto x3865 = x3730 * x3838;
// loc("cirgen/components/u32.cpp":229:31)
auto x3866 = x3729 * x3839;
// loc("cirgen/components/u32.cpp":229:20)
auto x3867 = x3865 + x3866;
// loc("cirgen/components/u32.cpp":231:19)
auto x3868 = x3867 * x97;
// loc("cirgen/components/u32.cpp":231:13)
auto x3869 = x3864 + x3868;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3870 = Fp(x3869.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3870);
reg = x3870;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("cirgen/components/bytes.cpp":83:16))
auto x3871 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x3871 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3872 = x3869 - x3871;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3873 = x3872 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3874 = Fp(x3873.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3874);
reg = x3874;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x3875 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x3875 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3876 = x3873 - x3875;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3877 = x3876 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3878 = Fp(x3877.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3878);
reg = x3878;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("cirgen/components/bytes.cpp":83:16))
auto x3879 = args[2][32 * steps + ((cycle - 0) & mask)];
assert(x3879 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3880 = x3877 - x3879;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3881 = x3880 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3881);
reg = x3881;
}
// loc("Top/Mux/4/Mux/4/U32Mul/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3882 = args[2][88 * steps + ((cycle - 0) & mask)];
assert(x3882 != Fp::invalid());
// loc("cirgen/components/u32.cpp":219:19)
auto x3883 = x3882 * x97;
// loc("cirgen/components/u32.cpp":219:13)
auto x3884 = x3879 + x3883;
// loc("cirgen/components/u32.cpp":229:31)
auto x3885 = x3731 * x3838;
// loc("cirgen/components/u32.cpp":229:31)
auto x3886 = x3730 * x3839;
// loc("cirgen/components/u32.cpp":229:20)
auto x3887 = x3885 + x3886;
// loc("cirgen/components/u32.cpp":229:31)
auto x3888 = x3729 * x3840;
// loc("cirgen/components/u32.cpp":229:20)
auto x3889 = x3887 + x3888;
// loc("cirgen/components/u32.cpp":231:13)
auto x3890 = x3884 + x3889;
// loc("cirgen/components/u32.cpp":229:31)
auto x3891 = x3732 * x3838;
// loc("cirgen/components/u32.cpp":229:31)
auto x3892 = x3731 * x3839;
// loc("cirgen/components/u32.cpp":229:20)
auto x3893 = x3891 + x3892;
// loc("cirgen/components/u32.cpp":229:31)
auto x3894 = x3730 * x3840;
// loc("cirgen/components/u32.cpp":229:20)
auto x3895 = x3893 + x3894;
// loc("cirgen/components/u32.cpp":229:31)
auto x3896 = x3729 * x3841;
// loc("cirgen/components/u32.cpp":229:20)
auto x3897 = x3895 + x3896;
// loc("cirgen/components/u32.cpp":231:19)
auto x3898 = x3897 * x97;
// loc("cirgen/components/u32.cpp":231:13)
auto x3899 = x3890 + x3898;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3900 = Fp(x3899.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3900);
reg = x3900;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x3901 = args[2][33 * steps + ((cycle - 0) & mask)];
assert(x3901 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3902 = x3899 - x3901;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3903 = x3902 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3904 = Fp(x3903.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3904);
reg = x3904;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("cirgen/components/bytes.cpp":83:16))
auto x3905 = args[2][34 * steps + ((cycle - 0) & mask)];
assert(x3905 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3906 = x3903 - x3905;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3907 = x3906 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3908 = Fp(x3907.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3908);
reg = x3908;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x3909 = args[2][35 * steps + ((cycle - 0) & mask)];
assert(x3909 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3910 = x3907 - x3909;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3911 = x3910 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3911);
reg = x3911;
}
// loc("Top/Mux/4/Mux/4/U32Mul/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3912 = args[2][89 * steps + ((cycle - 0) & mask)];
assert(x3912 != Fp::invalid());
// loc("cirgen/components/u32.cpp":219:19)
auto x3913 = x3912 * x97;
// loc("cirgen/components/u32.cpp":219:13)
auto x3914 = x3909 + x3913;
// loc("cirgen/components/u32.cpp":229:31)
auto x3915 = x3732 * x3839;
// loc("cirgen/components/u32.cpp":229:31)
auto x3916 = x3731 * x3840;
// loc("cirgen/components/u32.cpp":229:20)
auto x3917 = x3915 + x3916;
// loc("cirgen/components/u32.cpp":229:31)
auto x3918 = x3730 * x3841;
// loc("cirgen/components/u32.cpp":229:20)
auto x3919 = x3917 + x3918;
// loc("cirgen/components/u32.cpp":231:13)
auto x3920 = x3914 + x3919;
// loc("cirgen/components/u32.cpp":229:31)
auto x3921 = x3732 * x3840;
// loc("cirgen/components/u32.cpp":229:31)
auto x3922 = x3731 * x3841;
// loc("cirgen/components/u32.cpp":229:20)
auto x3923 = x3921 + x3922;
// loc("cirgen/components/u32.cpp":231:19)
auto x3924 = x3923 * x97;
// loc("cirgen/components/u32.cpp":231:13)
auto x3925 = x3920 + x3924;
// loc("cirgen/components/u32.cpp":234:13)
auto x3926 = x3925 + x38;
// loc("Top/Mux/4/Mux/4/U32Mul/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3927 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x3927 != Fp::invalid());
// loc("cirgen/components/u32.cpp":234:53)
auto x3928 = x3730 * x97;
// loc("cirgen/components/u32.cpp":234:38)
auto x3929 = x3729 + x3928;
// loc("cirgen/components/u32.cpp":234:30)
auto x3930 = x3927 * x3929;
// loc("cirgen/components/u32.cpp":234:13)
auto x3931 = x3926 - x3930;
// loc("Top/Mux/4/Mux/4/U32Mul/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3932 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x3932 != Fp::invalid());
// loc("cirgen/components/u32.cpp":235:37)
auto x3933 = x3839 * x97;
// loc("cirgen/components/u32.cpp":235:22)
auto x3934 = x3838 + x3933;
// loc("cirgen/components/u32.cpp":235:14)
auto x3935 = x3932 * x3934;
// loc("cirgen/components/u32.cpp":234:13)
auto x3936 = x3931 - x3935;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3937 = Fp(x3936.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3937);
reg = x3937;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":83:16))
auto x3938 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x3938 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3939 = x3936 - x3938;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3940 = x3939 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3941 = Fp(x3940.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3941);
reg = x3941;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x3942 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x3942 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3943 = x3940 - x3942;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3944 = x3943 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3945 = Fp(x3944.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3945);
reg = x3945;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("cirgen/components/bytes.cpp":83:16))
auto x3946 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x3946 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3947 = x3944 - x3946;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3948 = x3947 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3948);
reg = x3948;
}
// loc("Top/Mux/4/Mux/4/U32Mul/Twit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3949 = args[2][90 * steps + ((cycle - 0) & mask)];
assert(x3949 != Fp::invalid());
// loc("cirgen/components/u32.cpp":219:19)
auto x3950 = x3949 * x97;
// loc("cirgen/components/u32.cpp":219:13)
auto x3951 = x3946 + x3950;
// loc("cirgen/components/u32.cpp":229:31)
auto x3952 = x3732 * x3841;
// loc("cirgen/components/u32.cpp":231:13)
auto x3953 = x3951 + x3952;
// loc("cirgen/components/u32.cpp":238:13)
auto x3954 = x3953 + x37;
// loc("cirgen/components/u32.cpp":238:53)
auto x3955 = x3732 * x97;
// loc("cirgen/components/u32.cpp":238:38)
auto x3956 = x3731 + x3955;
// loc("cirgen/components/u32.cpp":238:30)
auto x3957 = x3927 * x3956;
// loc("cirgen/components/u32.cpp":238:13)
auto x3958 = x3954 - x3957;
// loc("cirgen/components/u32.cpp":239:37)
auto x3959 = x3841 * x97;
// loc("cirgen/components/u32.cpp":239:22)
auto x3960 = x3840 + x3959;
// loc("cirgen/components/u32.cpp":239:14)
auto x3961 = x3932 * x3960;
// loc("cirgen/components/u32.cpp":238:13)
auto x3962 = x3958 - x3961;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3963 = Fp(x3962.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3963);
reg = x3963;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x3964 = args[2][39 * steps + ((cycle - 0) & mask)];
assert(x3964 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3965 = x3962 - x3964;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3966 = x3965 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3967 = Fp(x3966.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3967);
reg = x3967;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement15/Reg"("cirgen/components/bytes.cpp":83:16))
auto x3968 = args[2][40 * steps + ((cycle - 0) & mask)];
assert(x3968 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3969 = x3966 - x3968;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3970 = x3969 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3970);
reg = x3970;
}
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3971 = x3675 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":45:25)
auto x3972 = x3678 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3973 = x3971 + x3972;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x3974 = x3973 + x3681;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x3975 = (x3974 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3975);
reg = x3975;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x3976 = inv(x3974);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3976);
reg = x3976;
}
}
// loc("Top/Mux/4/Mux/4/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3977 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x3977 != Fp::invalid());
if (x3977 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x3974 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x3978 = x102 - x3977;
if (x3978 != 0) {
// loc("Top/Mux/4/Mux/4/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x3979 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x3979 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x3980 = x3974 * x3979;
// loc("cirgen/components/iszero.cpp":15:26)
auto x3981 = x3980 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x3981 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("cirgen/circuit/rv32im/multiply.cpp":78:17)
auto x3982 = x603 + x85;
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x3983 = x3982 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3984 = Fp(x3983.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3984);
reg = x3984;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x3985 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x3985 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3986 = x3983 - x3985;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3987 = x3986 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3988 = Fp(x3987.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3988);
reg = x3988;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x3989 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x3989 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3990 = x3987 - x3989;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3991 = x3990 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x3992 = Fp(x3991.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3992);
reg = x3992;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x3993 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x3993 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x3994 = x3991 - x3993;
// loc("cirgen/components/bytes.cpp":83:10)
auto x3995 = x3994 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x3996 = Fp(x3995.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3996);
reg = x3996;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x3997 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x3997 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x3998 = x3995 - x3997;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x3999 = x3998 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3999);
reg = x3999;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4000 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x4000 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x4001 = x102 - x4000;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x4002 = x4000 * x4001;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4002);
reg = x4002;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4003 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x4003 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x4004 = x99 - x4000;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x4005 = x4003 * x4004;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x4005 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("cirgen/circuit/rv32im/multiply.cpp":79:3)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("cirgen/circuit/rv32im/multiply.cpp":80:38)
auto x4006 = x3716 * x3978;
if (x4006 != 0) {
// loc("cirgen/circuit/rv32im/multiply.cpp":81:29)
auto x4007 = x3974 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3938);
reg = x3938;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3942);
reg = x3942;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3964);
reg = x3964;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3968);
reg = x3968;
}
{
host_args.at(0) = x4007;
host_args.at(1) = x3938;
host_args.at(2) = x3942;
host_args.at(3) = x3964;
host_args.at(4) = x3968;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4008 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x4008 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4009 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x4009 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4010 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x4010 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4011 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x4011 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4007);
reg = x4007;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3594);
reg = x3594;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4008);
reg = x4008;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4009);
reg = x4009;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4010);
reg = x4010;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4011);
reg = x4011;
}
}
// loc("cirgen/circuit/rv32im/multiply.cpp":83:44)
auto x4012 = x102 - x3716;
// loc("cirgen/circuit/rv32im/multiply.cpp":83:44)
auto x4013 = x4012 * x3978;
if (x4013 != 0) {
// loc("cirgen/circuit/rv32im/multiply.cpp":84:29)
auto x4014 = x3974 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3871);
reg = x3871;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3875);
reg = x3875;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3901);
reg = x3901;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3905);
reg = x3905;
}
{
host_args.at(0) = x4014;
host_args.at(1) = x3871;
host_args.at(2) = x3875;
host_args.at(3) = x3901;
host_args.at(4) = x3905;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4015 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x4015 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4016 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x4016 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4017 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x4017 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4018 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x4018 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4014);
reg = x4014;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x3594);
reg = x3594;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4015);
reg = x4015;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4016);
reg = x4016;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4017);
reg = x4017;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4018);
reg = x4018;
}
}
if (x3977 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/4/OneHot/Reg"("./cirgen/circuit/rv32im/rv32im.inl":101:49))
auto x4019 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x4019 != Fp::invalid());
if (x4019 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":101:49)
auto x4020 = x3683 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":101:49)
if (x4020 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:101");
// loc("./cirgen/circuit/rv32im/rv32im.inl":101:49)
if (x3672 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:101");
// loc("./cirgen/circuit/rv32im/rv32im.inl":101:49)
auto x4021 = x3648 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":101:49)
if (x4021 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:101");
}
if (x3712 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":102:49)
auto x4022 = x3683 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":102:49)
if (x4022 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:102");
// loc("./cirgen/circuit/rv32im/rv32im.inl":102:49)
auto x4023 = x3672 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":102:49)
if (x4023 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:102");
// loc("./cirgen/circuit/rv32im/rv32im.inl":102:49)
auto x4024 = x3648 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":102:49)
if (x4024 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:102");
}
if (x3713 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":103:49)
auto x4025 = x3683 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":103:49)
if (x4025 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:103");
// loc("./cirgen/circuit/rv32im/rv32im.inl":103:49)
auto x4026 = x3672 - x99;
// loc("./cirgen/circuit/rv32im/rv32im.inl":103:49)
if (x4026 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:103");
// loc("./cirgen/circuit/rv32im/rv32im.inl":103:49)
auto x4027 = x3648 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":103:49)
if (x4027 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:103");
}
if (x3715 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":104:49)
auto x4028 = x3683 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":104:49)
if (x4028 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:104");
// loc("./cirgen/circuit/rv32im/rv32im.inl":104:49)
auto x4029 = x3672 - x84;
// loc("./cirgen/circuit/rv32im/rv32im.inl":104:49)
if (x4029 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:104");
// loc("./cirgen/circuit/rv32im/rv32im.inl":104:49)
auto x4030 = x3648 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":104:49)
if (x4030 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:104");
}
if (x3717 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":105:49)
auto x4031 = x3683 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":105:49)
if (x4031 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:105");
// loc("./cirgen/circuit/rv32im/rv32im.inl":105:49)
auto x4032 = x3672 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":105:49)
if (x4032 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:105");
// loc("./cirgen/circuit/rv32im/rv32im.inl":105:49)
if (x3648 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:105");
}
if (x3718 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":106:49)
auto x4033 = x3683 - x51;
// loc("./cirgen/circuit/rv32im/rv32im.inl":106:49)
if (x4033 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:106");
// loc("./cirgen/circuit/rv32im/rv32im.inl":106:49)
auto x4034 = x3672 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":106:49)
if (x4034 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:106");
// loc("./cirgen/circuit/rv32im/rv32im.inl":106:49)
if (x3648 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:106");
}
}
// loc("Top/Mux/4/OneHot/Reg5"("./cirgen/components/mux.h":37:25))
auto x4035 = args[2][99 * steps + ((cycle - 0) & mask)];
assert(x4035 != Fp::invalid());
if (x4035 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4036 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x4036 != Fp::invalid());
// loc("cirgen/circuit/rv32im/divide.cpp":20:41)
auto x4037 = x603 * x83;
{
host_args.at(0) = x4037;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x4038 = host_outs.at(0);
auto x4039 = host_outs.at(1);
auto x4040 = host_outs.at(2);
auto x4041 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4038);
reg = x4038;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4039);
reg = x4039;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4040);
reg = x4040;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4041);
reg = x4041;
}
}
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4042 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x4042 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4043 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x4043 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4044 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x4044 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4045 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x4045 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4037);
reg = x4037;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4036);
reg = x4036;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4042);
reg = x4042;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4043);
reg = x4043;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4044);
reg = x4044;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4045);
reg = x4045;
}
{
// loc("cirgen/circuit/rv32im/decode.cpp":11:16)
auto x4046 = Fp(x4045.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":11:15)
auto x4047 = x4046 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4047);
reg = x4047;
}
// loc("cirgen/circuit/rv32im/decode.cpp":12:17)
auto x4048 = Fp(x4045.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":12:16)
auto x4049 = x4048 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4049);
reg = x4049;
}
// loc("cirgen/circuit/rv32im/decode.cpp":13:16)
auto x4050 = Fp(x4045.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":13:15)
auto x4051 = x4050 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4051);
reg = x4051;
}
// loc("cirgen/circuit/rv32im/decode.cpp":14:16)
auto x4052 = Fp(x4045.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":14:15)
auto x4053 = x4052 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4053);
reg = x4053;
}
// loc("cirgen/circuit/rv32im/decode.cpp":15:17)
auto x4054 = Fp(x4045.asUInt32() & x79.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":15:16)
auto x4055 = x4054 * x63;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][78 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4055);
reg = x4055;
}
// loc("cirgen/circuit/rv32im/decode.cpp":16:17)
auto x4056 = Fp(x4045.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4056);
reg = x4056;
}
// loc("cirgen/circuit/rv32im/decode.cpp":17:17)
auto x4057 = Fp(x4044.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":17:16)
auto x4058 = x4057 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4058);
reg = x4058;
}
// loc("cirgen/circuit/rv32im/decode.cpp":18:18)
auto x4059 = Fp(x4044.asUInt32() & x69.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":18:17)
auto x4060 = x4059 * x67;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4060);
reg = x4060;
}
// loc("cirgen/circuit/rv32im/decode.cpp":19:17)
auto x4061 = Fp(x4044.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":19:16)
auto x4062 = x4061 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4062);
reg = x4062;
}
// loc("cirgen/circuit/rv32im/decode.cpp":20:18)
auto x4063 = Fp(x4044.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":20:17)
auto x4064 = x4063 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4064);
reg = x4064;
}
// loc("cirgen/circuit/rv32im/decode.cpp":21:18)
auto x4065 = Fp(x4044.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4065);
reg = x4065;
}
// loc("cirgen/circuit/rv32im/decode.cpp":22:17)
auto x4066 = Fp(x4043.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":22:16)
auto x4067 = x4066 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4067);
reg = x4067;
}
// loc("cirgen/circuit/rv32im/decode.cpp":23:19)
auto x4068 = Fp(x4043.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":23:18)
auto x4069 = x4068 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4069);
reg = x4069;
}
// loc("cirgen/circuit/rv32im/decode.cpp":24:20)
auto x4070 = Fp(x4043.asUInt32() & x60.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":24:19)
auto x4071 = x4070 * x65;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4071);
reg = x4071;
}
// loc("cirgen/circuit/rv32im/decode.cpp":25:17)
auto x4072 = Fp(x4043.asUInt32() & x73.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":25:16)
auto x4073 = x4072 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4073);
reg = x4073;
}
// loc("cirgen/circuit/rv32im/decode.cpp":26:17)
auto x4074 = Fp(x4043.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4074);
reg = x4074;
}
// loc("cirgen/circuit/rv32im/decode.cpp":27:16)
auto x4075 = Fp(x4042.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":27:15)
auto x4076 = x4075 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][169 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4076);
reg = x4076;
}
// loc("cirgen/circuit/rv32im/decode.cpp":28:18)
auto x4077 = Fp(x4042.asUInt32() & x59.asUInt32());
// loc("cirgen/circuit/rv32im/decode.cpp":28:5)
{
auto& reg = args[2][170 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4077);
reg = x4077;
}
}
// loc("Top/Mux/4/Mux/5/Decoder/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4078 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x4078 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x4079 = x4078 * x62;
// loc("Top/Mux/4/Mux/5/Decoder/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4080 = args[2][79 * steps + ((cycle - 0) & mask)];
assert(x4080 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x4081 = x4080 * x66;
// loc("Top/Mux/4/Mux/5/Decoder/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4082 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x4082 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:25)
auto x4083 = x4082 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x4084 = x4081 + x4083;
// loc("Top/Mux/4/Mux/5/Decoder/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4085 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x4085 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:39)
auto x4086 = x4085 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x4087 = x4084 + x4086;
// loc("Top/Mux/4/Mux/5/Decoder/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4088 = args[2][78 * steps + ((cycle - 0) & mask)];
assert(x4088 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":57:10)
auto x4089 = x4087 + x4088;
// loc("cirgen/circuit/rv32im/decode.cpp":53:10)
auto x4090 = x4079 + x4089;
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x4091 = x4090 * x99;
// loc("Top/Mux/4/Mux/5/Decoder/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4092 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x4092 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":30:21)
auto x4093 = x4091 + x4092;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
auto x4094 = x4045 - x4093;
// loc("cirgen/circuit/rv32im/decode.cpp":30:6)
if (x4094 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:30");
// loc("Top/Mux/4/Mux/5/Decoder/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4095 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x4095 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x4096 = x4095 * x77;
// loc("Top/Mux/4/Mux/5/Decoder/Twit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4097 = args[2][80 * steps + ((cycle - 0) & mask)];
assert(x4097 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:37)
auto x4098 = x4097 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x4099 = x4096 + x4098;
// loc("Top/Mux/4/Mux/5/Decoder/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4100 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x4100 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:22)
auto x4101 = x4099 + x4100;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x4102 = x4101 * x66;
// loc("Top/Mux/4/Mux/5/Decoder/Twit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4103 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x4103 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:69)
auto x4104 = x4103 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x4105 = x4102 + x4104;
// loc("Top/Mux/4/Mux/5/Decoder/Twit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4106 = args[2][81 * steps + ((cycle - 0) & mask)];
assert(x4106 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":31:21)
auto x4107 = x4105 + x4106;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
auto x4108 = x4044 - x4107;
// loc("cirgen/circuit/rv32im/decode.cpp":31:6)
if (x4108 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:31");
// loc("Top/Mux/4/Mux/5/Decoder/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4109 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x4109 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x4110 = x4109 * x71;
// loc("Top/Mux/4/Mux/5/Decoder/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4111 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x4111 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x4112 = x4111 * x85;
// loc("Top/Mux/4/Mux/5/Decoder/Twit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4113 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x4113 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":49:10)
auto x4114 = x4112 + x4113;
// loc("cirgen/circuit/rv32im/decode.cpp":32:36)
auto x4115 = x4114 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x4116 = x4110 + x4115;
// loc("Top/Mux/4/Mux/5/Decoder/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4117 = args[2][85 * steps + ((cycle - 0) & mask)];
assert(x4117 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:53)
auto x4118 = x4117 * x85;
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x4119 = x4116 + x4118;
// loc("Top/Mux/4/Mux/5/Decoder/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4120 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x4120 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":32:21)
auto x4121 = x4119 + x4120;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
auto x4122 = x4043 - x4121;
// loc("cirgen/circuit/rv32im/decode.cpp":32:6)
if (x4122 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:32");
// loc("Top/Mux/4/Mux/5/Decoder/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4123 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x4123 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x4124 = x4123 * x71;
// loc("Top/Mux/4/Mux/5/Decoder/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4125 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x4125 != Fp::invalid());
// loc("cirgen/circuit/rv32im/decode.cpp":33:21)
auto x4126 = x4124 + x4125;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
auto x4127 = x4042 - x4126;
// loc("cirgen/circuit/rv32im/decode.cpp":33:6)
if (x4127 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/decode.cpp:33");
{
host_args.at(0) = x4042;
host_args.at(1) = x4043;
host_args.at(2) = x4044;
host_args.at(3) = x4045;
host(ctx, "getMinor", "", host_args.data(), 4, host_outs.data(), 1);
auto x4128 = host_outs.at(0);
{
// loc("./cirgen/components/onehot.h":35:26)
auto x4129 = (x4128 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][171 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4129);
reg = x4129;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x4130 = x4128 - x102;
// loc("./cirgen/components/onehot.h":35:26)
auto x4131 = (x4130 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][172 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4131);
reg = x4131;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x4132 = x4128 - x99;
// loc("./cirgen/components/onehot.h":35:26)
auto x4133 = (x4132 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4133);
reg = x4133;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x4134 = x4128 - x84;
// loc("./cirgen/components/onehot.h":35:26)
auto x4135 = (x4134 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][174 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4135);
reg = x4135;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x4136 = x4128 - x85;
// loc("./cirgen/components/onehot.h":35:26)
auto x4137 = (x4136 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][175 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4137);
reg = x4137;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x4138 = x4128 - x80;
// loc("./cirgen/components/onehot.h":35:26)
auto x4139 = (x4138 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4139);
reg = x4139;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x4140 = x4128 - x79;
// loc("./cirgen/components/onehot.h":35:26)
auto x4141 = (x4140 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4141);
reg = x4141;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x4142 = x4128 - x78;
// loc("./cirgen/components/onehot.h":35:26)
auto x4143 = (x4142 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4143);
reg = x4143;
}
}
// loc("Top/Mux/4/Mux/5/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4144 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x4144 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4145 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x4145 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x4146 = x4145 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x4147 = x4144 + x4146;
// loc("Top/Mux/4/Mux/5/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4148 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x4148 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x4149 = x4148 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x4150 = x4147 + x4149;
// loc("Top/Mux/4/Mux/5/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4151 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x4151 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x4152 = x4151 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x4153 = x4150 + x4152;
// loc("Top/Mux/4/Mux/5/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4154 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x4154 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x4155 = x4154 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x4156 = x4153 + x4155;
// loc("Top/Mux/4/Mux/5/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4157 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x4157 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x4158 = x4157 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x4159 = x4156 + x4158;
// loc("Top/Mux/4/Mux/5/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4160 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x4160 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x4161 = x4160 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x4162 = x4159 + x4161;
// loc("./cirgen/components/onehot.h":38:8)
auto x4163 = x4162 - x4128;
// loc("./cirgen/components/onehot.h":38:8)
if (x4163 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
// loc("Top/Mux/4/Mux/5/OneHot/Reg"("./cirgen/circuit/rv32im/rv32im.inl":124:49))
auto x4164 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x4164 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/OneHot/Reg2"("./cirgen/circuit/rv32im/rv32im.inl":126:49))
auto x4165 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x4165 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":126:49)
auto x4166 = x4164 + x4165;
// loc("Top/Mux/4/Mux/5/OneHot/Reg3"("./cirgen/circuit/rv32im/rv32im.inl":127:49))
auto x4167 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x4167 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":127:49)
auto x4168 = x4165 + x4167;
// loc("Top/Mux/4/Mux/5/OneHot/Reg4"("./cirgen/circuit/rv32im/rv32im.inl":128:49))
auto x4169 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x4169 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/OneHot/Reg5"("./cirgen/circuit/rv32im/rv32im.inl":129:49))
auto x4170 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x4170 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":129:49)
auto x4171 = x4169 + x4170;
// loc("./cirgen/circuit/rv32im/rv32im.inl":129:49)
auto x4172 = x4166 + x4170;
// loc("Top/Mux/4/Mux/5/OneHot/Reg6"("./cirgen/circuit/rv32im/rv32im.inl":130:49))
auto x4173 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x4173 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":130:49)
auto x4174 = x4171 + x4173;
// loc("Top/Mux/4/Mux/5/OneHot/Reg7"("./cirgen/circuit/rv32im/rv32im.inl":131:49))
auto x4175 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x4175 != Fp::invalid());
// loc("./cirgen/circuit/rv32im/rv32im.inl":131:49)
auto x4176 = x4173 + x4175;
// loc("./cirgen/circuit/rv32im/rv32im.inl":131:49)
auto x4177 = x4174 + x4175;
// loc("./cirgen/circuit/rv32im/rv32im.inl":131:49)
auto x4178 = x4172 + x4175;
// loc("./cirgen/circuit/rv32im/rv32im.inl":131:49)
auto x4179 = x4170 + x4175;
// loc("cirgen/circuit/rv32im/divide.cpp":46:3)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4178);
reg = x4178;
}
// loc("cirgen/circuit/rv32im/divide.cpp":47:3)
{
auto& reg = args[2][190 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4179);
reg = x4179;
}
// loc("Top/Mux/4/Mux/5/Reg"("cirgen/circuit/rv32im/divide.cpp":51:8))
auto x4180 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x4180 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/Reg1"("cirgen/circuit/rv32im/divide.cpp":52:8))
auto x4181 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x4181 != Fp::invalid());
host_args.at(0) = x4176;
host_args.at(1) = x4177;
host_args.at(2) = x4180;
host_args.at(3) = x4181;
host_args.at(4) = x4168;
host(ctx, "log", " useImm=%u, usePo2=%u, signed=%u, onesComp=%u, useRem=%u", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x4182 = x4103 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":37:26)
auto x4183 = x4106 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x4184 = x4182 + x4183;
// loc("cirgen/circuit/rv32im/decode.cpp":37:10)
auto x4185 = x4184 + x4109;
// loc("cirgen/circuit/rv32im/divide.cpp":56:39)
auto x4186 = x4185 + x55;
{
host_args.at(0) = x4186;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x4187 = host_outs.at(0);
auto x4188 = host_outs.at(1);
auto x4189 = host_outs.at(2);
auto x4190 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4187);
reg = x4187;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4188);
reg = x4188;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4189);
reg = x4189;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4190);
reg = x4190;
}
}
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4191 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x4191 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4192 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x4192 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4193 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x4193 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4194 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x4194 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4186);
reg = x4186;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4036);
reg = x4036;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4191);
reg = x4191;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4192);
reg = x4192;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4193);
reg = x4193;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4194);
reg = x4194;
}
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x4195 = x4092 * x66;
// loc("cirgen/circuit/rv32im/decode.cpp":41:10)
auto x4196 = x4195 + x4101;
// loc("cirgen/circuit/rv32im/divide.cpp":57:39)
auto x4197 = x4196 + x55;
{
host_args.at(0) = x4197;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x4198 = host_outs.at(0);
auto x4199 = host_outs.at(1);
auto x4200 = host_outs.at(2);
auto x4201 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4198);
reg = x4198;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4199);
reg = x4199;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4200);
reg = x4200;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4201);
reg = x4201;
}
}
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4202 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x4202 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4203 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x4203 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4204 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x4204 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4205 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x4205 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4197);
reg = x4197;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4036);
reg = x4036;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4202);
reg = x4202;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4203);
reg = x4203;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4204);
reg = x4204;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4205);
reg = x4205;
}
host_args.at(0) = x4185;
host_args.at(1) = x4191;
host_args.at(2) = x4192;
host_args.at(3) = x4193;
host_args.at(4) = x4194;
host_args.at(5) = x4196;
host_args.at(6) = x4202;
host_args.at(7) = x4203;
host_args.at(8) = x4204;
host_args.at(9) = x4205;
host(ctx, "log", " rs1=x%u -> %w, rs2=x%u -> %w", host_args.data(), 10, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x4206 = x4085 * x71;
// loc("cirgen/circuit/rv32im/decode.cpp":70:21)
auto x4207 = x4088 * x68;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x4208 = x4206 + x4207;
// loc("cirgen/circuit/rv32im/decode.cpp":70:7)
auto x4209 = x4208 + x4196;
// loc("cirgen/components/u32.cpp":105:20)
auto x4210 = x4176 * x4209;
// loc("cirgen/circuit/rv32im/divide.cpp":63:35)
auto x4211 = x102 - x4176;
// loc("cirgen/components/u32.cpp":105:20)
auto x4212 = x4211 * x4202;
// loc("cirgen/components/u32.cpp":89:20)
auto x4213 = x4210 + x4212;
{
// loc("cirgen/circuit/rv32im/divide.cpp":65:16)
auto x4214 = Fp(x4213.asUInt32() & x41.asUInt32());
// loc("cirgen/circuit/rv32im/divide.cpp":65:15)
auto x4215 = x4214 * x61;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4215);
reg = x4215;
}
// loc("cirgen/circuit/rv32im/divide.cpp":66:16)
auto x4216 = Fp(x4213.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/divide.cpp":66:15)
auto x4217 = x4216 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4217);
reg = x4217;
}
// loc("cirgen/circuit/rv32im/divide.cpp":67:14)
auto x4218 = Fp(x4213.asUInt32() & x40.asUInt32());
{
// loc("cirgen/components/u32.cpp":187:21)
auto x4219 = Fp(x4218.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4219);
reg = x4219;
}
// loc("cirgen/components/u32.cpp":187:21)
auto x4220 = Fp(x4218.asUInt32() & x99.asUInt32());
// loc("cirgen/components/u32.cpp":187:20)
auto x4221 = x4220 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4221);
reg = x4221;
}
// loc("cirgen/components/u32.cpp":187:21)
auto x4222 = Fp(x4218.asUInt32() & x85.asUInt32());
// loc("cirgen/components/u32.cpp":187:20)
auto x4223 = x4222 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4223);
reg = x4223;
}
// loc("cirgen/components/u32.cpp":187:21)
auto x4224 = Fp(x4218.asUInt32() & x77.asUInt32());
// loc("cirgen/components/u32.cpp":187:20)
auto x4225 = x4224 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4225);
reg = x4225;
}
// loc("cirgen/components/u32.cpp":187:21)
auto x4226 = Fp(x4218.asUInt32() & x66.asUInt32());
// loc("cirgen/components/u32.cpp":187:20)
auto x4227 = x4226 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4227);
reg = x4227;
}
// loc("Top/Mux/4/Mux/5/U32Po2/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4228 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x4228 != Fp::invalid());
// loc("cirgen/components/u32.cpp":189:21)
auto x4229 = x4228 * x39;
// loc("cirgen/components/u32.cpp":189:17)
auto x4230 = x4229 + x102;
// loc("Top/Mux/4/Mux/5/U32Po2/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4231 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x4231 != Fp::invalid());
// loc("cirgen/components/u32.cpp":189:42)
auto x4232 = x4231 * x84;
// loc("cirgen/components/u32.cpp":189:38)
auto x4233 = x4232 + x102;
// loc("cirgen/components/u32.cpp":189:16)
auto x4234 = x4230 * x4233;
// loc("Top/Mux/4/Mux/5/U32Po2/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4235 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x4235 != Fp::invalid());
// loc("cirgen/components/u32.cpp":189:58)
auto x4236 = x4235 + x102;
// loc("cirgen/components/u32.cpp":189:16)
auto x4237 = x4234 * x4236;
// loc("Top/Mux/4/Mux/5/U32Po2/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4238 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x4238 != Fp::invalid());
// loc("cirgen/components/u32.cpp":190:15)
auto x4239 = x4238 * x99;
// loc("Top/Mux/4/Mux/5/U32Po2/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4240 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x4240 != Fp::invalid());
// loc("cirgen/components/u32.cpp":190:15)
auto x4241 = x4239 + x4240;
// loc("cirgen/components/u32.cpp":192:13)
auto x4242 = (x4241 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/u32.cpp":192:9)
auto x4243 = x4242 * x4237;
// loc("cirgen/components/u32.cpp":192:34)
auto x4244 = x4241 - x102;
// loc("cirgen/components/u32.cpp":192:34)
auto x4245 = (x4244 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/u32.cpp":192:30)
auto x4246 = x4245 * x4237;
// loc("cirgen/components/u32.cpp":192:55)
auto x4247 = x4241 - x99;
// loc("cirgen/components/u32.cpp":192:55)
auto x4248 = (x4247 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/u32.cpp":192:51)
auto x4249 = x4248 * x4237;
// loc("cirgen/components/u32.cpp":192:76)
auto x4250 = x4241 - x84;
// loc("cirgen/components/u32.cpp":192:76)
auto x4251 = (x4250 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/components/u32.cpp":192:72)
auto x4252 = x4251 * x4237;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4243);
reg = x4243;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4246);
reg = x4246;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4249);
reg = x4249;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4252);
reg = x4252;
}
}
// loc("Top/Mux/4/Mux/5/U32Po2/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4253 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x4253 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/U32Po2/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4254 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x4254 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x4255 = x4254 * x99;
// loc("cirgen/components/u32.cpp":201:11)
auto x4256 = x4253 + x4255;
// loc("Top/Mux/4/Mux/5/U32Po2/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4257 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x4257 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x4258 = x4257 * x85;
// loc("cirgen/components/u32.cpp":201:11)
auto x4259 = x4256 + x4258;
// loc("Top/Mux/4/Mux/5/U32Po2/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4260 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x4260 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x4261 = x4260 * x77;
// loc("cirgen/components/u32.cpp":201:11)
auto x4262 = x4259 + x4261;
// loc("Top/Mux/4/Mux/5/U32Po2/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4263 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x4263 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x4264 = x4263 * x66;
// loc("cirgen/components/u32.cpp":201:11)
auto x4265 = x4262 + x4264;
// loc("cirgen/components/u32.cpp":195:6)
auto x4266 = x4265 - x4218;
// loc("cirgen/components/u32.cpp":195:6)
if (x4266 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:195");
}
// loc("Top/Mux/4/Mux/5/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4267 = args[2][86 * steps + ((cycle - 0) & mask)];
assert(x4267 != Fp::invalid());
// loc("cirgen/circuit/rv32im/divide.cpp":69:23)
auto x4268 = x4267 * x62;
// loc("Top/Mux/4/Mux/5/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4269 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x4269 != Fp::invalid());
// loc("cirgen/circuit/rv32im/divide.cpp":69:37)
auto x4270 = x4269 * x68;
// loc("cirgen/circuit/rv32im/divide.cpp":69:23)
auto x4271 = x4268 + x4270;
// loc("Top/Mux/4/Mux/5/U32Po2/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4272 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x4272 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/U32Po2/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4273 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x4273 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x4274 = x4273 * x99;
// loc("cirgen/components/u32.cpp":201:11)
auto x4275 = x4272 + x4274;
// loc("Top/Mux/4/Mux/5/U32Po2/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4276 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x4276 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x4277 = x4276 * x85;
// loc("cirgen/components/u32.cpp":201:11)
auto x4278 = x4275 + x4277;
// loc("Top/Mux/4/Mux/5/U32Po2/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4279 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x4279 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x4280 = x4279 * x77;
// loc("cirgen/components/u32.cpp":201:11)
auto x4281 = x4278 + x4280;
// loc("Top/Mux/4/Mux/5/U32Po2/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4282 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x4282 != Fp::invalid());
// loc("cirgen/components/u32.cpp":201:17)
auto x4283 = x4282 * x66;
// loc("cirgen/components/u32.cpp":201:11)
auto x4284 = x4281 + x4283;
// loc("cirgen/circuit/rv32im/divide.cpp":69:23)
auto x4285 = x4271 + x4284;
// loc("cirgen/circuit/rv32im/divide.cpp":69:6)
auto x4286 = x4213 - x4285;
// loc("cirgen/circuit/rv32im/divide.cpp":69:6)
if (x4286 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/divide.cpp:69");
// loc("Top/Mux/4/Mux/5/U32Po2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4287 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x4287 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/U32Po2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4288 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x4288 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/U32Po2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4289 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x4289 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/U32Po2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4290 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x4290 != Fp::invalid());
// loc("cirgen/components/u32.cpp":105:20)
auto x4291 = x4177 * x4287;
// loc("cirgen/components/u32.cpp":105:20)
auto x4292 = x4177 * x4288;
// loc("cirgen/components/u32.cpp":105:20)
auto x4293 = x4177 * x4289;
// loc("cirgen/components/u32.cpp":105:20)
auto x4294 = x4177 * x4290;
// loc("cirgen/circuit/rv32im/divide.cpp":72:42)
auto x4295 = x102 - x4177;
// loc("cirgen/components/u32.cpp":105:20)
auto x4296 = x4295 * x4202;
// loc("cirgen/components/u32.cpp":105:20)
auto x4297 = x4295 * x4203;
// loc("cirgen/components/u32.cpp":105:20)
auto x4298 = x4295 * x4204;
// loc("cirgen/components/u32.cpp":105:20)
auto x4299 = x4295 * x4205;
// loc("cirgen/components/u32.cpp":89:20)
auto x4300 = x4291 + x4296;
// loc("cirgen/components/u32.cpp":89:20)
auto x4301 = x4292 + x4297;
// loc("cirgen/components/u32.cpp":89:20)
auto x4302 = x4293 + x4298;
// loc("cirgen/components/u32.cpp":89:20)
auto x4303 = x4294 + x4299;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4300);
reg = x4300;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4301);
reg = x4301;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4302);
reg = x4302;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4303);
reg = x4303;
}
{
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4304 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x4304 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4305 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x4305 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4306 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x4306 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4307 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x4307 != Fp::invalid());
// loc("cirgen/circuit/rv32im/divide.cpp":83:16)
auto x4308 = x4180 + x4181;
host_args.at(0) = x4191;
host_args.at(1) = x4192;
host_args.at(2) = x4193;
host_args.at(3) = x4194;
host_args.at(4) = x4304;
host_args.at(5) = x4305;
host_args.at(6) = x4306;
host_args.at(7) = x4307;
host_args.at(8) = x4308;
host(ctx, "divide", "", host_args.data(), 9, host_outs.data(), 8);
auto x4309 = host_outs.at(0);
auto x4310 = host_outs.at(1);
auto x4311 = host_outs.at(2);
auto x4312 = host_outs.at(3);
auto x4313 = host_outs.at(4);
auto x4314 = host_outs.at(5);
auto x4315 = host_outs.at(6);
auto x4316 = host_outs.at(7);
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4309);
reg = x4309;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4313);
reg = x4313;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4310);
reg = x4310;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4314);
reg = x4314;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4311);
reg = x4311;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4315);
reg = x4315;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4312);
reg = x4312;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4316);
reg = x4316;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4317 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x4317 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4318 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x4318 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4319 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x4319 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4320 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x4320 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4321 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x4321 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4322 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x4322 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4323 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x4323 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4324 = args[2][32 * steps + ((cycle - 0) & mask)];
assert(x4324 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4325 = args[2][33 * steps + ((cycle - 0) & mask)];
assert(x4325 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4326 = args[2][34 * steps + ((cycle - 0) & mask)];
assert(x4326 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4327 = args[2][35 * steps + ((cycle - 0) & mask)];
assert(x4327 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4328 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x4328 != Fp::invalid());
host_args.at(0) = x4191;
host_args.at(1) = x4192;
host_args.at(2) = x4193;
host_args.at(3) = x4194;
host_args.at(4) = x4317;
host_args.at(5) = x4318;
host_args.at(6) = x4319;
host_args.at(7) = x4320;
host_args.at(8) = x4321;
host_args.at(9) = x4322;
host_args.at(10) = x4323;
host_args.at(11) = x4324;
host_args.at(12) = x4325;
host_args.at(13) = x4326;
host_args.at(14) = x4327;
host_args.at(15) = x4328;
host(ctx, "log", " numer=%w, denom=%w, quot=%w, rem=%w", host_args.data(), 16, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x4329 = x4117 * x77;
// loc("cirgen/circuit/rv32im/decode.cpp":45:25)
auto x4330 = x4120 * x99;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x4331 = x4329 + x4330;
// loc("cirgen/circuit/rv32im/decode.cpp":45:10)
auto x4332 = x4331 + x4123;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x4333 = (x4332 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][191 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4333);
reg = x4333;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x4334 = inv(x4332);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][192 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4334);
reg = x4334;
}
}
// loc("Top/Mux/4/Mux/5/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4335 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x4335 != Fp::invalid());
if (x4335 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x4332 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x4336 = x102 - x4335;
if (x4336 != 0) {
// loc("Top/Mux/4/Mux/5/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4337 = args[2][192 * steps + ((cycle - 0) & mask)];
assert(x4337 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x4338 = x4332 * x4337;
// loc("cirgen/components/iszero.cpp":15:26)
auto x4339 = x4338 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x4339 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("cirgen/circuit/rv32im/divide.cpp":94:37)
auto x4340 = x4168 * x4336;
if (x4340 != 0) {
// loc("cirgen/circuit/rv32im/divide.cpp":96:16)
auto x4341 = x4332 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4325);
reg = x4325;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4326);
reg = x4326;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4327);
reg = x4327;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4328);
reg = x4328;
}
{
host_args.at(0) = x4341;
host_args.at(1) = x4325;
host_args.at(2) = x4326;
host_args.at(3) = x4327;
host_args.at(4) = x4328;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4342 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x4342 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4343 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x4343 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4344 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x4344 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4345 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x4345 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4341);
reg = x4341;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4036);
reg = x4036;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4342);
reg = x4342;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4343);
reg = x4343;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4344);
reg = x4344;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4345);
reg = x4345;
}
}
// loc("cirgen/circuit/rv32im/divide.cpp":98:43)
auto x4346 = x102 - x4168;
// loc("cirgen/circuit/rv32im/divide.cpp":98:43)
auto x4347 = x4346 * x4336;
if (x4347 != 0) {
// loc("cirgen/circuit/rv32im/divide.cpp":100:16)
auto x4348 = x4332 + x55;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4321);
reg = x4321;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4322);
reg = x4322;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4323);
reg = x4323;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4324);
reg = x4324;
}
{
host_args.at(0) = x4348;
host_args.at(1) = x4321;
host_args.at(2) = x4322;
host_args.at(3) = x4323;
host_args.at(4) = x4324;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4349 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x4349 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4350 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x4350 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4351 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x4351 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4352 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x4352 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4348);
reg = x4348;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4036);
reg = x4036;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4349);
reg = x4349;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4350);
reg = x4350;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4351);
reg = x4351;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4352);
reg = x4352;
}
}
if (x4335 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("cirgen/circuit/rv32im/divide.cpp":105:17)
auto x4353 = x603 + x85;
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x4354 = x4353 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4355 = Fp(x4354.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4355);
reg = x4355;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x4356 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x4356 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4357 = x4354 - x4356;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4358 = x4357 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4359 = Fp(x4358.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4359);
reg = x4359;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x4360 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x4360 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4361 = x4358 - x4360;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4362 = x4361 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4363 = Fp(x4362.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4363);
reg = x4363;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x4364 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x4364 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4365 = x4362 - x4364;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4366 = x4365 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x4367 = Fp(x4366.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4367);
reg = x4367;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4368 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x4368 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x4369 = x4366 - x4368;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x4370 = x4369 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4370);
reg = x4370;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4371 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x4371 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x4372 = x102 - x4371;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x4373 = x4371 * x4372;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4373);
reg = x4373;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4374 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x4374 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x4375 = x99 - x4371;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x4376 = x4374 * x4375;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x4376 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("cirgen/circuit/rv32im/divide.cpp":106:3)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x78);
reg = x78;
}
if (x4164 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":124:49)
auto x4377 = x4125 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":124:49)
if (x4377 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:124");
// loc("./cirgen/circuit/rv32im/rv32im.inl":124:49)
auto x4378 = x4114 - x85;
// loc("./cirgen/circuit/rv32im/rv32im.inl":124:49)
if (x4378 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:124");
// loc("./cirgen/circuit/rv32im/rv32im.inl":124:49)
auto x4379 = x4090 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":124:49)
if (x4379 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:124");
}
// loc("Top/Mux/4/Mux/5/OneHot/Reg1"("./cirgen/circuit/rv32im/rv32im.inl":125:49))
auto x4380 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x4380 != Fp::invalid());
if (x4380 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":125:49)
auto x4381 = x4125 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":125:49)
if (x4381 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:125");
// loc("./cirgen/circuit/rv32im/rv32im.inl":125:49)
auto x4382 = x4114 - x80;
// loc("./cirgen/circuit/rv32im/rv32im.inl":125:49)
if (x4382 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:125");
// loc("./cirgen/circuit/rv32im/rv32im.inl":125:49)
auto x4383 = x4090 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":125:49)
if (x4383 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:125");
}
if (x4165 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":126:49)
auto x4384 = x4125 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":126:49)
if (x4384 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:126");
// loc("./cirgen/circuit/rv32im/rv32im.inl":126:49)
auto x4385 = x4114 - x79;
// loc("./cirgen/circuit/rv32im/rv32im.inl":126:49)
if (x4385 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:126");
// loc("./cirgen/circuit/rv32im/rv32im.inl":126:49)
auto x4386 = x4090 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":126:49)
if (x4386 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:126");
}
if (x4167 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":127:49)
auto x4387 = x4125 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":127:49)
if (x4387 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:127");
// loc("./cirgen/circuit/rv32im/rv32im.inl":127:49)
auto x4388 = x4114 - x78;
// loc("./cirgen/circuit/rv32im/rv32im.inl":127:49)
if (x4388 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:127");
// loc("./cirgen/circuit/rv32im/rv32im.inl":127:49)
auto x4389 = x4090 - x102;
// loc("./cirgen/circuit/rv32im/rv32im.inl":127:49)
if (x4389 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:127");
}
if (x4169 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":128:49)
auto x4390 = x4125 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":128:49)
if (x4390 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:128");
// loc("./cirgen/circuit/rv32im/rv32im.inl":128:49)
auto x4391 = x4114 - x80;
// loc("./cirgen/circuit/rv32im/rv32im.inl":128:49)
if (x4391 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:128");
// loc("./cirgen/circuit/rv32im/rv32im.inl":128:49)
if (x4090 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:128");
}
if (x4170 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":129:49)
auto x4392 = x4125 - x52;
// loc("./cirgen/circuit/rv32im/rv32im.inl":129:49)
if (x4392 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:129");
// loc("./cirgen/circuit/rv32im/rv32im.inl":129:49)
auto x4393 = x4114 - x80;
// loc("./cirgen/circuit/rv32im/rv32im.inl":129:49)
if (x4393 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:129");
// loc("./cirgen/circuit/rv32im/rv32im.inl":129:49)
auto x4394 = x4090 - x68;
// loc("./cirgen/circuit/rv32im/rv32im.inl":129:49)
if (x4394 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:129");
}
if (x4173 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":130:49)
auto x4395 = x4125 - x51;
// loc("./cirgen/circuit/rv32im/rv32im.inl":130:49)
if (x4395 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:130");
// loc("./cirgen/circuit/rv32im/rv32im.inl":130:49)
auto x4396 = x4114 - x80;
// loc("./cirgen/circuit/rv32im/rv32im.inl":130:49)
if (x4396 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:130");
// loc("./cirgen/circuit/rv32im/rv32im.inl":130:49)
if (x4090 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:130");
}
if (x4175 != 0) {
// loc("./cirgen/circuit/rv32im/rv32im.inl":131:49)
auto x4397 = x4125 - x51;
// loc("./cirgen/circuit/rv32im/rv32im.inl":131:49)
if (x4397 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:131");
// loc("./cirgen/circuit/rv32im/rv32im.inl":131:49)
auto x4398 = x4114 - x80;
// loc("./cirgen/circuit/rv32im/rv32im.inl":131:49)
if (x4398 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:131");
// loc("./cirgen/circuit/rv32im/rv32im.inl":131:49)
auto x4399 = x4090 - x68;
// loc("./cirgen/circuit/rv32im/rv32im.inl":131:49)
if (x4399 != 0) throw std::runtime_error("eqz failed at: ./cirgen/circuit/rv32im/rv32im.inl:131");
}
}
// loc("Top/Mux/4/OneHot/Reg6"("./cirgen/components/mux.h":37:25))
auto x4400 = args[2][100 * steps + ((cycle - 0) & mask)];
assert(x4400 != Fp::invalid());
if (x4400 != 0) {
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4401 = args[2][118 * steps + ((cycle - 1) & mask)];
assert(x4401 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4402 = args[2][119 * steps + ((cycle - 1) & mask)];
assert(x4402 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4403 = args[2][120 * steps + ((cycle - 1) & mask)];
assert(x4403 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4404 = args[2][121 * steps + ((cycle - 1) & mask)];
assert(x4404 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4405 = args[2][191 * steps + ((cycle - 1) & mask)];
assert(x4405 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4406 = args[2][192 * steps + ((cycle - 1) & mask)];
assert(x4406 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4407 = args[2][193 * steps + ((cycle - 1) & mask)];
assert(x4407 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4408 = args[2][194 * steps + ((cycle - 1) & mask)];
assert(x4408 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4409 = args[2][195 * steps + ((cycle - 1) & mask)];
assert(x4409 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4410 = args[2][196 * steps + ((cycle - 1) & mask)];
assert(x4410 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4411 = args[2][197 * steps + ((cycle - 1) & mask)];
assert(x4411 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/ALU/U32Reg1/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4412 = args[2][198 * steps + ((cycle - 1) & mask)];
assert(x4412 != Fp::invalid());
{
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4413 = Fp(x4401.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4413);
reg = x4413;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4414 = Fp(x4405.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4414);
reg = x4414;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4415 = Fp(x4401.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4416 = x4415 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4416);
reg = x4416;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4417 = Fp(x4405.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4418 = x4417 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4418);
reg = x4418;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4419 = Fp(x4401.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4420 = x4419 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4420);
reg = x4420;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4421 = Fp(x4405.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4422 = x4421 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4422);
reg = x4422;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4423 = Fp(x4401.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4424 = x4423 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4424);
reg = x4424;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4425 = Fp(x4405.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4426 = x4425 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][143 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4426);
reg = x4426;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4427 = Fp(x4401.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4428 = x4427 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4428);
reg = x4428;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4429 = Fp(x4405.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4430 = x4429 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][144 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4430);
reg = x4430;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4431 = Fp(x4401.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4432 = x4431 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4432);
reg = x4432;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4433 = Fp(x4405.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4434 = x4433 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][145 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4434);
reg = x4434;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4435 = Fp(x4401.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4436 = x4435 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4436);
reg = x4436;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4437 = Fp(x4405.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4438 = x4437 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][146 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4438);
reg = x4438;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4439 = Fp(x4401.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4440 = x4439 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4440);
reg = x4440;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4441 = Fp(x4405.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4442 = x4441 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][147 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4442);
reg = x4442;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4443 = Fp(x4402.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4443);
reg = x4443;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4444 = Fp(x4406.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][148 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4444);
reg = x4444;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4445 = Fp(x4402.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4446 = x4445 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4446);
reg = x4446;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4447 = Fp(x4406.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4448 = x4447 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][149 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4448);
reg = x4448;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4449 = Fp(x4402.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4450 = x4449 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4450);
reg = x4450;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4451 = Fp(x4406.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4452 = x4451 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][150 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4452);
reg = x4452;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4453 = Fp(x4402.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4454 = x4453 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4454);
reg = x4454;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4455 = Fp(x4406.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4456 = x4455 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][151 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4456);
reg = x4456;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4457 = Fp(x4402.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4458 = x4457 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4458);
reg = x4458;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4459 = Fp(x4406.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4460 = x4459 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][152 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4460);
reg = x4460;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4461 = Fp(x4402.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4462 = x4461 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4462);
reg = x4462;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4463 = Fp(x4406.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4464 = x4463 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][153 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4464);
reg = x4464;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4465 = Fp(x4402.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4466 = x4465 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4466);
reg = x4466;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4467 = Fp(x4406.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4468 = x4467 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][154 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4468);
reg = x4468;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4469 = Fp(x4402.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4470 = x4469 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4470);
reg = x4470;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4471 = Fp(x4406.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4472 = x4471 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][155 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4472);
reg = x4472;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4473 = Fp(x4403.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4473);
reg = x4473;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4474 = Fp(x4407.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][156 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4474);
reg = x4474;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4475 = Fp(x4403.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4476 = x4475 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4476);
reg = x4476;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4477 = Fp(x4407.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4478 = x4477 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][157 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4478);
reg = x4478;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4479 = Fp(x4403.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4480 = x4479 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4480);
reg = x4480;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4481 = Fp(x4407.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4482 = x4481 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][158 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4482);
reg = x4482;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4483 = Fp(x4403.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4484 = x4483 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4484);
reg = x4484;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4485 = Fp(x4407.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4486 = x4485 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][159 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4486);
reg = x4486;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4487 = Fp(x4403.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4488 = x4487 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4488);
reg = x4488;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4489 = Fp(x4407.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4490 = x4489 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][160 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4490);
reg = x4490;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4491 = Fp(x4403.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4492 = x4491 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4492);
reg = x4492;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4493 = Fp(x4407.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4494 = x4493 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4494);
reg = x4494;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4495 = Fp(x4403.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4496 = x4495 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4496);
reg = x4496;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4497 = Fp(x4407.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4498 = x4497 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4498);
reg = x4498;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4499 = Fp(x4403.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4500 = x4499 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4500);
reg = x4500;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4501 = Fp(x4407.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4502 = x4501 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4502);
reg = x4502;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4503 = Fp(x4404.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4503);
reg = x4503;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4504 = Fp(x4408.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4504);
reg = x4504;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4505 = Fp(x4404.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4506 = x4505 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4506);
reg = x4506;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4507 = Fp(x4408.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4508 = x4507 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4508);
reg = x4508;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4509 = Fp(x4404.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4510 = x4509 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4510);
reg = x4510;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4511 = Fp(x4408.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4512 = x4511 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4512);
reg = x4512;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4513 = Fp(x4404.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4514 = x4513 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4514);
reg = x4514;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4515 = Fp(x4408.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4516 = x4515 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4516);
reg = x4516;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4517 = Fp(x4404.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4518 = x4517 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4518);
reg = x4518;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4519 = Fp(x4408.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4520 = x4519 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4520);
reg = x4520;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4521 = Fp(x4404.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4522 = x4521 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4522);
reg = x4522;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4523 = Fp(x4408.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4524 = x4523 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][169 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4524);
reg = x4524;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4525 = Fp(x4404.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4526 = x4525 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4526);
reg = x4526;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4527 = Fp(x4408.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4528 = x4527 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][170 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4528);
reg = x4528;
}
// loc("cirgen/circuit/rv32im/compute.cpp":210:37)
auto x4529 = Fp(x4404.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":210:36)
auto x4530 = x4529 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4530);
reg = x4530;
}
// loc("cirgen/circuit/rv32im/compute.cpp":211:37)
auto x4531 = Fp(x4408.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/compute.cpp":211:36)
auto x4532 = x4531 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][171 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4532);
reg = x4532;
}
}
// loc("Top/Mux/4/Mux/6/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4533 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x4533 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4534 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x4534 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4535 = x4533 * x4534;
// loc("Top/Mux/4/Mux/6/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4536 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x4536 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4537 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x4537 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4538 = x4536 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4539 = x4533 + x4538;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4540 = x4537 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4541 = x4534 + x4540;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4542 = x4536 * x4537;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4543 = x4542 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4544 = x4535 + x4543;
// loc("Top/Mux/4/Mux/6/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4545 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x4545 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4546 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x4546 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4547 = x4545 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4548 = x4539 + x4547;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4549 = x4546 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4550 = x4541 + x4549;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4551 = x4545 * x4546;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4552 = x4551 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4553 = x4544 + x4552;
// loc("Top/Mux/4/Mux/6/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4554 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x4554 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4555 = args[2][143 * steps + ((cycle - 0) & mask)];
assert(x4555 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4556 = x4554 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4557 = x4548 + x4556;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4558 = x4555 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4559 = x4550 + x4558;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4560 = x4554 * x4555;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4561 = x4560 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4562 = x4553 + x4561;
// loc("Top/Mux/4/Mux/6/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4563 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x4563 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4564 = args[2][144 * steps + ((cycle - 0) & mask)];
assert(x4564 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4565 = x4563 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4566 = x4557 + x4565;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4567 = x4564 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4568 = x4559 + x4567;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4569 = x4563 * x4564;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4570 = x4569 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4571 = x4562 + x4570;
// loc("Top/Mux/4/Mux/6/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4572 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x4572 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4573 = args[2][145 * steps + ((cycle - 0) & mask)];
assert(x4573 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4574 = x4572 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4575 = x4566 + x4574;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4576 = x4573 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4577 = x4568 + x4576;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4578 = x4572 * x4573;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4579 = x4578 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4580 = x4571 + x4579;
// loc("Top/Mux/4/Mux/6/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4581 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x4581 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4582 = args[2][146 * steps + ((cycle - 0) & mask)];
assert(x4582 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4583 = x4581 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4584 = x4575 + x4583;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4585 = x4582 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4586 = x4577 + x4585;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4587 = x4581 * x4582;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4588 = x4587 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4589 = x4580 + x4588;
// loc("Top/Mux/4/Mux/6/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4590 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x4590 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4591 = args[2][147 * steps + ((cycle - 0) & mask)];
assert(x4591 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4592 = x4590 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4593 = x4584 + x4592;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4594 = x4591 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4595 = x4586 + x4594;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4596 = x4590 * x4591;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4597 = x4596 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4598 = x4589 + x4597;
// loc("Top/Mux/4/Mux/6/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4599 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x4599 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4600 = args[2][148 * steps + ((cycle - 0) & mask)];
assert(x4600 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4601 = x4599 * x4600;
// loc("Top/Mux/4/Mux/6/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4602 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x4602 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4603 = args[2][149 * steps + ((cycle - 0) & mask)];
assert(x4603 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4604 = x4602 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4605 = x4599 + x4604;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4606 = x4603 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4607 = x4600 + x4606;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4608 = x4602 * x4603;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4609 = x4608 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4610 = x4601 + x4609;
// loc("Top/Mux/4/Mux/6/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4611 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x4611 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4612 = args[2][150 * steps + ((cycle - 0) & mask)];
assert(x4612 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4613 = x4611 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4614 = x4605 + x4613;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4615 = x4612 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4616 = x4607 + x4615;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4617 = x4611 * x4612;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4618 = x4617 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4619 = x4610 + x4618;
// loc("Top/Mux/4/Mux/6/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4620 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x4620 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4621 = args[2][151 * steps + ((cycle - 0) & mask)];
assert(x4621 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4622 = x4620 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4623 = x4614 + x4622;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4624 = x4621 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4625 = x4616 + x4624;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4626 = x4620 * x4621;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4627 = x4626 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4628 = x4619 + x4627;
// loc("Top/Mux/4/Mux/6/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4629 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x4629 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4630 = args[2][152 * steps + ((cycle - 0) & mask)];
assert(x4630 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4631 = x4629 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4632 = x4623 + x4631;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4633 = x4630 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4634 = x4625 + x4633;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4635 = x4629 * x4630;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4636 = x4635 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4637 = x4628 + x4636;
// loc("Top/Mux/4/Mux/6/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4638 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x4638 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4639 = args[2][153 * steps + ((cycle - 0) & mask)];
assert(x4639 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4640 = x4638 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4641 = x4632 + x4640;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4642 = x4639 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4643 = x4634 + x4642;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4644 = x4638 * x4639;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4645 = x4644 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4646 = x4637 + x4645;
// loc("Top/Mux/4/Mux/6/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4647 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x4647 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4648 = args[2][154 * steps + ((cycle - 0) & mask)];
assert(x4648 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4649 = x4647 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4650 = x4641 + x4649;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4651 = x4648 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4652 = x4643 + x4651;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4653 = x4647 * x4648;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4654 = x4653 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4655 = x4646 + x4654;
// loc("Top/Mux/4/Mux/6/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4656 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x4656 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4657 = args[2][155 * steps + ((cycle - 0) & mask)];
assert(x4657 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4658 = x4656 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4659 = x4650 + x4658;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4660 = x4657 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4661 = x4652 + x4660;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4662 = x4656 * x4657;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4663 = x4662 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4664 = x4655 + x4663;
// loc("Top/Mux/4/Mux/6/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4665 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x4665 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4666 = args[2][156 * steps + ((cycle - 0) & mask)];
assert(x4666 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4667 = x4665 * x4666;
// loc("Top/Mux/4/Mux/6/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4668 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x4668 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4669 = args[2][157 * steps + ((cycle - 0) & mask)];
assert(x4669 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4670 = x4668 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4671 = x4665 + x4670;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4672 = x4669 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4673 = x4666 + x4672;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4674 = x4668 * x4669;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4675 = x4674 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4676 = x4667 + x4675;
// loc("Top/Mux/4/Mux/6/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4677 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x4677 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4678 = args[2][158 * steps + ((cycle - 0) & mask)];
assert(x4678 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4679 = x4677 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4680 = x4671 + x4679;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4681 = x4678 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4682 = x4673 + x4681;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4683 = x4677 * x4678;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4684 = x4683 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4685 = x4676 + x4684;
// loc("Top/Mux/4/Mux/6/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4686 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x4686 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4687 = args[2][159 * steps + ((cycle - 0) & mask)];
assert(x4687 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4688 = x4686 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4689 = x4680 + x4688;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4690 = x4687 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4691 = x4682 + x4690;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4692 = x4686 * x4687;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4693 = x4692 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4694 = x4685 + x4693;
// loc("Top/Mux/4/Mux/6/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4695 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x4695 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4696 = args[2][160 * steps + ((cycle - 0) & mask)];
assert(x4696 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4697 = x4695 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4698 = x4689 + x4697;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4699 = x4696 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4700 = x4691 + x4699;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4701 = x4695 * x4696;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4702 = x4701 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4703 = x4694 + x4702;
// loc("Top/Mux/4/Mux/6/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4704 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x4704 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4705 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x4705 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4706 = x4704 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4707 = x4698 + x4706;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4708 = x4705 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4709 = x4700 + x4708;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4710 = x4704 * x4705;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4711 = x4710 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4712 = x4703 + x4711;
// loc("Top/Mux/4/Mux/6/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4713 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x4713 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4714 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x4714 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4715 = x4713 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4716 = x4707 + x4715;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4717 = x4714 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4718 = x4709 + x4717;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4719 = x4713 * x4714;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4720 = x4719 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4721 = x4712 + x4720;
// loc("Top/Mux/4/Mux/6/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4722 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x4722 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4723 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x4723 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4724 = x4722 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4725 = x4716 + x4724;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4726 = x4723 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4727 = x4718 + x4726;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4728 = x4722 * x4723;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4729 = x4728 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4730 = x4721 + x4729;
// loc("Top/Mux/4/Mux/6/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4731 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x4731 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4732 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x4732 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4733 = x4731 * x4732;
// loc("Top/Mux/4/Mux/6/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4734 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x4734 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4735 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x4735 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4736 = x4734 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4737 = x4731 + x4736;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4738 = x4735 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4739 = x4732 + x4738;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4740 = x4734 * x4735;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4741 = x4740 * x99;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4742 = x4733 + x4741;
// loc("Top/Mux/4/Mux/6/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4743 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x4743 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4744 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x4744 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4745 = x4743 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4746 = x4737 + x4745;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4747 = x4744 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4748 = x4739 + x4747;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4749 = x4743 * x4744;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4750 = x4749 * x85;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4751 = x4742 + x4750;
// loc("Top/Mux/4/Mux/6/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4752 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x4752 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4753 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x4753 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4754 = x4752 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4755 = x4746 + x4754;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4756 = x4753 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4757 = x4748 + x4756;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4758 = x4752 * x4753;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4759 = x4758 * x77;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4760 = x4751 + x4759;
// loc("Top/Mux/4/Mux/6/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4761 = args[2][136 * steps + ((cycle - 0) & mask)];
assert(x4761 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4762 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x4762 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4763 = x4761 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4764 = x4755 + x4763;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4765 = x4762 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4766 = x4757 + x4765;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4767 = x4761 * x4762;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4768 = x4767 * x66;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4769 = x4760 + x4768;
// loc("Top/Mux/4/Mux/6/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4770 = args[2][137 * steps + ((cycle - 0) & mask)];
assert(x4770 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4771 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x4771 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4772 = x4770 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4773 = x4764 + x4772;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4774 = x4771 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4775 = x4766 + x4774;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4776 = x4770 * x4771;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4777 = x4776 * x68;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4778 = x4769 + x4777;
// loc("Top/Mux/4/Mux/6/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4779 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x4779 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4780 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x4780 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4781 = x4779 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4782 = x4773 + x4781;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4783 = x4780 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4784 = x4775 + x4783;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4785 = x4779 * x4780;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4786 = x4785 * x62;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4787 = x4778 + x4786;
// loc("Top/Mux/4/Mux/6/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4788 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x4788 != Fp::invalid());
// loc("Top/Mux/4/Mux/6/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4789 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x4789 != Fp::invalid());
// loc("cirgen/circuit/rv32im/compute.cpp":222:41)
auto x4790 = x4788 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":222:24)
auto x4791 = x4782 + x4790;
// loc("cirgen/circuit/rv32im/compute.cpp":223:41)
auto x4792 = x4789 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":223:24)
auto x4793 = x4784 + x4792;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4794 = x4788 * x4789;
// loc("cirgen/circuit/rv32im/compute.cpp":224:41)
auto x4795 = x4794 * x71;
// loc("cirgen/circuit/rv32im/compute.cpp":224:24)
auto x4796 = x4787 + x4795;
host_args.at(0) = x4401;
host_args.at(1) = x4402;
host_args.at(2) = x4403;
host_args.at(3) = x4404;
host_args.at(4) = x4593;
host_args.at(5) = x4659;
host_args.at(6) = x4725;
host_args.at(7) = x4791;
host(ctx, "log", " a = %w, ax = %w", host_args.data(), 8, host_outs.data(), 0);
host_args.at(0) = x4405;
host_args.at(1) = x4406;
host_args.at(2) = x4407;
host_args.at(3) = x4408;
host_args.at(4) = x4595;
host_args.at(5) = x4661;
host_args.at(6) = x4727;
host_args.at(7) = x4793;
host(ctx, "log", " b = %w, bx = %w", host_args.data(), 8, host_outs.data(), 0);
host_args.at(0) = x4409;
host_args.at(1) = x4410;
host_args.at(2) = x4411;
host_args.at(3) = x4412;
host_args.at(4) = x4598;
host_args.at(5) = x4664;
host_args.at(6) = x4730;
host_args.at(7) = x4796;
host(ctx, "log", " c = %w, cx = %w", host_args.data(), 8, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/compute.cpp":230:3)
auto x4797 = x4401 - x4593;
// loc("cirgen/circuit/rv32im/compute.cpp":230:3)
if (x4797 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:230");
// loc("cirgen/circuit/rv32im/compute.cpp":230:3)
auto x4798 = x4402 - x4659;
// loc("cirgen/circuit/rv32im/compute.cpp":230:3)
if (x4798 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:230");
// loc("cirgen/circuit/rv32im/compute.cpp":230:3)
auto x4799 = x4403 - x4725;
// loc("cirgen/circuit/rv32im/compute.cpp":230:3)
if (x4799 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:230");
// loc("cirgen/circuit/rv32im/compute.cpp":230:3)
auto x4800 = x4404 - x4791;
// loc("cirgen/circuit/rv32im/compute.cpp":230:3)
if (x4800 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:230");
// loc("cirgen/circuit/rv32im/compute.cpp":231:3)
auto x4801 = x4405 - x4595;
// loc("cirgen/circuit/rv32im/compute.cpp":231:3)
if (x4801 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:231");
// loc("cirgen/circuit/rv32im/compute.cpp":231:3)
auto x4802 = x4406 - x4661;
// loc("cirgen/circuit/rv32im/compute.cpp":231:3)
if (x4802 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:231");
// loc("cirgen/circuit/rv32im/compute.cpp":231:3)
auto x4803 = x4407 - x4727;
// loc("cirgen/circuit/rv32im/compute.cpp":231:3)
if (x4803 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:231");
// loc("cirgen/circuit/rv32im/compute.cpp":231:3)
auto x4804 = x4408 - x4793;
// loc("cirgen/circuit/rv32im/compute.cpp":231:3)
if (x4804 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:231");
// loc("cirgen/circuit/rv32im/compute.cpp":232:3)
auto x4805 = x4409 - x4598;
// loc("cirgen/circuit/rv32im/compute.cpp":232:3)
if (x4805 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:232");
// loc("cirgen/circuit/rv32im/compute.cpp":232:3)
auto x4806 = x4410 - x4664;
// loc("cirgen/circuit/rv32im/compute.cpp":232:3)
if (x4806 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:232");
// loc("cirgen/circuit/rv32im/compute.cpp":232:3)
auto x4807 = x4411 - x4730;
// loc("cirgen/circuit/rv32im/compute.cpp":232:3)
if (x4807 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:232");
// loc("cirgen/circuit/rv32im/compute.cpp":232:3)
auto x4808 = x4412 - x4796;
// loc("cirgen/circuit/rv32im/compute.cpp":232:3)
if (x4808 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/compute.cpp:232");
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x4809 = x603 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4810 = Fp(x4809.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4810);
reg = x4810;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x4811 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x4811 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4812 = x4809 - x4811;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4813 = x4812 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4814 = Fp(x4813.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4814);
reg = x4814;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x4815 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x4815 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4816 = x4813 - x4815;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4817 = x4816 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4818 = Fp(x4817.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4818);
reg = x4818;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x4819 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x4819 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4820 = x4817 - x4819;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4821 = x4820 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x4822 = Fp(x4821.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4822);
reg = x4822;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4823 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x4823 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x4824 = x4821 - x4823;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x4825 = x4824 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4825);
reg = x4825;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4826 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x4826 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x4827 = x102 - x4826;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x4828 = x4826 * x4827;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4828);
reg = x4828;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4829 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x4829 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x4830 = x99 - x4826;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x4831 = x4829 * x4830;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x4831 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("cirgen/circuit/rv32im/compute.cpp":235:3)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/OneHot/Reg7"("./cirgen/components/mux.h":37:25))
auto x4832 = args[2][101 * steps + ((cycle - 0) & mask)];
assert(x4832 != Fp::invalid());
if (x4832 != 0) {
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4833 = args[2][118 * steps + ((cycle - 1) & mask)];
assert(x4833 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x4834 = args[2][119 * steps + ((cycle - 1) & mask)];
assert(x4834 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x4835 = args[2][120 * steps + ((cycle - 1) & mask)];
assert(x4835 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x4836 = args[2][121 * steps + ((cycle - 1) & mask)];
assert(x4836 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4837 = args[2][25 * steps + ((cycle - 1) & mask)];
assert(x4837 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4838 = args[2][26 * steps + ((cycle - 1) & mask)];
assert(x4838 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4839 = args[2][27 * steps + ((cycle - 1) & mask)];
assert(x4839 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4840 = args[2][28 * steps + ((cycle - 1) & mask)];
assert(x4840 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4841 = args[2][29 * steps + ((cycle - 1) & mask)];
assert(x4841 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4842 = args[2][30 * steps + ((cycle - 1) & mask)];
assert(x4842 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4843 = args[2][31 * steps + ((cycle - 1) & mask)];
assert(x4843 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4844 = args[2][32 * steps + ((cycle - 1) & mask)];
assert(x4844 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4845 = args[2][33 * steps + ((cycle - 1) & mask)];
assert(x4845 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4846 = args[2][34 * steps + ((cycle - 1) & mask)];
assert(x4846 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4847 = args[2][35 * steps + ((cycle - 1) & mask)];
assert(x4847 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4848 = args[2][36 * steps + ((cycle - 1) & mask)];
assert(x4848 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/Reg"("cirgen/circuit/rv32im/divide.cpp":135:51))
auto x4849 = args[2][189 * steps + ((cycle - 1) & mask)];
assert(x4849 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/Reg1"("cirgen/circuit/rv32im/divide.cpp":136:51))
auto x4850 = args[2][190 * steps + ((cycle - 1) & mask)];
assert(x4850 != Fp::invalid());
{
// loc("cirgen/components/u32.cpp":120:18)
auto x4851 = Fp(x4836.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x4852 = x4851 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4852);
reg = x4852;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x4853 = Fp(x4836.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x4854 = x4853 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][13 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4854);
reg = x4854;
}
}
// loc("Top/Mux/4/Mux/7/TopBit/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4855 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x4855 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x4856 = x4855 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x4857 = args[2][13 * steps + ((cycle - 0) & mask)];
assert(x4857 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x4858 = x4857 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x4859 = x4856 + x4858;
// loc("cirgen/components/u32.cpp":123:6)
auto x4860 = x4836 - x4859;
// loc("cirgen/components/u32.cpp":123:6)
if (x4860 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
{
// loc("cirgen/components/u32.cpp":120:18)
auto x4861 = Fp(x4840.asUInt32() & x71.asUInt32());
// loc("cirgen/components/u32.cpp":120:17)
auto x4862 = x4861 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4862);
reg = x4862;
}
// loc("cirgen/components/u32.cpp":121:25)
auto x4863 = Fp(x4840.asUInt32() & x59.asUInt32());
// loc("cirgen/components/u32.cpp":121:24)
auto x4864 = x4863 * x99;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][14 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4864);
reg = x4864;
}
}
// loc("Top/Mux/4/Mux/7/TopBit1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4865 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x4865 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:19)
auto x4866 = x4865 * x71;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement2/Reg"("cirgen/components/bytes.cpp":78:10))
auto x4867 = args[2][14 * steps + ((cycle - 0) & mask)];
assert(x4867 != Fp::invalid());
// loc("cirgen/components/u32.cpp":123:34)
auto x4868 = x4867 * x63;
// loc("cirgen/components/u32.cpp":123:19)
auto x4869 = x4866 + x4868;
// loc("cirgen/components/u32.cpp":123:6)
auto x4870 = x4840 - x4869;
// loc("cirgen/components/u32.cpp":123:6)
if (x4870 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:123");
// loc("cirgen/circuit/rv32im/divide.cpp":139:17)
auto x4871 = x4849 * x4855;
// loc("cirgen/circuit/rv32im/divide.cpp":139:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4871);
reg = x4871;
}
// loc("cirgen/circuit/rv32im/divide.cpp":140:29)
auto x4872 = x102 - x4850;
// loc("cirgen/circuit/rv32im/divide.cpp":140:17)
auto x4873 = x4849 * x4872;
// loc("cirgen/circuit/rv32im/divide.cpp":140:17)
auto x4874 = x4873 * x4865;
// loc("cirgen/circuit/rv32im/divide.cpp":140:3)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4874);
reg = x4874;
}
// loc("Top/Mux/4/Mux/7/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4875 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x4875 != Fp::invalid());
// loc("cirgen/circuit/rv32im/divide.cpp":142:47)
auto x4876 = x102 - x4875;
// loc("cirgen/components/u32.cpp":105:20)
auto x4877 = x4876 * x4833;
// loc("cirgen/components/u32.cpp":105:20)
auto x4878 = x4876 * x4834;
// loc("cirgen/components/u32.cpp":105:20)
auto x4879 = x4876 * x4835;
// loc("cirgen/components/u32.cpp":105:20)
auto x4880 = x4876 * x4836;
// loc("cirgen/components/u32.cpp":89:20)
auto x4881 = x4877 + x97;
// loc("cirgen/components/u32.cpp":89:20)
auto x4882 = x4878 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x4883 = x4879 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x4884 = x4880 + x98;
// loc("cirgen/components/u32.cpp":105:20)
auto x4885 = x4875 * x4833;
// loc("cirgen/components/u32.cpp":105:20)
auto x4886 = x4875 * x4834;
// loc("cirgen/components/u32.cpp":105:20)
auto x4887 = x4875 * x4835;
// loc("cirgen/components/u32.cpp":105:20)
auto x4888 = x4875 * x4836;
// loc("cirgen/components/u32.cpp":97:20)
auto x4889 = x4881 - x4885;
// loc("cirgen/components/u32.cpp":97:20)
auto x4890 = x4882 - x4886;
// loc("cirgen/components/u32.cpp":97:20)
auto x4891 = x4883 - x4887;
// loc("cirgen/components/u32.cpp":97:20)
auto x4892 = x4884 - x4888;
// loc("cirgen/circuit/rv32im/divide.cpp":143:17)
auto x4893 = x4875 * x4850;
// loc("cirgen/components/u32.cpp":97:20)
auto x4894 = x4889 - x4893;
// loc("cirgen/components/u32.cpp":146:29)
auto x4895 = x4890 * x97;
// loc("cirgen/components/u32.cpp":146:15)
auto x4896 = x4894 + x4895;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4897 = Fp(x4896.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][15 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4897);
reg = x4897;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement2/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x4898 = args[2][15 * steps + ((cycle - 0) & mask)];
assert(x4898 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4899 = x4896 - x4898;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4900 = x4899 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4901 = Fp(x4900.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][16 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4901);
reg = x4901;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement3/Reg"("cirgen/components/bytes.cpp":83:16))
auto x4902 = args[2][16 * steps + ((cycle - 0) & mask)];
assert(x4902 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4903 = x4900 - x4902;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4904 = x4903 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][74 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4904);
reg = x4904;
}
// loc("Top/Mux/4/Mux/7/U32Normalize/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4905 = args[2][74 * steps + ((cycle - 0) & mask)];
assert(x4905 != Fp::invalid());
// loc("cirgen/components/u32.cpp":148:16)
auto x4906 = x4905 + x4891;
// loc("cirgen/components/u32.cpp":148:41)
auto x4907 = x4892 * x97;
// loc("cirgen/components/u32.cpp":148:16)
auto x4908 = x4906 + x4907;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4909 = Fp(x4908.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][17 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4909);
reg = x4909;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement3/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x4910 = args[2][17 * steps + ((cycle - 0) & mask)];
assert(x4910 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4911 = x4908 - x4910;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4912 = x4911 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4913 = Fp(x4912.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][18 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4913);
reg = x4913;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement4/Reg"("cirgen/components/bytes.cpp":83:16))
auto x4914 = args[2][18 * steps + ((cycle - 0) & mask)];
assert(x4914 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4915 = x4912 - x4914;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4916 = x4915 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][75 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4916);
reg = x4916;
}
host_args.at(0) = x4833;
host_args.at(1) = x4834;
host_args.at(2) = x4835;
host_args.at(3) = x4836;
host_args.at(4) = x4898;
host_args.at(5) = x4902;
host_args.at(6) = x4910;
host_args.at(7) = x4914;
host(ctx, "log", " numer = %w, numerAbs = %w", host_args.data(), 8, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/7/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4917 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x4917 != Fp::invalid());
// loc("cirgen/circuit/rv32im/divide.cpp":145:47)
auto x4918 = x102 - x4917;
// loc("cirgen/components/u32.cpp":105:20)
auto x4919 = x4918 * x4837;
// loc("cirgen/components/u32.cpp":105:20)
auto x4920 = x4918 * x4838;
// loc("cirgen/components/u32.cpp":105:20)
auto x4921 = x4918 * x4839;
// loc("cirgen/components/u32.cpp":105:20)
auto x4922 = x4918 * x4840;
// loc("cirgen/components/u32.cpp":89:20)
auto x4923 = x4919 + x97;
// loc("cirgen/components/u32.cpp":89:20)
auto x4924 = x4920 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x4925 = x4921 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x4926 = x4922 + x98;
// loc("cirgen/components/u32.cpp":105:20)
auto x4927 = x4917 * x4837;
// loc("cirgen/components/u32.cpp":105:20)
auto x4928 = x4917 * x4838;
// loc("cirgen/components/u32.cpp":105:20)
auto x4929 = x4917 * x4839;
// loc("cirgen/components/u32.cpp":105:20)
auto x4930 = x4917 * x4840;
// loc("cirgen/components/u32.cpp":97:20)
auto x4931 = x4923 - x4927;
// loc("cirgen/components/u32.cpp":97:20)
auto x4932 = x4924 - x4928;
// loc("cirgen/components/u32.cpp":97:20)
auto x4933 = x4925 - x4929;
// loc("cirgen/components/u32.cpp":97:20)
auto x4934 = x4926 - x4930;
// loc("cirgen/circuit/rv32im/divide.cpp":146:17)
auto x4935 = x4917 * x4850;
// loc("cirgen/components/u32.cpp":97:20)
auto x4936 = x4931 - x4935;
// loc("cirgen/components/u32.cpp":146:29)
auto x4937 = x4932 * x97;
// loc("cirgen/components/u32.cpp":146:15)
auto x4938 = x4936 + x4937;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4939 = Fp(x4938.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][19 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4939);
reg = x4939;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement4/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x4940 = args[2][19 * steps + ((cycle - 0) & mask)];
assert(x4940 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4941 = x4938 - x4940;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4942 = x4941 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4943 = Fp(x4942.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][20 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4943);
reg = x4943;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg"("cirgen/components/bytes.cpp":83:16))
auto x4944 = args[2][20 * steps + ((cycle - 0) & mask)];
assert(x4944 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4945 = x4942 - x4944;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4946 = x4945 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][76 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4946);
reg = x4946;
}
// loc("Top/Mux/4/Mux/7/U32Normalize1/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4947 = args[2][76 * steps + ((cycle - 0) & mask)];
assert(x4947 != Fp::invalid());
// loc("cirgen/components/u32.cpp":148:16)
auto x4948 = x4947 + x4933;
// loc("cirgen/components/u32.cpp":148:41)
auto x4949 = x4934 * x97;
// loc("cirgen/components/u32.cpp":148:16)
auto x4950 = x4948 + x4949;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4951 = Fp(x4950.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][21 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4951);
reg = x4951;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x4952 = args[2][21 * steps + ((cycle - 0) & mask)];
assert(x4952 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4953 = x4950 - x4952;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4954 = x4953 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x4955 = Fp(x4954.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][22 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4955);
reg = x4955;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg"("cirgen/components/bytes.cpp":83:16))
auto x4956 = args[2][22 * steps + ((cycle - 0) & mask)];
assert(x4956 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x4957 = x4954 - x4956;
// loc("cirgen/components/bytes.cpp":83:10)
auto x4958 = x4957 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][77 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4958);
reg = x4958;
}
host_args.at(0) = x4837;
host_args.at(1) = x4838;
host_args.at(2) = x4839;
host_args.at(3) = x4840;
host_args.at(4) = x4940;
host_args.at(5) = x4944;
host_args.at(6) = x4952;
host_args.at(7) = x4956;
host(ctx, "log", " demom = %w, denomAbs = %w", host_args.data(), 8, host_outs.data(), 0);
// loc("cirgen/components/u32.cpp":137:26)
auto x4959 = x4944 * x97;
// loc("cirgen/components/u32.cpp":137:12)
auto x4960 = x4940 + x4959;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x4961 = (x4960 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4961);
reg = x4961;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x4962 = inv(x4960);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4962);
reg = x4962;
}
}
// loc("Top/Mux/4/Mux/7/IsZeroU32/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4963 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x4963 != Fp::invalid());
if (x4963 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x4960 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x4964 = x102 - x4963;
if (x4964 != 0) {
// loc("Top/Mux/4/Mux/7/IsZeroU32/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4965 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x4965 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x4966 = x4960 * x4965;
// loc("cirgen/components/iszero.cpp":15:26)
auto x4967 = x4966 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x4967 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("cirgen/components/u32.cpp":138:27)
auto x4968 = x4956 * x97;
// loc("cirgen/components/u32.cpp":138:13)
auto x4969 = x4952 + x4968;
// loc("cirgen/components/u32.cpp":138:47)
auto x4970 = x4964 * x87;
// loc("cirgen/components/u32.cpp":138:13)
auto x4971 = x4969 + x4970;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x4972 = (x4971 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4972);
reg = x4972;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x4973 = inv(x4971);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4973);
reg = x4973;
}
}
// loc("Top/Mux/4/Mux/7/IsZeroU32/IsZero1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x4974 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x4974 != Fp::invalid());
if (x4974 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x4971 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x4975 = x102 - x4974;
if (x4975 != 0) {
// loc("Top/Mux/4/Mux/7/IsZeroU32/IsZero1/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4976 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x4976 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x4977 = x4971 * x4976;
// loc("cirgen/components/iszero.cpp":15:26)
auto x4978 = x4977 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x4978 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("cirgen/circuit/rv32im/divide.cpp":149:16)
auto x4979 = x4875 + x4917;
// loc("cirgen/circuit/rv32im/divide.cpp":149:38)
auto x4980 = x4875 * x99;
// loc("cirgen/circuit/rv32im/divide.cpp":149:38)
auto x4981 = x4980 * x4917;
// loc("cirgen/circuit/rv32im/divide.cpp":149:16)
auto x4982 = x4979 - x4981;
// loc("cirgen/circuit/rv32im/divide.cpp":149:64)
auto x4983 = x4974 * x4875;
// loc("cirgen/circuit/rv32im/divide.cpp":149:16)
auto x4984 = x4982 - x4983;
// loc("cirgen/circuit/rv32im/divide.cpp":149:3)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4984);
reg = x4984;
}
// loc("Top/Mux/4/Mux/7/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x4985 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x4985 != Fp::invalid());
// loc("cirgen/circuit/rv32im/divide.cpp":151:46)
auto x4986 = x102 - x4985;
// loc("cirgen/components/u32.cpp":105:20)
auto x4987 = x4986 * x4841;
// loc("cirgen/components/u32.cpp":105:20)
auto x4988 = x4986 * x4842;
// loc("cirgen/components/u32.cpp":105:20)
auto x4989 = x4986 * x4843;
// loc("cirgen/components/u32.cpp":105:20)
auto x4990 = x4986 * x4844;
// loc("cirgen/components/u32.cpp":89:20)
auto x4991 = x4987 + x97;
// loc("cirgen/components/u32.cpp":89:20)
auto x4992 = x4988 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x4993 = x4989 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x4994 = x4990 + x98;
// loc("cirgen/components/u32.cpp":105:20)
auto x4995 = x4985 * x4841;
// loc("cirgen/components/u32.cpp":105:20)
auto x4996 = x4985 * x4842;
// loc("cirgen/components/u32.cpp":105:20)
auto x4997 = x4985 * x4843;
// loc("cirgen/components/u32.cpp":105:20)
auto x4998 = x4985 * x4844;
// loc("cirgen/components/u32.cpp":97:20)
auto x4999 = x4991 - x4995;
// loc("cirgen/components/u32.cpp":97:20)
auto x5000 = x4992 - x4996;
// loc("cirgen/components/u32.cpp":97:20)
auto x5001 = x4993 - x4997;
// loc("cirgen/components/u32.cpp":97:20)
auto x5002 = x4994 - x4998;
// loc("cirgen/circuit/rv32im/divide.cpp":152:16)
auto x5003 = x4985 * x4850;
// loc("cirgen/components/u32.cpp":97:20)
auto x5004 = x4999 - x5003;
// loc("cirgen/components/u32.cpp":146:29)
auto x5005 = x5000 * x97;
// loc("cirgen/components/u32.cpp":146:15)
auto x5006 = x5004 + x5005;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5007 = Fp(x5006.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][23 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5007);
reg = x5007;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5008 = args[2][23 * steps + ((cycle - 0) & mask)];
assert(x5008 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5009 = x5006 - x5008;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5010 = x5009 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5011 = Fp(x5010.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][24 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5011);
reg = x5011;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5012 = args[2][24 * steps + ((cycle - 0) & mask)];
assert(x5012 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5013 = x5010 - x5012;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5014 = x5013 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][78 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5014);
reg = x5014;
}
// loc("Top/Mux/4/Mux/7/U32Normalize2/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5015 = args[2][78 * steps + ((cycle - 0) & mask)];
assert(x5015 != Fp::invalid());
// loc("cirgen/components/u32.cpp":148:16)
auto x5016 = x5015 + x5001;
// loc("cirgen/components/u32.cpp":148:41)
auto x5017 = x5002 * x97;
// loc("cirgen/components/u32.cpp":148:16)
auto x5018 = x5016 + x5017;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5019 = Fp(x5018.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5019);
reg = x5019;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5020 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x5020 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5021 = x5018 - x5020;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5022 = x5021 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5023 = Fp(x5022.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5023);
reg = x5023;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5024 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x5024 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5025 = x5022 - x5024;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5026 = x5025 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5026);
reg = x5026;
}
host_args.at(0) = x4841;
host_args.at(1) = x4842;
host_args.at(2) = x4843;
host_args.at(3) = x4844;
host_args.at(4) = x5008;
host_args.at(5) = x5012;
host_args.at(6) = x5020;
host_args.at(7) = x5024;
host(ctx, "log", " quot = %w, quotAbs = %w", host_args.data(), 8, host_outs.data(), 0);
// loc("cirgen/components/u32.cpp":105:20)
auto x5027 = x4876 * x4845;
// loc("cirgen/components/u32.cpp":105:20)
auto x5028 = x4876 * x4846;
// loc("cirgen/components/u32.cpp":105:20)
auto x5029 = x4876 * x4847;
// loc("cirgen/components/u32.cpp":105:20)
auto x5030 = x4876 * x4848;
// loc("cirgen/components/u32.cpp":89:20)
auto x5031 = x5027 + x97;
// loc("cirgen/components/u32.cpp":89:20)
auto x5032 = x5028 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x5033 = x5029 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x5034 = x5030 + x98;
// loc("cirgen/components/u32.cpp":105:20)
auto x5035 = x4875 * x4845;
// loc("cirgen/components/u32.cpp":105:20)
auto x5036 = x4875 * x4846;
// loc("cirgen/components/u32.cpp":105:20)
auto x5037 = x4875 * x4847;
// loc("cirgen/components/u32.cpp":105:20)
auto x5038 = x4875 * x4848;
// loc("cirgen/components/u32.cpp":97:20)
auto x5039 = x5031 - x5035;
// loc("cirgen/components/u32.cpp":97:20)
auto x5040 = x5032 - x5036;
// loc("cirgen/components/u32.cpp":97:20)
auto x5041 = x5033 - x5037;
// loc("cirgen/components/u32.cpp":97:20)
auto x5042 = x5034 - x5038;
// loc("cirgen/components/u32.cpp":97:20)
auto x5043 = x5039 - x4893;
// loc("cirgen/components/u32.cpp":146:29)
auto x5044 = x5040 * x97;
// loc("cirgen/components/u32.cpp":146:15)
auto x5045 = x5043 + x5044;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5046 = Fp(x5045.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5046);
reg = x5046;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5047 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x5047 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5048 = x5045 - x5047;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5049 = x5048 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5050 = Fp(x5049.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5050);
reg = x5050;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5051 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x5051 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5052 = x5049 - x5051;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5053 = x5052 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5053);
reg = x5053;
}
// loc("Top/Mux/4/Mux/7/U32Normalize3/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5054 = args[2][80 * steps + ((cycle - 0) & mask)];
assert(x5054 != Fp::invalid());
// loc("cirgen/components/u32.cpp":148:16)
auto x5055 = x5054 + x5041;
// loc("cirgen/components/u32.cpp":148:41)
auto x5056 = x5042 * x97;
// loc("cirgen/components/u32.cpp":148:16)
auto x5057 = x5055 + x5056;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5058 = Fp(x5057.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5058);
reg = x5058;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5059 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x5059 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5060 = x5057 - x5059;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5061 = x5060 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5062 = Fp(x5061.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5062);
reg = x5062;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5063 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x5063 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5064 = x5061 - x5063;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5065 = x5064 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5065);
reg = x5065;
}
host_args.at(0) = x4845;
host_args.at(1) = x4846;
host_args.at(2) = x4847;
host_args.at(3) = x4848;
host_args.at(4) = x5047;
host_args.at(5) = x5051;
host_args.at(6) = x5059;
host_args.at(7) = x5063;
host(ctx, "log", " rem = %w, remAbs = %w", host_args.data(), 8, host_outs.data(), 0);
// loc("cirgen/components/u32.cpp":89:20)
auto x5066 = x4940 + x97;
// loc("cirgen/components/u32.cpp":89:20)
auto x5067 = x4944 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x5068 = x4952 + x98;
// loc("cirgen/components/u32.cpp":89:20)
auto x5069 = x4956 + x98;
// loc("cirgen/components/u32.cpp":97:20)
auto x5070 = x5066 - x102;
// loc("cirgen/components/u32.cpp":97:20)
auto x5071 = x5070 - x5047;
// loc("cirgen/components/u32.cpp":97:20)
auto x5072 = x5067 - x5051;
// loc("cirgen/components/u32.cpp":97:20)
auto x5073 = x5068 - x5059;
// loc("cirgen/components/u32.cpp":97:20)
auto x5074 = x5069 - x5063;
// loc("cirgen/components/u32.cpp":146:29)
auto x5075 = x5072 * x97;
// loc("cirgen/components/u32.cpp":146:15)
auto x5076 = x5071 + x5075;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5077 = Fp(x5076.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5077);
reg = x5077;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5078 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x5078 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5079 = x5076 - x5078;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5080 = x5079 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5081 = Fp(x5080.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5081);
reg = x5081;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5082 = args[2][32 * steps + ((cycle - 0) & mask)];
assert(x5082 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5083 = x5080 - x5082;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5084 = x5083 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5084);
reg = x5084;
}
// loc("Top/Mux/4/Mux/7/U32Normalize4/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5085 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x5085 != Fp::invalid());
// loc("cirgen/components/u32.cpp":148:16)
auto x5086 = x5085 + x5073;
// loc("cirgen/components/u32.cpp":148:41)
auto x5087 = x5074 * x97;
// loc("cirgen/components/u32.cpp":148:16)
auto x5088 = x5086 + x5087;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5089 = Fp(x5088.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5089);
reg = x5089;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5090 = args[2][33 * steps + ((cycle - 0) & mask)];
assert(x5090 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5091 = x5088 - x5090;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5092 = x5091 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5093 = Fp(x5092.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5093);
reg = x5093;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5094 = args[2][34 * steps + ((cycle - 0) & mask)];
assert(x5094 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5095 = x5092 - x5094;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5096 = x5095 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5096);
reg = x5096;
}
// loc("cirgen/components/u32.cpp":260:14)
auto x5097 = x5008 * x4940;
// loc("cirgen/components/u32.cpp":260:14)
auto x5098 = x5097 + x5047;
// loc("cirgen/components/u32.cpp":261:21)
auto x5099 = x5008 * x4944;
// loc("cirgen/components/u32.cpp":261:51)
auto x5100 = x5012 * x4940;
// loc("cirgen/components/u32.cpp":261:21)
auto x5101 = x5099 + x5100;
// loc("cirgen/components/u32.cpp":261:21)
auto x5102 = x5101 + x5051;
// loc("cirgen/components/u32.cpp":261:14)
auto x5103 = x5102 * x97;
// loc("cirgen/components/u32.cpp":260:14)
auto x5104 = x5098 + x5103;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5105 = Fp(x5104.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5105);
reg = x5105;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5106 = args[2][35 * steps + ((cycle - 0) & mask)];
assert(x5106 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5107 = x5104 - x5106;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5108 = x5107 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5109 = Fp(x5108.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5109);
reg = x5109;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5110 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x5110 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5111 = x5108 - x5110;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5112 = x5111 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5113 = Fp(x5112.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5113);
reg = x5113;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5114 = args[2][39 * steps + ((cycle - 0) & mask)];
assert(x5114 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5115 = x5112 - x5114;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5116 = x5115 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5116);
reg = x5116;
}
// loc("Top/Mux/4/Mux/7/U32MulAcc/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5117 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x5117 != Fp::invalid());
// loc("cirgen/components/u32.cpp":264:15)
auto x5118 = x5117 * x97;
// loc("cirgen/components/u32.cpp":264:15)
auto x5119 = x5118 + x5114;
// loc("cirgen/components/u32.cpp":266:7)
auto x5120 = x5012 * x4956;
// loc("cirgen/components/u32.cpp":266:7)
if (x5120 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:266");
// loc("cirgen/components/u32.cpp":267:7)
auto x5121 = x5020 * x4952;
// loc("cirgen/components/u32.cpp":267:7)
if (x5121 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:267");
// loc("cirgen/components/u32.cpp":268:7)
auto x5122 = x5024 * x4944;
// loc("cirgen/components/u32.cpp":268:7)
if (x5122 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:268");
// loc("cirgen/components/u32.cpp":269:7)
auto x5123 = x5020 * x4956;
// loc("cirgen/components/u32.cpp":269:7)
if (x5123 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:269");
// loc("cirgen/components/u32.cpp":270:7)
auto x5124 = x5024 * x4952;
// loc("cirgen/components/u32.cpp":270:7)
if (x5124 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:270");
// loc("cirgen/components/u32.cpp":271:7)
auto x5125 = x5024 * x4956;
// loc("cirgen/components/u32.cpp":271:7)
if (x5125 != 0) throw std::runtime_error("eqz failed at: cirgen/components/u32.cpp:271");
// loc("cirgen/components/u32.cpp":273:15)
auto x5126 = x5020 * x4940;
// loc("cirgen/components/u32.cpp":273:45)
auto x5127 = x5012 * x4944;
// loc("cirgen/components/u32.cpp":273:15)
auto x5128 = x5126 + x5127;
// loc("cirgen/components/u32.cpp":274:15)
auto x5129 = x5008 * x4952;
// loc("cirgen/components/u32.cpp":273:15)
auto x5130 = x5128 + x5129;
// loc("cirgen/components/u32.cpp":273:15)
auto x5131 = x5130 + x5059;
// loc("cirgen/components/u32.cpp":273:15)
auto x5132 = x5131 + x5119;
// loc("cirgen/components/u32.cpp":275:22)
auto x5133 = x5024 * x4940;
// loc("cirgen/components/u32.cpp":275:52)
auto x5134 = x5020 * x4944;
// loc("cirgen/components/u32.cpp":275:22)
auto x5135 = x5133 + x5134;
// loc("cirgen/components/u32.cpp":276:22)
auto x5136 = x5012 * x4952;
// loc("cirgen/components/u32.cpp":275:22)
auto x5137 = x5135 + x5136;
// loc("cirgen/components/u32.cpp":276:52)
auto x5138 = x5008 * x4956;
// loc("cirgen/components/u32.cpp":275:22)
auto x5139 = x5137 + x5138;
// loc("cirgen/components/u32.cpp":275:22)
auto x5140 = x5139 + x5063;
// loc("cirgen/components/u32.cpp":275:15)
auto x5141 = x5140 * x97;
// loc("cirgen/components/u32.cpp":273:15)
auto x5142 = x5132 + x5141;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5143 = Fp(x5142.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5143);
reg = x5143;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5144 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x5144 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5145 = x5142 - x5144;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5146 = x5145 * x96;
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5146);
reg = x5146;
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("cirgen/components/bytes.cpp":78:10))
auto x5147 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x5147 != Fp::invalid());
// loc("Top/Mux/4/Mux/7/U32Normalize4/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5148 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x5148 != Fp::invalid());
host_args.at(0) = x5106;
host_args.at(1) = x5110;
host_args.at(2) = x5144;
host_args.at(3) = x5147;
host_args.at(4) = x5148;
host(ctx, "log", " mul->getOut() = %w, denomRemCheck->carry = %u", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/divide.cpp":161:3)
auto x5149 = x5106 - x4898;
// loc("cirgen/circuit/rv32im/divide.cpp":161:3)
if (x5149 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/divide.cpp:161");
// loc("cirgen/circuit/rv32im/divide.cpp":161:3)
auto x5150 = x5110 - x4902;
// loc("cirgen/circuit/rv32im/divide.cpp":161:3)
if (x5150 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/divide.cpp:161");
// loc("cirgen/circuit/rv32im/divide.cpp":161:3)
auto x5151 = x5144 - x4910;
// loc("cirgen/circuit/rv32im/divide.cpp":161:3)
if (x5151 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/divide.cpp:161");
// loc("cirgen/circuit/rv32im/divide.cpp":161:3)
auto x5152 = x5147 - x4914;
// loc("cirgen/circuit/rv32im/divide.cpp":161:3)
if (x5152 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/divide.cpp:161");
if (x4975 != 0) {
// loc("cirgen/circuit/rv32im/divide.cpp":162:36)
auto x5153 = x5148 - x102;
// loc("cirgen/circuit/rv32im/divide.cpp":162:36)
if (x5153 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/divide.cpp:162");
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x5154 = x603 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5155 = Fp(x5154.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5155);
reg = x5155;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5156 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x5156 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5157 = x5154 - x5156;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5158 = x5157 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5159 = Fp(x5158.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5159);
reg = x5159;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5160 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x5160 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5161 = x5158 - x5160;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5162 = x5161 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5163 = Fp(x5162.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5163);
reg = x5163;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5164 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x5164 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5165 = x5162 - x5164;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5166 = x5165 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x5167 = Fp(x5166.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5167);
reg = x5167;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5168 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x5168 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x5169 = x5166 - x5168;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x5170 = x5169 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5170);
reg = x5170;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5171 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x5171 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x5172 = x102 - x5171;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x5173 = x5171 * x5172;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5173);
reg = x5173;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5174 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x5174 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x5175 = x99 - x5171;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x5176 = x5174 * x5175;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x5176 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("cirgen/circuit/rv32im/divide.cpp":164:3)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
// loc("Top/Mux/4/OneHot/Reg8"("./cirgen/components/mux.h":37:25))
auto x5177 = args[2][102 * steps + ((cycle - 0) & mask)];
assert(x5177 != Fp::invalid());
if (x5177 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5178 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x5178 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ecall.cpp":122:41)
auto x5179 = x603 * x83;
{
host_args.at(0) = x5179;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5180 = host_outs.at(0);
auto x5181 = host_outs.at(1);
auto x5182 = host_outs.at(2);
auto x5183 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5180);
reg = x5180;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5181);
reg = x5181;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5182);
reg = x5182;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5183);
reg = x5183;
}
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5184 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x5184 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5185 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x5185 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5186 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x5186 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5187 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x5187 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5179);
reg = x5179;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5178);
reg = x5178;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5184);
reg = x5184;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5185);
reg = x5185;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5186);
reg = x5186;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5187);
reg = x5187;
}
// loc("cirgen/circuit/rv32im/ecall.cpp":124:6)
auto x5188 = x5184 - x36;
// loc("cirgen/circuit/rv32im/ecall.cpp":124:6)
if (x5188 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ecall.cpp:124");
// loc("cirgen/circuit/rv32im/ecall.cpp":125:7)
if (x5185 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ecall.cpp:125");
// loc("cirgen/circuit/rv32im/ecall.cpp":126:7)
if (x5186 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ecall.cpp:126");
// loc("cirgen/circuit/rv32im/ecall.cpp":127:7)
if (x5187 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ecall.cpp:127");
{
host_args.at(0) = x35;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5189 = host_outs.at(0);
auto x5190 = host_outs.at(1);
auto x5191 = host_outs.at(2);
auto x5192 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5189);
reg = x5189;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5190);
reg = x5190;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5191);
reg = x5191;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5192);
reg = x5192;
}
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5193 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x5193 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5194 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x5194 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5195 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x5195 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5196 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x5196 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x35);
reg = x35;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5178);
reg = x5178;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5193);
reg = x5193;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5194);
reg = x5194;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5195);
reg = x5195;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5196);
reg = x5196;
}
{
// loc("./cirgen/components/onehot.h":35:26)
auto x5197 = (x5193 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5197);
reg = x5197;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5198 = x5193 - x102;
// loc("./cirgen/components/onehot.h":35:26)
auto x5199 = (x5198 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5199);
reg = x5199;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5200 = x5193 - x99;
// loc("./cirgen/components/onehot.h":35:26)
auto x5201 = (x5200 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5201);
reg = x5201;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5202 = x5193 - x84;
// loc("./cirgen/components/onehot.h":35:26)
auto x5203 = (x5202 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5203);
reg = x5203;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5204 = x5193 - x85;
// loc("./cirgen/components/onehot.h":35:26)
auto x5205 = (x5204 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5205);
reg = x5205;
}
}
// loc("Top/Mux/4/Mux/8/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5206 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x5206 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5207 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x5207 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5208 = x5207 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x5209 = x5206 + x5208;
// loc("Top/Mux/4/Mux/8/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5210 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x5210 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5211 = x5210 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x5212 = x5209 + x5211;
// loc("Top/Mux/4/Mux/8/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5213 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x5213 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5214 = x5213 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x5215 = x5212 + x5214;
// loc("./cirgen/components/onehot.h":38:8)
auto x5216 = x5215 - x5193;
// loc("./cirgen/components/onehot.h":38:8)
if (x5216 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
{
// loc("cirgen/circuit/rv32im/ecall.cpp":134:47)
auto x5217 = (x5215 == 0) ? Fp(1) : Fp(0);
// loc("cirgen/circuit/rv32im/ecall.cpp":134:47)
auto x5218 = x102 - x5217;
if (x5218 != 0) {
host_args.at(0) = x5193;
host_args.at(1) = x5194;
host_args.at(2) = x5195;
host_args.at(3) = x5196;
host(ctx, "log", " ecall, selector = %w", host_args.data(), 4, host_outs.data(), 0);
}
}
// loc("Top/Mux/4/Mux/8/OneHot/Reg"("./cirgen/components/mux.h":37:25))
auto x5219 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x5219 != Fp::invalid());
if (x5219 != 0) {
{
host_args.at(0) = x5193;
host_args.at(1) = x5194;
host_args.at(2) = x5195;
host_args.at(3) = x5196;
host(ctx, "halt", "", host_args.data(), 4, host_outs.data(), 0);
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x5220 = x603 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5221 = Fp(x5220.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5221);
reg = x5221;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5222 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x5222 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5223 = x5220 - x5222;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5224 = x5223 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5225 = Fp(x5224.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5225);
reg = x5225;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5226 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x5226 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5227 = x5224 - x5226;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5228 = x5227 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5229 = Fp(x5228.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5229);
reg = x5229;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5230 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x5230 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5231 = x5228 - x5230;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5232 = x5231 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x5233 = Fp(x5232.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5233);
reg = x5233;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5234 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x5234 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x5235 = x5232 - x5234;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x5236 = x5235 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5236);
reg = x5236;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5237 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x5237 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x5238 = x102 - x5237;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x5239 = x5237 * x5238;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5239);
reg = x5239;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5240 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x5240 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x5241 = x99 - x5237;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x5242 = x5240 * x5241;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x5242 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("cirgen/circuit/rv32im/ecall.cpp":24:3)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x77);
reg = x77;
}
}
if (x5206 != 0) {
{
host_args.at(0) = x34;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5243 = host_outs.at(0);
auto x5244 = host_outs.at(1);
auto x5245 = host_outs.at(2);
auto x5246 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5243);
reg = x5243;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5244);
reg = x5244;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5245);
reg = x5245;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5246);
reg = x5246;
}
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5247 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x5247 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5248 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x5248 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5249 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x5249 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5250 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x5250 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x34);
reg = x34;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5178);
reg = x5178;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5247);
reg = x5247;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5248);
reg = x5248;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5249);
reg = x5249;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5250);
reg = x5250;
}
{
host_args.at(0) = x33;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5251 = host_outs.at(0);
auto x5252 = host_outs.at(1);
auto x5253 = host_outs.at(2);
auto x5254 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5251);
reg = x5251;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5252);
reg = x5252;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5253);
reg = x5253;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5254);
reg = x5254;
}
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5255 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x5255 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5256 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x5256 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5257 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x5257 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5258 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x5258 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x33);
reg = x33;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5178);
reg = x5178;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5255);
reg = x5255;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5256);
reg = x5256;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5257);
reg = x5257;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5258);
reg = x5258;
}
{
// loc("./cirgen/components/onehot.h":35:26)
auto x5259 = (x5247 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5259);
reg = x5259;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5260 = x5247 - x102;
// loc("./cirgen/components/onehot.h":35:26)
auto x5261 = (x5260 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5261);
reg = x5261;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5262 = x5247 - x99;
// loc("./cirgen/components/onehot.h":35:26)
auto x5263 = (x5262 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5263);
reg = x5263;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5264 = x5247 - x84;
// loc("./cirgen/components/onehot.h":35:26)
auto x5265 = (x5264 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5265);
reg = x5265;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5266 = x5247 - x85;
// loc("./cirgen/components/onehot.h":35:26)
auto x5267 = (x5266 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5267);
reg = x5267;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5268 = x5247 - x80;
// loc("./cirgen/components/onehot.h":35:26)
auto x5269 = (x5268 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5269);
reg = x5269;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5270 = x5247 - x79;
// loc("./cirgen/components/onehot.h":35:26)
auto x5271 = (x5270 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5271);
reg = x5271;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5272 = x5247 - x78;
// loc("./cirgen/components/onehot.h":35:26)
auto x5273 = (x5272 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5273);
reg = x5273;
}
// loc("./cirgen/components/onehot.h":35:26)
auto x5274 = x5247 - x77;
// loc("./cirgen/components/onehot.h":35:26)
auto x5275 = (x5274 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5275);
reg = x5275;
}
}
// loc("Top/Mux/4/Mux/8/Mux/1/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5276 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x5276 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/Mux/1/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5277 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x5277 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5278 = x5277 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x5279 = x5276 + x5278;
// loc("Top/Mux/4/Mux/8/Mux/1/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5280 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x5280 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5281 = x5280 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x5282 = x5279 + x5281;
// loc("Top/Mux/4/Mux/8/Mux/1/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5283 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x5283 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5284 = x5283 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x5285 = x5282 + x5284;
// loc("Top/Mux/4/Mux/8/Mux/1/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5286 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x5286 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5287 = x5286 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x5288 = x5285 + x5287;
// loc("Top/Mux/4/Mux/8/Mux/1/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5289 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x5289 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5290 = x5289 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x5291 = x5288 + x5290;
// loc("Top/Mux/4/Mux/8/Mux/1/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5292 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x5292 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5293 = x5292 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x5294 = x5291 + x5293;
// loc("Top/Mux/4/Mux/8/Mux/1/OneHot/Reg8"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5295 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x5295 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5296 = x5295 * x77;
// loc("./cirgen/components/onehot.h":44:13)
auto x5297 = x5294 + x5296;
// loc("./cirgen/components/onehot.h":38:8)
auto x5298 = x5297 - x5247;
// loc("./cirgen/components/onehot.h":38:8)
if (x5298 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
// loc("Top/Mux/4/Mux/8/Mux/1/OneHot/Reg"("cirgen/circuit/rv32im/ecall.cpp":43:24))
auto x5299 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x5299 != Fp::invalid());
if (x5299 != 0) {
host_args.at(0) = x5297;
host_args.at(1) = x5255;
host_args.at(2) = x5256;
host_args.at(3) = x5257;
host_args.at(4) = x5258;
host(ctx, "log", " OUTPUT to %u: %w", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5300 = x5256 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5301 = x5300 + x5255;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:7)
args[1][36] = x5301;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5302 = x5258 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5303 = x5302 + x5257;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:7)
args[1][37] = x5303;
}
if (x5276 != 0) {
host_args.at(0) = x5297;
host_args.at(1) = x5255;
host_args.at(2) = x5256;
host_args.at(3) = x5257;
host_args.at(4) = x5258;
host(ctx, "log", " OUTPUT to %u: %w", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5304 = x5256 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5305 = x5304 + x5255;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:7)
args[1][38] = x5305;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5306 = x5258 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5307 = x5306 + x5257;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:7)
args[1][39] = x5307;
}
if (x5277 != 0) {
host_args.at(0) = x5297;
host_args.at(1) = x5255;
host_args.at(2) = x5256;
host_args.at(3) = x5257;
host_args.at(4) = x5258;
host(ctx, "log", " OUTPUT to %u: %w", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5308 = x5256 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5309 = x5308 + x5255;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:7)
args[1][40] = x5309;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5310 = x5258 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5311 = x5310 + x5257;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:7)
args[1][41] = x5311;
}
if (x5280 != 0) {
host_args.at(0) = x5297;
host_args.at(1) = x5255;
host_args.at(2) = x5256;
host_args.at(3) = x5257;
host_args.at(4) = x5258;
host(ctx, "log", " OUTPUT to %u: %w", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5312 = x5256 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5313 = x5312 + x5255;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:7)
args[1][42] = x5313;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5314 = x5258 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5315 = x5314 + x5257;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:7)
args[1][43] = x5315;
}
if (x5283 != 0) {
host_args.at(0) = x5297;
host_args.at(1) = x5255;
host_args.at(2) = x5256;
host_args.at(3) = x5257;
host_args.at(4) = x5258;
host(ctx, "log", " OUTPUT to %u: %w", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5316 = x5256 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5317 = x5316 + x5255;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:7)
args[1][44] = x5317;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5318 = x5258 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5319 = x5318 + x5257;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:7)
args[1][45] = x5319;
}
if (x5286 != 0) {
host_args.at(0) = x5297;
host_args.at(1) = x5255;
host_args.at(2) = x5256;
host_args.at(3) = x5257;
host_args.at(4) = x5258;
host(ctx, "log", " OUTPUT to %u: %w", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5320 = x5256 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5321 = x5320 + x5255;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:7)
args[1][46] = x5321;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5322 = x5258 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5323 = x5322 + x5257;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:7)
args[1][47] = x5323;
}
if (x5289 != 0) {
host_args.at(0) = x5297;
host_args.at(1) = x5255;
host_args.at(2) = x5256;
host_args.at(3) = x5257;
host_args.at(4) = x5258;
host(ctx, "log", " OUTPUT to %u: %w", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5324 = x5256 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5325 = x5324 + x5255;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:7)
args[1][48] = x5325;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5326 = x5258 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5327 = x5326 + x5257;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:7)
args[1][49] = x5327;
}
if (x5292 != 0) {
host_args.at(0) = x5297;
host_args.at(1) = x5255;
host_args.at(2) = x5256;
host_args.at(3) = x5257;
host_args.at(4) = x5258;
host(ctx, "log", " OUTPUT to %u: %w", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5328 = x5256 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5329 = x5328 + x5255;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:7)
args[1][50] = x5329;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5330 = x5258 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5331 = x5330 + x5257;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:7)
args[1][51] = x5331;
}
if (x5295 != 0) {
host_args.at(0) = x5297;
host_args.at(1) = x5255;
host_args.at(2) = x5256;
host_args.at(3) = x5257;
host_args.at(4) = x5258;
host(ctx, "log", " OUTPUT to %u: %w", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5332 = x5256 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:34)
auto x5333 = x5332 + x5255;
// loc("cirgen/circuit/rv32im/ecall.cpp":45:7)
args[1][52] = x5333;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5334 = x5258 * x97;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:38)
auto x5335 = x5334 + x5257;
// loc("cirgen/circuit/rv32im/ecall.cpp":46:7)
args[1][53] = x5335;
}
// loc("cirgen/circuit/rv32im/ecall.cpp":50:17)
auto x5336 = x603 + x85;
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x5337 = x5336 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5338 = Fp(x5337.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5338);
reg = x5338;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5339 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x5339 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5340 = x5337 - x5339;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5341 = x5340 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5342 = Fp(x5341.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5342);
reg = x5342;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5343 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x5343 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5344 = x5341 - x5343;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5345 = x5344 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5346 = Fp(x5345.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5346);
reg = x5346;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5347 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x5347 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5348 = x5345 - x5347;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5349 = x5348 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x5350 = Fp(x5349.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5350);
reg = x5350;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5351 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x5351 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x5352 = x5349 - x5351;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x5353 = x5352 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5353);
reg = x5353;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5354 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x5354 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x5355 = x102 - x5354;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x5356 = x5354 * x5355;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5356);
reg = x5356;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5357 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x5357 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x5358 = x99 - x5354;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x5359 = x5357 * x5358;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x5359 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("cirgen/circuit/rv32im/ecall.cpp":51:3)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
if (x5207 != 0) {
{
host_args.at(0) = x5193;
host_args.at(1) = x5194;
host_args.at(2) = x5195;
host_args.at(3) = x5196;
host(ctx, "log", " Doing syscall, selector = %w", host_args.data(), 4, host_outs.data(), 0);
host(ctx, "syscall", "", host_args.data(), 0, host_outs.data(), 8);
auto x5360 = host_outs.at(0);
auto x5361 = host_outs.at(1);
auto x5362 = host_outs.at(2);
auto x5363 = host_outs.at(3);
auto x5364 = host_outs.at(4);
auto x5365 = host_outs.at(5);
auto x5366 = host_outs.at(6);
auto x5367 = host_outs.at(7);
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5360);
reg = x5360;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5361);
reg = x5361;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5362);
reg = x5362;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5363);
reg = x5363;
}
{
host_args.at(0) = x34;
host_args.at(1) = x5360;
host_args.at(2) = x5361;
host_args.at(3) = x5362;
host_args.at(4) = x5363;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5368 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x5368 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5369 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x5369 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5370 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x5370 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5371 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x5371 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x34);
reg = x34;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5178);
reg = x5178;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5368);
reg = x5368;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5369);
reg = x5369;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5370);
reg = x5370;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5371);
reg = x5371;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5364);
reg = x5364;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5365);
reg = x5365;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5366);
reg = x5366;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5367);
reg = x5367;
}
{
host_args.at(0) = x33;
host_args.at(1) = x5364;
host_args.at(2) = x5365;
host_args.at(3) = x5366;
host_args.at(4) = x5367;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5372 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x5372 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5373 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x5373 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5374 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x5374 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5375 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x5375 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x33);
reg = x33;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5178);
reg = x5178;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5372);
reg = x5372;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5373);
reg = x5373;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5374);
reg = x5374;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5375);
reg = x5375;
}
host_args.at(0) = x5368;
host_args.at(1) = x5369;
host_args.at(2) = x5370;
host_args.at(3) = x5371;
host(ctx, "log", " A0 = %w", host_args.data(), 4, host_outs.data(), 0);
host_args.at(0) = x5372;
host_args.at(1) = x5373;
host_args.at(2) = x5374;
host_args.at(3) = x5375;
host(ctx, "log", " A1 = %w", host_args.data(), 4, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/Reg1"("cirgen/components/ram.cpp":141:10))
auto x5376 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x5376 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ecall.cpp":71:6)
auto x5377 = x5376 - x5178;
// loc("cirgen/circuit/rv32im/ecall.cpp":71:6)
if (x5377 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ecall.cpp:71");
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/Reg1"("cirgen/components/ram.cpp":141:10))
auto x5378 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x5378 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ecall.cpp":72:6)
auto x5379 = x5378 - x5178;
// loc("cirgen/circuit/rv32im/ecall.cpp":72:6)
if (x5379 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ecall.cpp:72");
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/Reg"("cirgen/components/ram.cpp":137:10))
auto x5380 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x5380 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ecall.cpp":73:6)
auto x5381 = x5380 - x34;
// loc("cirgen/circuit/rv32im/ecall.cpp":73:6)
if (x5381 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ecall.cpp:73");
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/Reg"("cirgen/components/ram.cpp":137:10))
auto x5382 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x5382 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ecall.cpp":74:6)
auto x5383 = x5382 - x33;
// loc("cirgen/circuit/rv32im/ecall.cpp":74:6)
if (x5383 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ecall.cpp:74");
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/Reg2"("cirgen/components/ram.cpp":145:10))
auto x5384 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x5384 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ecall.cpp":75:6)
auto x5385 = x5384 - x99;
// loc("cirgen/circuit/rv32im/ecall.cpp":75:6)
if (x5385 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ecall.cpp:75");
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/Reg2"("cirgen/components/ram.cpp":145:10))
auto x5386 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x5386 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ecall.cpp":76:6)
auto x5387 = x5386 - x99;
// loc("cirgen/circuit/rv32im/ecall.cpp":76:6)
if (x5387 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ecall.cpp:76");
// loc("cirgen/circuit/rv32im/ecall.cpp":78:17)
auto x5388 = x603 + x85;
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x5389 = x5388 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5390 = Fp(x5389.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5390);
reg = x5390;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5391 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x5391 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5392 = x5389 - x5391;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5393 = x5392 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5394 = Fp(x5393.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5394);
reg = x5394;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5395 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x5395 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5396 = x5393 - x5395;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5397 = x5396 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5398 = Fp(x5397.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5398);
reg = x5398;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5399 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x5399 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5400 = x5397 - x5399;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5401 = x5400 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x5402 = Fp(x5401.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5402);
reg = x5402;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5403 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x5403 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x5404 = x5401 - x5403;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x5405 = x5404 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5405);
reg = x5405;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5406 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x5406 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x5407 = x102 - x5406;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x5408 = x5406 * x5407;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5408);
reg = x5408;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5409 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x5409 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x5410 = x99 - x5406;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x5411 = x5409 * x5410;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x5411 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("cirgen/circuit/rv32im/ecall.cpp":79:3)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
if (x5210 != 0) {
{
host_args.at(0) = x34;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5412 = host_outs.at(0);
auto x5413 = host_outs.at(1);
auto x5414 = host_outs.at(2);
auto x5415 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5412);
reg = x5412;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5413);
reg = x5413;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5414);
reg = x5414;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5415);
reg = x5415;
}
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5416 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x5416 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5417 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x5417 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5418 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x5418 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5419 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x5419 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x34);
reg = x34;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5178);
reg = x5178;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5416);
reg = x5416;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5417);
reg = x5417;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5418);
reg = x5418;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5419);
reg = x5419;
}
{
host_args.at(0) = x33;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5420 = host_outs.at(0);
auto x5421 = host_outs.at(1);
auto x5422 = host_outs.at(2);
auto x5423 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5420);
reg = x5420;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5421);
reg = x5421;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5422);
reg = x5422;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5423);
reg = x5423;
}
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5424 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x5424 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5425 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x5425 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5426 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x5426 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5427 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x5427 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x33);
reg = x33;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5178);
reg = x5178;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5424);
reg = x5424;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5425);
reg = x5425;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5426);
reg = x5426;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5427);
reg = x5427;
}
{
host_args.at(0) = x32;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5428 = host_outs.at(0);
auto x5429 = host_outs.at(1);
auto x5430 = host_outs.at(2);
auto x5431 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5428);
reg = x5428;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5429);
reg = x5429;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5430);
reg = x5430;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5431);
reg = x5431;
}
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5432 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x5432 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5433 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x5433 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5434 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x5434 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5435 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x5435 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x32);
reg = x32;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5178);
reg = x5178;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5432);
reg = x5432;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5433);
reg = x5433;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5434);
reg = x5434;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5435);
reg = x5435;
}
// loc("cirgen/circuit/rv32im/ecall.cpp":92:17)
auto x5436 = x603 + x85;
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x5437 = x5436 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5438 = Fp(x5437.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5438);
reg = x5438;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5439 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x5439 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5440 = x5437 - x5439;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5441 = x5440 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5442 = Fp(x5441.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5442);
reg = x5442;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5443 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x5443 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5444 = x5441 - x5443;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5445 = x5444 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5446 = Fp(x5445.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5446);
reg = x5446;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5447 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x5447 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5448 = x5445 - x5447;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5449 = x5448 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x5450 = Fp(x5449.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5450);
reg = x5450;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5451 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x5451 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x5452 = x5449 - x5451;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x5453 = x5452 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5453);
reg = x5453;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5454 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x5454 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x5455 = x102 - x5454;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x5456 = x5454 * x5455;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5456);
reg = x5456;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5457 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x5457 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x5458 = x99 - x5454;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x5459 = x5457 * x5458;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x5459 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("cirgen/circuit/rv32im/ecall.cpp":93:3)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x76);
reg = x76;
}
}
if (x5213 != 0) {
// loc("cirgen/circuit/rv32im/ecall.cpp":102:3)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x603);
reg = x603;
}
{
host_args.at(0) = x34;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5460 = host_outs.at(0);
auto x5461 = host_outs.at(1);
auto x5462 = host_outs.at(2);
auto x5463 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5460);
reg = x5460;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5461);
reg = x5461;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5462);
reg = x5462;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5463);
reg = x5463;
}
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5464 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x5464 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5465 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x5465 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5466 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x5466 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5467 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x5467 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x34);
reg = x34;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5178);
reg = x5178;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5464);
reg = x5464;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5465);
reg = x5465;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5466);
reg = x5466;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5467);
reg = x5467;
}
{
host_args.at(0) = x33;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5468 = host_outs.at(0);
auto x5469 = host_outs.at(1);
auto x5470 = host_outs.at(2);
auto x5471 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5468);
reg = x5468;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5469);
reg = x5469;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5470);
reg = x5470;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5471);
reg = x5471;
}
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5472 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x5472 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5473 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x5473 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5474 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x5474 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5475 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x5475 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x33);
reg = x33;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5178);
reg = x5178;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5472);
reg = x5472;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5473);
reg = x5473;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5474);
reg = x5474;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5475);
reg = x5475;
}
// loc("./cirgen/components/u32.h":25:12)
auto x5476 = x5465 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x5477 = x5464 + x5476;
// loc("./cirgen/components/u32.h":26:12)
auto x5478 = x5466 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x5479 = x5477 + x5478;
// loc("./cirgen/components/u32.h":27:12)
auto x5480 = x5467 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x5481 = x5479 + x5480;
// loc("cirgen/circuit/rv32im/ecall.cpp":111:17)
auto x5482 = x5481 - x85;
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x5483 = x5482 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5484 = Fp(x5483.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5484);
reg = x5484;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5485 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x5485 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5486 = x5483 - x5485;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5487 = x5486 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5488 = Fp(x5487.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5488);
reg = x5488;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5489 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x5489 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5490 = x5487 - x5489;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5491 = x5490 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5492 = Fp(x5491.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5492);
reg = x5492;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5493 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x5493 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5494 = x5491 - x5493;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5495 = x5494 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x5496 = Fp(x5495.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5496);
reg = x5496;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5497 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x5497 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x5498 = x5495 - x5497;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x5499 = x5498 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5499);
reg = x5499;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5500 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x5500 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x5501 = x102 - x5500;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x5502 = x5500 * x5501;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5502);
reg = x5502;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5503 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x5503 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x5504 = x99 - x5500;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x5505 = x5503 * x5504;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x5505 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("cirgen/circuit/rv32im/ecall.cpp":112:3)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x73);
reg = x73;
}
}
}
// loc("Top/Mux/4/OneHot/Reg9"("./cirgen/components/mux.h":37:25))
auto x5506 = args[2][103 * steps + ((cycle - 0) & mask)];
assert(x5506 != Fp::invalid());
if (x5506 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5507 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x5507 != Fp::invalid());
// loc("Top/Mux/4/OneHot/Reg8"("cirgen/circuit/rv32im/sha.cpp":174:69))
auto x5508 = args[2][102 * steps + ((cycle - 1) & mask)];
assert(x5508 != Fp::invalid());
// loc("Top/Mux/4/OneHot/Reg13"("cirgen/circuit/rv32im/sha.cpp":175:77))
auto x5509 = args[2][107 * steps + ((cycle - 1) & mask)];
assert(x5509 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":176:35)
auto x5510 = x5508 + x5509;
if (x5510 != 0) {
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/sha.cpp":178:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x85);
reg = x85;
}
}
// loc("cirgen/circuit/rv32im/sha.cpp":180:39)
auto x5511 = x102 - x5508;
// loc("cirgen/circuit/rv32im/sha.cpp":180:39)
auto x5512 = x5511 - x5509;
if (x5512 != 0) {
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5513 = args[2][141 * steps + ((cycle - 1) & mask)];
assert(x5513 != Fp::invalid());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5513);
reg = x5513;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg4"("cirgen/circuit/rv32im/sha.cpp":183:40))
auto x5514 = args[2][135 * steps + ((cycle - 1) & mask)];
assert(x5514 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":183:40)
auto x5515 = x5514 - x102;
// loc("cirgen/circuit/rv32im/sha.cpp":183:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5515);
reg = x5515;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg4"("./cirgen/compiler/edsl/component.h":85:27))
auto x5516 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x5516 != Fp::invalid());
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x5517 = (x5516 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5517);
reg = x5517;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x5518 = inv(x5516);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5518);
reg = x5518;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5519 = args[2][136 * steps + ((cycle - 0) & mask)];
assert(x5519 != Fp::invalid());
if (x5519 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x5516 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x5520 = x102 - x5519;
if (x5520 != 0) {
// loc("Top/Mux/4/Mux/9/ShaCycle/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5521 = args[2][137 * steps + ((cycle - 0) & mask)];
assert(x5521 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x5522 = x5516 * x5521;
// loc("cirgen/components/iszero.cpp":15:26)
auto x5523 = x5522 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x5523 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
if (x5519 != 0) {
// loc("cirgen/circuit/rv32im/sha.cpp":187:29)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x75);
reg = x75;
}
}
if (x5520 != 0) {
// loc("./cirgen/components/onehot.h":44:19)
auto x5524 = x2132 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x5525 = x1347 + x5524;
// loc("./cirgen/components/onehot.h":44:19)
auto x5526 = x2836 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x5527 = x5525 + x5526;
// loc("./cirgen/components/onehot.h":44:19)
auto x5528 = x3593 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x5529 = x5527 + x5528;
// loc("./cirgen/components/onehot.h":44:19)
auto x5530 = x4035 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x5531 = x5529 + x5530;
// loc("./cirgen/components/onehot.h":44:19)
auto x5532 = x4400 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x5533 = x5531 + x5532;
// loc("./cirgen/components/onehot.h":44:19)
auto x5534 = x4832 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x5535 = x5533 + x5534;
// loc("./cirgen/components/onehot.h":44:19)
auto x5536 = x5177 * x77;
// loc("./cirgen/components/onehot.h":44:13)
auto x5537 = x5535 + x5536;
// loc("./cirgen/components/onehot.h":44:19)
auto x5538 = x5506 * x76;
// loc("./cirgen/components/onehot.h":44:13)
auto x5539 = x5537 + x5538;
// loc("Top/Mux/4/OneHot/Reg10"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5540 = args[2][104 * steps + ((cycle - 0) & mask)];
assert(x5540 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5541 = x5540 * x75;
// loc("./cirgen/components/onehot.h":44:13)
auto x5542 = x5539 + x5541;
// loc("Top/Mux/4/OneHot/Reg11"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5543 = args[2][105 * steps + ((cycle - 0) & mask)];
assert(x5543 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5544 = x5543 * x74;
// loc("./cirgen/components/onehot.h":44:13)
auto x5545 = x5542 + x5544;
// loc("Top/Mux/4/OneHot/Reg12"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5546 = args[2][106 * steps + ((cycle - 0) & mask)];
assert(x5546 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5547 = x5546 * x73;
// loc("./cirgen/components/onehot.h":44:13)
auto x5548 = x5545 + x5547;
// loc("Top/Mux/4/OneHot/Reg13"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5549 = args[2][107 * steps + ((cycle - 0) & mask)];
assert(x5549 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x5550 = x5549 * x72;
// loc("./cirgen/components/onehot.h":44:13)
auto x5551 = x5548 + x5550;
// loc("cirgen/circuit/rv32im/sha.cpp":188:33)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5551);
reg = x5551;
}
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x5552 = x603 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5553 = Fp(x5552.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5553);
reg = x5553;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5554 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x5554 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5555 = x5552 - x5554;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5556 = x5555 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5557 = Fp(x5556.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5557);
reg = x5557;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x5558 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x5558 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5559 = x5556 - x5558;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5560 = x5559 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x5561 = Fp(x5560.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5561);
reg = x5561;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x5562 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x5562 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x5563 = x5560 - x5562;
// loc("cirgen/components/bytes.cpp":83:10)
auto x5564 = x5563 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x5565 = Fp(x5564.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5565);
reg = x5565;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5566 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x5566 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x5567 = x5564 - x5566;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x5568 = x5567 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5568);
reg = x5568;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5569 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x5569 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x5570 = x102 - x5569;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x5571 = x5569 * x5570;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5571);
reg = x5571;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5572 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x5572 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x5573 = x99 - x5569;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x5574 = x5572 * x5573;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x5574 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5575 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x5575 != Fp::invalid());
host_args.at(0) = x76;
host_args.at(1) = x5575;
host_args.at(2) = x5516;
host(ctx, "log", "SHA_INIT: major = %u, minor = %u, count = %u", host_args.data(), 3, host_outs.data(), 0);
if (x5508 != 0) {
{
host_args.at(0) = x31;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5576 = host_outs.at(0);
auto x5577 = host_outs.at(1);
auto x5578 = host_outs.at(2);
auto x5579 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5576);
reg = x5576;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5577);
reg = x5577;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5578);
reg = x5578;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5579);
reg = x5579;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5580 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x5580 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5581 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x5581 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5582 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x5582 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5583 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x5583 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x31);
reg = x31;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5507);
reg = x5507;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5580);
reg = x5580;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5581);
reg = x5581;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5582);
reg = x5582;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5583);
reg = x5583;
}
{
host_args.at(0) = x30;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5584 = host_outs.at(0);
auto x5585 = host_outs.at(1);
auto x5586 = host_outs.at(2);
auto x5587 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5584);
reg = x5584;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5585);
reg = x5585;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5586);
reg = x5586;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5587);
reg = x5587;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5588 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x5588 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5589 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x5589 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5590 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x5590 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5591 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x5591 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x30);
reg = x30;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5507);
reg = x5507;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5588);
reg = x5588;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5589);
reg = x5589;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5590);
reg = x5590;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5591);
reg = x5591;
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5592 = args[2][125 * steps + ((cycle - 1) & mask)];
assert(x5592 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5593 = args[2][126 * steps + ((cycle - 1) & mask)];
assert(x5593 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5594 = args[2][127 * steps + ((cycle - 1) & mask)];
assert(x5594 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5595 = args[2][128 * steps + ((cycle - 1) & mask)];
assert(x5595 != Fp::invalid());
// loc("./cirgen/components/u32.h":25:12)
auto x5596 = x5593 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x5597 = x5592 + x5596;
// loc("./cirgen/components/u32.h":26:12)
auto x5598 = x5594 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x5599 = x5597 + x5598;
// loc("./cirgen/components/u32.h":27:12)
auto x5600 = x5595 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x5601 = x5599 + x5600;
// loc("cirgen/circuit/rv32im/sha.cpp":197:58)
auto x5602 = x5601 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":197:5)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5602);
reg = x5602;
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5603 = args[2][132 * steps + ((cycle - 1) & mask)];
assert(x5603 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5604 = args[2][133 * steps + ((cycle - 1) & mask)];
assert(x5604 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5605 = args[2][134 * steps + ((cycle - 1) & mask)];
assert(x5605 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5606 = args[2][135 * steps + ((cycle - 1) & mask)];
assert(x5606 != Fp::invalid());
// loc("./cirgen/components/u32.h":25:12)
auto x5607 = x5604 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x5608 = x5603 + x5607;
// loc("./cirgen/components/u32.h":26:12)
auto x5609 = x5605 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x5610 = x5608 + x5609;
// loc("./cirgen/components/u32.h":27:12)
auto x5611 = x5606 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x5612 = x5610 + x5611;
// loc("cirgen/circuit/rv32im/sha.cpp":198:57)
auto x5613 = x5612 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":198:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5613);
reg = x5613;
}
// loc("./cirgen/components/u32.h":25:12)
auto x5614 = x5581 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x5615 = x5580 + x5614;
// loc("./cirgen/components/u32.h":26:12)
auto x5616 = x5582 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x5617 = x5615 + x5616;
// loc("./cirgen/components/u32.h":27:12)
auto x5618 = x5583 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x5619 = x5617 + x5618;
// loc("cirgen/circuit/rv32im/sha.cpp":199:16)
auto x5620 = x5619 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":199:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5620);
reg = x5620;
}
// loc("./cirgen/components/u32.h":25:12)
auto x5621 = x5589 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x5622 = x5588 + x5621;
// loc("./cirgen/components/u32.h":26:12)
auto x5623 = x5590 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x5624 = x5622 + x5623;
// loc("./cirgen/components/u32.h":27:12)
auto x5625 = x5591 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x5626 = x5624 + x5625;
// loc("cirgen/circuit/rv32im/sha.cpp":200:16)
auto x5627 = x5626 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":200:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5627);
reg = x5627;
}
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5628 = args[2][139 * steps + ((cycle - 1) & mask)];
assert(x5628 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5629 = args[2][140 * steps + ((cycle - 1) & mask)];
assert(x5629 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5630 = args[2][141 * steps + ((cycle - 1) & mask)];
assert(x5630 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5631 = args[2][142 * steps + ((cycle - 1) & mask)];
assert(x5631 != Fp::invalid());
// loc("./cirgen/components/u32.h":25:12)
auto x5632 = x5629 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x5633 = x5628 + x5632;
// loc("./cirgen/components/u32.h":26:12)
auto x5634 = x5630 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x5635 = x5633 + x5634;
// loc("./cirgen/components/u32.h":27:12)
auto x5636 = x5631 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x5637 = x5635 + x5636;
// loc("cirgen/circuit/rv32im/sha.cpp":201:5)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5637);
reg = x5637;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][143 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5638 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x5638 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":204:10)
auto x5639 = x5638 * x85;
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5640 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x5640 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":205:10)
auto x5641 = x5640 * x85;
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5642 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x5642 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":206:10)
auto x5643 = x5642 * x85;
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5644 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x5644 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":207:10)
auto x5645 = x5644 * x85;
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x5646 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x5646 != Fp::invalid());
host_args.at(0) = x5639;
host_args.at(1) = x5641;
host_args.at(2) = x5643;
host_args.at(3) = x5645;
host_args.at(4) = x5646;
host(ctx, "log", " FromEcall: stateOut = 0x%x, stateIn = 0x%x, data0 = 0x%x, data1 = 0x%x, repeat: %u", host_args.data(), 5, host_outs.data(), 0);
}
if (x5509 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("Top/Mux/4/Mux/13/Reg1"("cirgen/circuit/rv32im/sha.cpp":214:53))
auto x5647 = args[2][109 * steps + ((cycle - 1) & mask)];
assert(x5647 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":214:5)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5647);
reg = x5647;
}
// loc("Top/Mux/4/Mux/13/Reg2"("cirgen/circuit/rv32im/sha.cpp":215:51))
auto x5648 = args[2][110 * steps + ((cycle - 1) & mask)];
assert(x5648 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":215:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5648);
reg = x5648;
}
// loc("Top/Mux/4/Mux/13/Reg3"("cirgen/circuit/rv32im/sha.cpp":216:83))
auto x5649 = args[2][111 * steps + ((cycle - 1) & mask)];
assert(x5649 != Fp::invalid());
// loc("cirgen/circuit/rv32im/page_fault.cpp":54:12)
auto x5650 = x5649 * x29;
// loc("cirgen/circuit/rv32im/page_fault.cpp":54:12)
auto x5651 = x5650 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":216:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5651);
reg = x5651;
}
// loc("cirgen/circuit/rv32im/sha.cpp":217:83)
auto x5652 = x5651 + x77;
// loc("cirgen/circuit/rv32im/sha.cpp":217:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5652);
reg = x5652;
}
// loc("Top/Mux/4/Mux/13/Reg4"("cirgen/circuit/rv32im/sha.cpp":218:49))
auto x5653 = args[2][113 * steps + ((cycle - 1) & mask)];
assert(x5653 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":218:5)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5653);
reg = x5653;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][143 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5654 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x5654 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":221:10)
auto x5655 = x5654 * x85;
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5656 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x5656 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":222:10)
auto x5657 = x5656 * x85;
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5658 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x5658 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":223:10)
auto x5659 = x5658 * x85;
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5660 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x5660 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":224:10)
auto x5661 = x5660 * x85;
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x5662 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x5662 != Fp::invalid());
host_args.at(0) = x5655;
host_args.at(1) = x5657;
host_args.at(2) = x5659;
host_args.at(3) = x5661;
host_args.at(4) = x5662;
host(ctx, "log", " FromPageFault: stateOut = 0x%x, stateIn = 0x%x, data0 = 0x%x, data1 = 0x%x, repeat: %u", host_args.data(), 5, host_outs.data(), 0);
}
if (x5512 != 0) {
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg"("cirgen/circuit/rv32im/sha.cpp":228:42))
auto x5663 = args[2][131 * steps + ((cycle - 1) & mask)];
assert(x5663 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":228:5)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5663);
reg = x5663;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg1"("cirgen/circuit/rv32im/sha.cpp":229:40))
auto x5664 = args[2][132 * steps + ((cycle - 1) & mask)];
assert(x5664 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":229:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5664);
reg = x5664;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg2"("cirgen/circuit/rv32im/sha.cpp":230:36))
auto x5665 = args[2][133 * steps + ((cycle - 1) & mask)];
assert(x5665 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":230:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5665);
reg = x5665;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg3"("cirgen/circuit/rv32im/sha.cpp":231:36))
auto x5666 = args[2][134 * steps + ((cycle - 1) & mask)];
assert(x5666 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":231:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5666);
reg = x5666;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg5"("cirgen/circuit/rv32im/sha.cpp":232:38))
auto x5667 = args[2][138 * steps + ((cycle - 1) & mask)];
assert(x5667 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":232:5)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5667);
reg = x5667;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5668 = args[2][143 * steps + ((cycle - 1) & mask)];
assert(x5668 != Fp::invalid());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][143 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5668);
reg = x5668;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5669 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x5669 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":236:24)
auto x5670 = x5669 + x5516;
{
host_args.at(0) = x5670;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5671 = host_outs.at(0);
auto x5672 = host_outs.at(1);
auto x5673 = host_outs.at(2);
auto x5674 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5671);
reg = x5671;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5672);
reg = x5672;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5673);
reg = x5673;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5674);
reg = x5674;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5675 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x5675 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5676 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x5676 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5677 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x5677 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5678 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x5678 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5670);
reg = x5670;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5507);
reg = x5507;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5675);
reg = x5675;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5676);
reg = x5676;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5677);
reg = x5677;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5678);
reg = x5678;
}
// loc("cirgen/circuit/rv32im/sha.cpp":237:24)
auto x5679 = x5670 + x85;
{
host_args.at(0) = x5679;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x5680 = host_outs.at(0);
auto x5681 = host_outs.at(1);
auto x5682 = host_outs.at(2);
auto x5683 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5680);
reg = x5680;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5681);
reg = x5681;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5682);
reg = x5682;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5683);
reg = x5683;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5684 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x5684 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5685 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x5685 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5686 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x5686 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5687 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x5687 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5679);
reg = x5679;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5507);
reg = x5507;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5684);
reg = x5684;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5685);
reg = x5685;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5686);
reg = x5686;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5687);
reg = x5687;
}
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x5688 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x5688 != Fp::invalid());
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x5689 = (x5688 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5689);
reg = x5689;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x5690 = inv(x5688);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5690);
reg = x5690;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/IsZero1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5691 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x5691 != Fp::invalid());
if (x5691 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x5688 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x5692 = x102 - x5691;
if (x5692 != 0) {
// loc("Top/Mux/4/Mux/9/ShaCycle/IsZero1/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x5693 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x5693 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x5694 = x5688 * x5693;
// loc("cirgen/components/iszero.cpp":15:26)
auto x5695 = x5694 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x5695 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
{
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][19 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][20 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][21 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][22 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][23 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][24 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5696 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x5696 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5697 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x5697 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5698 = x5697 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5699 = x5696 + x5698;
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5700 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x5700 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5701 = x5700 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5702 = x5699 + x5701;
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5703 = args[2][85 * steps + ((cycle - 0) & mask)];
assert(x5703 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5704 = x5703 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5705 = x5702 + x5704;
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5706 = args[2][86 * steps + ((cycle - 0) & mask)];
assert(x5706 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5707 = x5706 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5708 = x5705 + x5707;
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5709 = args[2][87 * steps + ((cycle - 0) & mask)];
assert(x5709 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5710 = x5709 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5711 = x5708 + x5710;
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5712 = args[2][88 * steps + ((cycle - 0) & mask)];
assert(x5712 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5713 = x5712 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5714 = x5711 + x5713;
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5715 = args[2][89 * steps + ((cycle - 0) & mask)];
assert(x5715 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5716 = x5715 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5717 = x5714 + x5716;
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5718 = args[2][90 * steps + ((cycle - 0) & mask)];
assert(x5718 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5719 = x5718 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5720 = x5717 + x5719;
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5721 = args[2][91 * steps + ((cycle - 0) & mask)];
assert(x5721 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5722 = x5721 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5723 = x5720 + x5722;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5724 = args[2][19 * steps + ((cycle - 0) & mask)];
assert(x5724 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5725 = x5724 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5726 = x5723 + x5725;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5727 = args[2][20 * steps + ((cycle - 0) & mask)];
assert(x5727 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5728 = x5727 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5729 = x5726 + x5728;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5730 = args[2][21 * steps + ((cycle - 0) & mask)];
assert(x5730 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5731 = x5730 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5732 = x5729 + x5731;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5733 = args[2][22 * steps + ((cycle - 0) & mask)];
assert(x5733 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5734 = x5733 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5735 = x5732 + x5734;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5736 = args[2][23 * steps + ((cycle - 0) & mask)];
assert(x5736 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5737 = x5736 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5738 = x5735 + x5737;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5739 = args[2][24 * steps + ((cycle - 0) & mask)];
assert(x5739 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5740 = x5739 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5741 = x5738 + x5740;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x5742 = x101 - x5741;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x5743 = x5742 * x16;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5743);
reg = x5743;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5744 = args[2][80 * steps + ((cycle - 0) & mask)];
assert(x5744 != Fp::invalid());
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5745 = Fp(x5744.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5745);
reg = x5745;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5746 = Fp(x5744.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5747 = x5746 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5747);
reg = x5747;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5748 = Fp(x5744.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5749 = x5748 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5749);
reg = x5749;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5750 = Fp(x5744.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5751 = x5750 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5751);
reg = x5751;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5752 = Fp(x5744.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5753 = x5752 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5753);
reg = x5753;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5754 = Fp(x5744.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5755 = x5754 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5755);
reg = x5755;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5756 = Fp(x5744.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5757 = x5756 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5757);
reg = x5757;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5758 = Fp(x5744.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5759 = x5758 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5759);
reg = x5759;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5760 = Fp(x5744.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5761 = x5760 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5761);
reg = x5761;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5762 = Fp(x5744.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5763 = x5762 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5763);
reg = x5763;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5764 = Fp(x5744.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5765 = x5764 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5765);
reg = x5765;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5766 = Fp(x5744.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5767 = x5766 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5767);
reg = x5767;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5768 = Fp(x5744.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5769 = x5768 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5769);
reg = x5769;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5770 = Fp(x5744.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5771 = x5770 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5771);
reg = x5771;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5772 = Fp(x5744.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5773 = x5772 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5773);
reg = x5773;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5774 = Fp(x5744.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5775 = x5774 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5775);
reg = x5775;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5776 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x5776 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5777 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x5777 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5778 = x5777 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5779 = x5776 + x5778;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5780 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x5780 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5781 = x5780 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5782 = x5779 + x5781;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5783 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x5783 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5784 = x5783 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5785 = x5782 + x5784;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5786 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x5786 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5787 = x5786 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5788 = x5785 + x5787;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5789 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x5789 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5790 = x5789 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5791 = x5788 + x5790;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5792 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x5792 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5793 = x5792 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5794 = x5791 + x5793;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5795 = args[2][32 * steps + ((cycle - 0) & mask)];
assert(x5795 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5796 = x5795 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5797 = x5794 + x5796;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5798 = args[2][33 * steps + ((cycle - 0) & mask)];
assert(x5798 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5799 = x5798 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5800 = x5797 + x5799;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5801 = args[2][34 * steps + ((cycle - 0) & mask)];
assert(x5801 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5802 = x5801 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5803 = x5800 + x5802;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5804 = args[2][35 * steps + ((cycle - 0) & mask)];
assert(x5804 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5805 = x5804 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5806 = x5803 + x5805;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5807 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x5807 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5808 = x5807 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5809 = x5806 + x5808;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5810 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x5810 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5811 = x5810 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5812 = x5809 + x5811;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5813 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x5813 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5814 = x5813 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5815 = x5812 + x5814;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5816 = args[2][39 * steps + ((cycle - 0) & mask)];
assert(x5816 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5817 = x5816 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5818 = x5815 + x5817;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5819 = args[2][40 * steps + ((cycle - 0) & mask)];
assert(x5819 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5820 = x5819 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5821 = x5818 + x5820;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x5822 = x5744 - x5821;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x5823 = x5822 * x16;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5823);
reg = x5823;
}
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5824 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x5824 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x5825 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x5825 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x5826 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x5826 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x5827 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x5827 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":136:26)
auto x5828 = x5826 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":136:11)
auto x5829 = x5827 + x5828;
// loc("cirgen/circuit/rv32im/sha.cpp":136:61)
auto x5830 = x5824 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":136:46)
auto x5831 = x5825 + x5830;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5832 = Fp(x5829.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][150 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5832);
reg = x5832;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5833 = Fp(x5829.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5834 = x5833 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][151 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5834);
reg = x5834;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5835 = Fp(x5829.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5836 = x5835 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][152 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5836);
reg = x5836;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5837 = Fp(x5829.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5838 = x5837 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][153 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5838);
reg = x5838;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5839 = Fp(x5829.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5840 = x5839 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][154 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5840);
reg = x5840;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5841 = Fp(x5829.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5842 = x5841 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][155 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5842);
reg = x5842;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5843 = Fp(x5829.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5844 = x5843 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][156 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5844);
reg = x5844;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5845 = Fp(x5829.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5846 = x5845 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][157 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5846);
reg = x5846;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5847 = Fp(x5829.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5848 = x5847 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][158 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5848);
reg = x5848;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5849 = Fp(x5829.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5850 = x5849 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][159 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5850);
reg = x5850;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5851 = Fp(x5829.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5852 = x5851 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][160 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5852);
reg = x5852;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5853 = Fp(x5829.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5854 = x5853 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5854);
reg = x5854;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5855 = Fp(x5829.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5856 = x5855 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5856);
reg = x5856;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5857 = Fp(x5829.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5858 = x5857 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5858);
reg = x5858;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5859 = Fp(x5829.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5860 = x5859 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5860);
reg = x5860;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5861 = Fp(x5829.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5862 = x5861 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5862);
reg = x5862;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5863 = args[2][150 * steps + ((cycle - 0) & mask)];
assert(x5863 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5864 = args[2][151 * steps + ((cycle - 0) & mask)];
assert(x5864 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5865 = x5864 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5866 = x5863 + x5865;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5867 = args[2][152 * steps + ((cycle - 0) & mask)];
assert(x5867 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5868 = x5867 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5869 = x5866 + x5868;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5870 = args[2][153 * steps + ((cycle - 0) & mask)];
assert(x5870 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5871 = x5870 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5872 = x5869 + x5871;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5873 = args[2][154 * steps + ((cycle - 0) & mask)];
assert(x5873 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5874 = x5873 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5875 = x5872 + x5874;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5876 = args[2][155 * steps + ((cycle - 0) & mask)];
assert(x5876 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5877 = x5876 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5878 = x5875 + x5877;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5879 = args[2][156 * steps + ((cycle - 0) & mask)];
assert(x5879 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5880 = x5879 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5881 = x5878 + x5880;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5882 = args[2][157 * steps + ((cycle - 0) & mask)];
assert(x5882 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5883 = x5882 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5884 = x5881 + x5883;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5885 = args[2][158 * steps + ((cycle - 0) & mask)];
assert(x5885 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5886 = x5885 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5887 = x5884 + x5886;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5888 = args[2][159 * steps + ((cycle - 0) & mask)];
assert(x5888 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5889 = x5888 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5890 = x5887 + x5889;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5891 = args[2][160 * steps + ((cycle - 0) & mask)];
assert(x5891 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5892 = x5891 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5893 = x5890 + x5892;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5894 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x5894 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5895 = x5894 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5896 = x5893 + x5895;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5897 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x5897 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5898 = x5897 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5899 = x5896 + x5898;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5900 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x5900 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5901 = x5900 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5902 = x5899 + x5901;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5903 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x5903 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5904 = x5903 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5905 = x5902 + x5904;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5906 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x5906 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5907 = x5906 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5908 = x5905 + x5907;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x5909 = x5829 - x5908;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x5910 = x5909 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":122:26)
auto x5911 = Fp(x5910.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][76 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5911);
reg = x5911;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5912 = args[2][76 * steps + ((cycle - 0) & mask)];
assert(x5912 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":123:20)
auto x5913 = x5910 - x5912;
// loc("cirgen/circuit/rv32im/sha.cpp":123:19)
auto x5914 = x5913 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":124:20)
auto x5915 = x102 - x5914;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
auto x5916 = x5914 * x5915;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
if (x5916 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:124");
// loc("cirgen/circuit/rv32im/sha.cpp":125:32)
auto x5917 = x5831 + x5910;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5918 = Fp(x5917.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5918);
reg = x5918;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5919 = Fp(x5917.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5920 = x5919 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5920);
reg = x5920;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5921 = Fp(x5917.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5922 = x5921 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5922);
reg = x5922;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5923 = Fp(x5917.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5924 = x5923 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][169 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5924);
reg = x5924;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5925 = Fp(x5917.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5926 = x5925 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][170 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5926);
reg = x5926;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5927 = Fp(x5917.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5928 = x5927 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][171 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5928);
reg = x5928;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5929 = Fp(x5917.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5930 = x5929 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][172 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5930);
reg = x5930;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5931 = Fp(x5917.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5932 = x5931 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5932);
reg = x5932;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5933 = Fp(x5917.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5934 = x5933 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][174 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5934);
reg = x5934;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5935 = Fp(x5917.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5936 = x5935 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][175 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5936);
reg = x5936;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5937 = Fp(x5917.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5938 = x5937 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5938);
reg = x5938;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5939 = Fp(x5917.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5940 = x5939 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5940);
reg = x5940;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5941 = Fp(x5917.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5942 = x5941 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5942);
reg = x5942;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5943 = Fp(x5917.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5944 = x5943 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5944);
reg = x5944;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5945 = Fp(x5917.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5946 = x5945 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5946);
reg = x5946;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x5947 = Fp(x5917.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x5948 = x5947 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5948);
reg = x5948;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5949 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x5949 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5950 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x5950 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5951 = x5950 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5952 = x5949 + x5951;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5953 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x5953 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5954 = x5953 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5955 = x5952 + x5954;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5956 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x5956 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5957 = x5956 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5958 = x5955 + x5957;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5959 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x5959 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5960 = x5959 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5961 = x5958 + x5960;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5962 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x5962 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5963 = x5962 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5964 = x5961 + x5963;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5965 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x5965 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5966 = x5965 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5967 = x5964 + x5966;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5968 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x5968 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5969 = x5968 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5970 = x5967 + x5969;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5971 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x5971 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5972 = x5971 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5973 = x5970 + x5972;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5974 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x5974 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5975 = x5974 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5976 = x5973 + x5975;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5977 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x5977 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5978 = x5977 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5979 = x5976 + x5978;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5980 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x5980 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5981 = x5980 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5982 = x5979 + x5981;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5983 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x5983 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5984 = x5983 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5985 = x5982 + x5984;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5986 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x5986 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5987 = x5986 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5988 = x5985 + x5987;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5989 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x5989 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5990 = x5989 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5991 = x5988 + x5990;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5992 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x5992 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x5993 = x5992 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x5994 = x5991 + x5993;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x5995 = x5917 - x5994;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x5996 = x5995 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":126:27)
auto x5997 = Fp(x5996.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][77 * steps + cycle];
assert(reg == Fp::invalid() || reg == x5997);
reg = x5997;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x5998 = args[2][77 * steps + ((cycle - 0) & mask)];
assert(x5998 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":127:21)
auto x5999 = x5996 - x5998;
// loc("cirgen/circuit/rv32im/sha.cpp":127:20)
auto x6000 = x5999 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":128:21)
auto x6001 = x102 - x6000;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
auto x6002 = x6000 * x6001;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
if (x6002 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:128");
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6003 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x6003 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6004 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x6004 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x6005 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x6005 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x6006 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x6006 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":136:26)
auto x6007 = x6005 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":136:11)
auto x6008 = x6006 + x6007;
// loc("cirgen/circuit/rv32im/sha.cpp":136:61)
auto x6009 = x6003 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":136:46)
auto x6010 = x6004 + x6009;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6011 = Fp(x6008.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6011);
reg = x6011;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6012 = Fp(x6008.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6013 = x6012 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6013);
reg = x6013;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6014 = Fp(x6008.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6015 = x6014 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6015);
reg = x6015;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6016 = Fp(x6008.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6017 = x6016 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6017);
reg = x6017;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6018 = Fp(x6008.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6019 = x6018 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6019);
reg = x6019;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6020 = Fp(x6008.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6021 = x6020 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6021);
reg = x6021;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6022 = Fp(x6008.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6023 = x6022 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6023);
reg = x6023;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6024 = Fp(x6008.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6025 = x6024 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6025);
reg = x6025;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6026 = Fp(x6008.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6027 = x6026 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][190 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6027);
reg = x6027;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6028 = Fp(x6008.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6029 = x6028 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][191 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6029);
reg = x6029;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6030 = Fp(x6008.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6031 = x6030 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][192 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6031);
reg = x6031;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6032 = Fp(x6008.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6033 = x6032 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][193 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6033);
reg = x6033;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6034 = Fp(x6008.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6035 = x6034 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][194 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6035);
reg = x6035;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6036 = Fp(x6008.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6037 = x6036 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][195 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6037);
reg = x6037;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6038 = Fp(x6008.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6039 = x6038 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][196 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6039);
reg = x6039;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6040 = Fp(x6008.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6041 = x6040 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][197 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6041);
reg = x6041;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6042 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x6042 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6043 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x6043 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6044 = x6043 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6045 = x6042 + x6044;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6046 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x6046 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6047 = x6046 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6048 = x6045 + x6047;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6049 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x6049 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6050 = x6049 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6051 = x6048 + x6050;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6052 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x6052 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6053 = x6052 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6054 = x6051 + x6053;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6055 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x6055 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6056 = x6055 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6057 = x6054 + x6056;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6058 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x6058 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6059 = x6058 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6060 = x6057 + x6059;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6061 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x6061 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6062 = x6061 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6063 = x6060 + x6062;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6064 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x6064 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6065 = x6064 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6066 = x6063 + x6065;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6067 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x6067 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6068 = x6067 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6069 = x6066 + x6068;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6070 = args[2][192 * steps + ((cycle - 0) & mask)];
assert(x6070 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6071 = x6070 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6072 = x6069 + x6071;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6073 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x6073 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6074 = x6073 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6075 = x6072 + x6074;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6076 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x6076 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6077 = x6076 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6078 = x6075 + x6077;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6079 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x6079 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6080 = x6079 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6081 = x6078 + x6080;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6082 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x6082 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6083 = x6082 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6084 = x6081 + x6083;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6085 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x6085 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6086 = x6085 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6087 = x6084 + x6086;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x6088 = x6008 - x6087;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x6089 = x6088 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":122:26)
auto x6090 = Fp(x6089.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][78 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6090);
reg = x6090;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6091 = args[2][78 * steps + ((cycle - 0) & mask)];
assert(x6091 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":123:20)
auto x6092 = x6089 - x6091;
// loc("cirgen/circuit/rv32im/sha.cpp":123:19)
auto x6093 = x6092 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":124:20)
auto x6094 = x102 - x6093;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
auto x6095 = x6093 * x6094;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
if (x6095 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:124");
// loc("cirgen/circuit/rv32im/sha.cpp":125:32)
auto x6096 = x6010 + x6089;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6097 = Fp(x6096.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][198 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6097);
reg = x6097;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6098 = Fp(x6096.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6099 = x6098 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][199 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6099);
reg = x6099;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6100 = Fp(x6096.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6101 = x6100 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][200 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6101);
reg = x6101;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6102 = Fp(x6096.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6103 = x6102 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][201 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6103);
reg = x6103;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6104 = Fp(x6096.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6105 = x6104 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][202 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6105);
reg = x6105;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6106 = Fp(x6096.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6107 = x6106 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][203 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6107);
reg = x6107;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6108 = Fp(x6096.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6109 = x6108 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6109);
reg = x6109;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6110 = Fp(x6096.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6111 = x6110 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6111);
reg = x6111;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6112 = Fp(x6096.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6113 = x6112 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6113);
reg = x6113;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6114 = Fp(x6096.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6115 = x6114 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6115);
reg = x6115;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6116 = Fp(x6096.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6117 = x6116 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][208 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6117);
reg = x6117;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6118 = Fp(x6096.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6119 = x6118 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][209 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6119);
reg = x6119;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6120 = Fp(x6096.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6121 = x6120 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][210 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6121);
reg = x6121;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6122 = Fp(x6096.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6123 = x6122 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][211 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6123);
reg = x6123;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6124 = Fp(x6096.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6125 = x6124 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][212 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6125);
reg = x6125;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6126 = Fp(x6096.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6127 = x6126 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][213 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6127);
reg = x6127;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6128 = args[2][198 * steps + ((cycle - 0) & mask)];
assert(x6128 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6129 = args[2][199 * steps + ((cycle - 0) & mask)];
assert(x6129 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6130 = x6129 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6131 = x6128 + x6130;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6132 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x6132 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6133 = x6132 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6134 = x6131 + x6133;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6135 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x6135 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6136 = x6135 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6137 = x6134 + x6136;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6138 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x6138 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6139 = x6138 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6140 = x6137 + x6139;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6141 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x6141 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6142 = x6141 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6143 = x6140 + x6142;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6144 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x6144 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6145 = x6144 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6146 = x6143 + x6145;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6147 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x6147 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6148 = x6147 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6149 = x6146 + x6148;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6150 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x6150 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6151 = x6150 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6152 = x6149 + x6151;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6153 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x6153 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6154 = x6153 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6155 = x6152 + x6154;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6156 = args[2][208 * steps + ((cycle - 0) & mask)];
assert(x6156 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6157 = x6156 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6158 = x6155 + x6157;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6159 = args[2][209 * steps + ((cycle - 0) & mask)];
assert(x6159 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6160 = x6159 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6161 = x6158 + x6160;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6162 = args[2][210 * steps + ((cycle - 0) & mask)];
assert(x6162 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6163 = x6162 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6164 = x6161 + x6163;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6165 = args[2][211 * steps + ((cycle - 0) & mask)];
assert(x6165 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6166 = x6165 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6167 = x6164 + x6166;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6168 = args[2][212 * steps + ((cycle - 0) & mask)];
assert(x6168 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6169 = x6168 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6170 = x6167 + x6169;
// loc("Top/Mux/4/Mux/9/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6171 = args[2][213 * steps + ((cycle - 0) & mask)];
assert(x6171 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6172 = x6171 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6173 = x6170 + x6172;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x6174 = x6096 - x6173;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x6175 = x6174 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":126:27)
auto x6176 = Fp(x6175.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6176);
reg = x6176;
}
}
// loc("Top/Mux/4/Mux/9/ShaCycle/Twit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6177 = args[2][79 * steps + ((cycle - 0) & mask)];
assert(x6177 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":127:21)
auto x6178 = x6175 - x6177;
// loc("cirgen/circuit/rv32im/sha.cpp":127:20)
auto x6179 = x6178 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":128:21)
auto x6180 = x102 - x6179;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
auto x6181 = x6179 * x6180;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
if (x6181 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:128");
}
// loc("Top/Mux/4/OneHot/Reg10"("./cirgen/components/mux.h":37:25))
auto x6182 = args[2][104 * steps + ((cycle - 0) & mask)];
assert(x6182 != Fp::invalid());
if (x6182 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6183 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x6183 != Fp::invalid());
// loc("Top/Mux/4/OneHot/Reg9"("cirgen/circuit/rv32im/sha.cpp":259:70))
auto x6184 = args[2][103 * steps + ((cycle - 1) & mask)];
assert(x6184 != Fp::invalid());
// loc("Top/Mux/4/OneHot/Reg11"("cirgen/circuit/rv32im/sha.cpp":260:70))
auto x6185 = args[2][105 * steps + ((cycle - 1) & mask)];
assert(x6185 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":261:29)
auto x6186 = x6184 + x6185;
if (x6186 != 0) {
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/sha.cpp":263:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x78);
reg = x78;
}
}
// loc("cirgen/circuit/rv32im/sha.cpp":265:33)
auto x6187 = x102 - x6184;
// loc("cirgen/circuit/rv32im/sha.cpp":265:33)
auto x6188 = x6187 - x6185;
if (x6188 != 0) {
// loc("Top/Mux/4/Mux/10/ShaCycle/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6189 = args[2][136 * steps + ((cycle - 1) & mask)];
assert(x6189 != Fp::invalid());
if (x6189 != 0) {
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/sha.cpp":269:7)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x78);
reg = x78;
}
}
// loc("cirgen/circuit/rv32im/sha.cpp":271:20)
auto x6190 = x102 - x6189;
if (x6190 != 0) {
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6191 = args[2][141 * steps + ((cycle - 1) & mask)];
assert(x6191 != Fp::invalid());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6191);
reg = x6191;
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg4"("cirgen/circuit/rv32im/sha.cpp":274:42))
auto x6192 = args[2][135 * steps + ((cycle - 1) & mask)];
assert(x6192 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":274:42)
auto x6193 = x6192 - x102;
// loc("cirgen/circuit/rv32im/sha.cpp":274:7)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6193);
reg = x6193;
}
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg4"("./cirgen/compiler/edsl/component.h":85:27))
auto x6194 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x6194 != Fp::invalid());
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x6195 = (x6194 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6195);
reg = x6195;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x6196 = inv(x6194);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6196);
reg = x6196;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6197 = args[2][136 * steps + ((cycle - 0) & mask)];
assert(x6197 != Fp::invalid());
if (x6197 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x6194 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x6198 = x102 - x6197;
if (x6198 != 0) {
// loc("Top/Mux/4/Mux/10/ShaCycle/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x6199 = args[2][137 * steps + ((cycle - 0) & mask)];
assert(x6199 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x6200 = x6194 * x6199;
// loc("cirgen/components/iszero.cpp":15:26)
auto x6201 = x6200 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x6201 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
if (x6197 != 0) {
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6202 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x6202 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":281:17)
auto x6203 = x102 - x6202;
if (x6203 != 0) {
// loc("cirgen/circuit/rv32im/sha.cpp":281:21)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x75);
reg = x75;
}
}
if (x6202 != 0) {
// loc("cirgen/circuit/rv32im/sha.cpp":282:17)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x74);
reg = x74;
}
}
}
if (x6198 != 0) {
// loc("./cirgen/components/onehot.h":44:19)
auto x6204 = x2132 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x6205 = x1347 + x6204;
// loc("./cirgen/components/onehot.h":44:19)
auto x6206 = x2836 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x6207 = x6205 + x6206;
// loc("./cirgen/components/onehot.h":44:19)
auto x6208 = x3593 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x6209 = x6207 + x6208;
// loc("./cirgen/components/onehot.h":44:19)
auto x6210 = x4035 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x6211 = x6209 + x6210;
// loc("./cirgen/components/onehot.h":44:19)
auto x6212 = x4400 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x6213 = x6211 + x6212;
// loc("./cirgen/components/onehot.h":44:19)
auto x6214 = x4832 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x6215 = x6213 + x6214;
// loc("./cirgen/components/onehot.h":44:19)
auto x6216 = x5177 * x77;
// loc("./cirgen/components/onehot.h":44:13)
auto x6217 = x6215 + x6216;
// loc("./cirgen/components/onehot.h":44:19)
auto x6218 = x5506 * x76;
// loc("./cirgen/components/onehot.h":44:13)
auto x6219 = x6217 + x6218;
// loc("./cirgen/components/onehot.h":44:19)
auto x6220 = x6182 * x75;
// loc("./cirgen/components/onehot.h":44:13)
auto x6221 = x6219 + x6220;
// loc("Top/Mux/4/OneHot/Reg11"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x6222 = args[2][105 * steps + ((cycle - 0) & mask)];
assert(x6222 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x6223 = x6222 * x74;
// loc("./cirgen/components/onehot.h":44:13)
auto x6224 = x6221 + x6223;
// loc("Top/Mux/4/OneHot/Reg12"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x6225 = args[2][106 * steps + ((cycle - 0) & mask)];
assert(x6225 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x6226 = x6225 * x73;
// loc("./cirgen/components/onehot.h":44:13)
auto x6227 = x6224 + x6226;
// loc("Top/Mux/4/OneHot/Reg13"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x6228 = args[2][107 * steps + ((cycle - 0) & mask)];
assert(x6228 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x6229 = x6228 * x72;
// loc("./cirgen/components/onehot.h":44:13)
auto x6230 = x6227 + x6229;
// loc("cirgen/circuit/rv32im/sha.cpp":284:33)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6230);
reg = x6230;
}
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x6231 = x603 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x6232 = Fp(x6231.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6232);
reg = x6232;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x6233 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x6233 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x6234 = x6231 - x6233;
// loc("cirgen/components/bytes.cpp":83:10)
auto x6235 = x6234 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x6236 = Fp(x6235.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6236);
reg = x6236;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x6237 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x6237 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x6238 = x6235 - x6237;
// loc("cirgen/components/bytes.cpp":83:10)
auto x6239 = x6238 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x6240 = Fp(x6239.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6240);
reg = x6240;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x6241 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x6241 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x6242 = x6239 - x6241;
// loc("cirgen/components/bytes.cpp":83:10)
auto x6243 = x6242 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x6244 = Fp(x6243.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6244);
reg = x6244;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6245 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x6245 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x6246 = x6243 - x6245;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x6247 = x6246 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6247);
reg = x6247;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6248 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x6248 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x6249 = x102 - x6248;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x6250 = x6248 * x6249;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6250);
reg = x6250;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x6251 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x6251 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x6252 = x99 - x6248;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x6253 = x6251 * x6252;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x6253 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg"("cirgen/circuit/rv32im/sha.cpp":287:40))
auto x6254 = args[2][131 * steps + ((cycle - 1) & mask)];
assert(x6254 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":287:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6254);
reg = x6254;
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg1"("cirgen/circuit/rv32im/sha.cpp":288:38))
auto x6255 = args[2][132 * steps + ((cycle - 1) & mask)];
assert(x6255 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":288:3)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6255);
reg = x6255;
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg2"("cirgen/circuit/rv32im/sha.cpp":289:34))
auto x6256 = args[2][133 * steps + ((cycle - 1) & mask)];
assert(x6256 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":289:3)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6256);
reg = x6256;
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg3"("cirgen/circuit/rv32im/sha.cpp":290:34))
auto x6257 = args[2][134 * steps + ((cycle - 1) & mask)];
assert(x6257 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":290:3)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6257);
reg = x6257;
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg5"("cirgen/circuit/rv32im/sha.cpp":291:36))
auto x6258 = args[2][138 * steps + ((cycle - 1) & mask)];
assert(x6258 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":291:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6258);
reg = x6258;
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6259 = args[2][143 * steps + ((cycle - 1) & mask)];
assert(x6259 != Fp::invalid());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][143 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6259);
reg = x6259;
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x6260 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x6260 != Fp::invalid());
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x6261 = (x6260 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6261);
reg = x6261;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x6262 = inv(x6260);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6262);
reg = x6262;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/IsZero1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6263 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x6263 != Fp::invalid());
if (x6263 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x6260 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x6264 = x102 - x6263;
if (x6264 != 0) {
// loc("Top/Mux/4/Mux/10/ShaCycle/IsZero1/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x6265 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x6265 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x6266 = x6260 * x6265;
// loc("cirgen/components/iszero.cpp":15:26)
auto x6267 = x6266 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x6267 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x6268 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x6268 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":300:8)
auto x6269 = x6268 * x85;
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x6270 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x6270 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":301:8)
auto x6271 = x6270 * x85;
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x6272 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x6272 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":302:8)
auto x6273 = x6272 * x85;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6274 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x6274 != Fp::invalid());
host_args.at(0) = x75;
host_args.at(1) = x6274;
host_args.at(2) = x6194;
host_args.at(3) = x6269;
host_args.at(4) = x6271;
host_args.at(5) = x6273;
host_args.at(6) = x6260;
host(ctx, "log", "SHA_LOAD: major = %u, minor = %u, count = %u, data0 = 0x%x, data1 = 0x%x, state = 0x%x, repeat: %u", host_args.data(), 7, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/sha.cpp":306:15)
auto x6275 = x102 - x6274;
if (x6275 != 0) {
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6276 = args[2][143 * steps + ((cycle - 0) & mask)];
assert(x6276 != Fp::invalid());
if (x6276 != 0) {
// loc("cirgen/circuit/rv32im/sha.cpp":307:37)
auto x6277 = x6268 + x78;
// loc("cirgen/circuit/rv32im/sha.cpp":307:37)
auto x6278 = x6277 - x6194;
{
host_args.at(0) = x6278;
host_args.at(1) = x101;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x6279 = host_outs.at(0);
auto x6280 = host_outs.at(1);
auto x6281 = host_outs.at(2);
auto x6282 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6279);
reg = x6279;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6280);
reg = x6280;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6281);
reg = x6281;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6282);
reg = x6282;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6283 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x6283 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6284 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x6284 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x6285 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x6285 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x6286 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x6286 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6278);
reg = x6278;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6183);
reg = x6183;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6283);
reg = x6283;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6284);
reg = x6284;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6285);
reg = x6285;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6286);
reg = x6286;
}
}
// loc("cirgen/circuit/rv32im/sha.cpp":308:16)
auto x6287 = x102 - x6276;
if (x6287 != 0) {
// loc("cirgen/circuit/rv32im/sha.cpp":308:39)
auto x6288 = x6268 + x78;
// loc("cirgen/circuit/rv32im/sha.cpp":308:39)
auto x6289 = x6288 - x6194;
{
host_args.at(0) = x6289;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x6290 = host_outs.at(0);
auto x6291 = host_outs.at(1);
auto x6292 = host_outs.at(2);
auto x6293 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6290);
reg = x6290;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6291);
reg = x6291;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6292);
reg = x6292;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6293);
reg = x6293;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6294 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x6294 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6295 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x6295 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x6296 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x6296 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x6297 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x6297 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6289);
reg = x6289;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6183);
reg = x6183;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6294);
reg = x6294;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6295);
reg = x6295;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6296);
reg = x6296;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6297);
reg = x6297;
}
}
// loc("cirgen/circuit/rv32im/sha.cpp":309:24)
auto x6298 = x15 - x6194;
{
host_args.at(0) = x6298;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x6299 = host_outs.at(0);
auto x6300 = host_outs.at(1);
auto x6301 = host_outs.at(2);
auto x6302 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6299);
reg = x6299;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6300);
reg = x6300;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6301);
reg = x6301;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6302);
reg = x6302;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6303 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x6303 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6304 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x6304 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x6305 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x6305 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x6306 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x6306 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6298);
reg = x6298;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6183);
reg = x6183;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6303);
reg = x6303;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6304);
reg = x6304;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6305);
reg = x6305;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6306);
reg = x6306;
}
}
if (x6274 != 0) {
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6307 = args[2][143 * steps + ((cycle - 0) & mask)];
assert(x6307 != Fp::invalid());
if (x6307 != 0) {
// loc("cirgen/circuit/rv32im/sha.cpp":312:37)
auto x6308 = x6270 + x78;
// loc("cirgen/circuit/rv32im/sha.cpp":312:37)
auto x6309 = x6308 - x6194;
{
host_args.at(0) = x6309;
host_args.at(1) = x101;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x6310 = host_outs.at(0);
auto x6311 = host_outs.at(1);
auto x6312 = host_outs.at(2);
auto x6313 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6310);
reg = x6310;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6311);
reg = x6311;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6312);
reg = x6312;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6313);
reg = x6313;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6314 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x6314 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6315 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x6315 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x6316 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x6316 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x6317 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x6317 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6309);
reg = x6309;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6183);
reg = x6183;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6314);
reg = x6314;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6315);
reg = x6315;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6316);
reg = x6316;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6317);
reg = x6317;
}
}
// loc("cirgen/circuit/rv32im/sha.cpp":313:16)
auto x6318 = x102 - x6307;
if (x6318 != 0) {
// loc("cirgen/circuit/rv32im/sha.cpp":313:39)
auto x6319 = x6270 + x78;
// loc("cirgen/circuit/rv32im/sha.cpp":313:39)
auto x6320 = x6319 - x6194;
{
host_args.at(0) = x6320;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x6321 = host_outs.at(0);
auto x6322 = host_outs.at(1);
auto x6323 = host_outs.at(2);
auto x6324 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6321);
reg = x6321;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6322);
reg = x6322;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6323);
reg = x6323;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6324);
reg = x6324;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6325 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x6325 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6326 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x6326 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x6327 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x6327 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x6328 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x6328 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6320);
reg = x6320;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6183);
reg = x6183;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6325);
reg = x6325;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6326);
reg = x6326;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6327);
reg = x6327;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6328);
reg = x6328;
}
}
// loc("cirgen/circuit/rv32im/sha.cpp":314:24)
auto x6329 = x14 - x6194;
{
host_args.at(0) = x6329;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x6330 = host_outs.at(0);
auto x6331 = host_outs.at(1);
auto x6332 = host_outs.at(2);
auto x6333 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6330);
reg = x6330;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6331);
reg = x6331;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6332);
reg = x6332;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6333);
reg = x6333;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6334 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x6334 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6335 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x6335 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x6336 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x6336 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x6337 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x6337 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6329);
reg = x6329;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6183);
reg = x6183;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6334);
reg = x6334;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6335);
reg = x6335;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6336);
reg = x6336;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6337);
reg = x6337;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6338 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x6338 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6339 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x6339 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x6340 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x6340 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x6341 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x6341 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":136:26)
auto x6342 = x6340 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":136:11)
auto x6343 = x6341 + x6342;
// loc("cirgen/circuit/rv32im/sha.cpp":136:61)
auto x6344 = x6338 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":136:46)
auto x6345 = x6339 + x6344;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6346 = Fp(x6343.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6346);
reg = x6346;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6347 = Fp(x6343.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6348 = x6347 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6348);
reg = x6348;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6349 = Fp(x6343.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6350 = x6349 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6350);
reg = x6350;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6351 = Fp(x6343.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6352 = x6351 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6352);
reg = x6352;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6353 = Fp(x6343.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6354 = x6353 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6354);
reg = x6354;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6355 = Fp(x6343.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6356 = x6355 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6356);
reg = x6356;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6357 = Fp(x6343.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6358 = x6357 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6358);
reg = x6358;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6359 = Fp(x6343.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6360 = x6359 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6360);
reg = x6360;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6361 = Fp(x6343.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6362 = x6361 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6362);
reg = x6362;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6363 = Fp(x6343.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6364 = x6363 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6364);
reg = x6364;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6365 = Fp(x6343.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6366 = x6365 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][19 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6366);
reg = x6366;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6367 = Fp(x6343.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6368 = x6367 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][20 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6368);
reg = x6368;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6369 = Fp(x6343.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6370 = x6369 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][21 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6370);
reg = x6370;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6371 = Fp(x6343.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6372 = x6371 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][22 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6372);
reg = x6372;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6373 = Fp(x6343.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6374 = x6373 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][23 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6374);
reg = x6374;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6375 = Fp(x6343.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6376 = x6375 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][24 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6376);
reg = x6376;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6377 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x6377 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6378 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x6378 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6379 = x6378 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6380 = x6377 + x6379;
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6381 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x6381 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6382 = x6381 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6383 = x6380 + x6382;
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6384 = args[2][85 * steps + ((cycle - 0) & mask)];
assert(x6384 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6385 = x6384 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6386 = x6383 + x6385;
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6387 = args[2][86 * steps + ((cycle - 0) & mask)];
assert(x6387 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6388 = x6387 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6389 = x6386 + x6388;
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6390 = args[2][87 * steps + ((cycle - 0) & mask)];
assert(x6390 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6391 = x6390 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6392 = x6389 + x6391;
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6393 = args[2][88 * steps + ((cycle - 0) & mask)];
assert(x6393 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6394 = x6393 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6395 = x6392 + x6394;
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6396 = args[2][89 * steps + ((cycle - 0) & mask)];
assert(x6396 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6397 = x6396 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6398 = x6395 + x6397;
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6399 = args[2][90 * steps + ((cycle - 0) & mask)];
assert(x6399 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6400 = x6399 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6401 = x6398 + x6400;
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6402 = args[2][91 * steps + ((cycle - 0) & mask)];
assert(x6402 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6403 = x6402 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6404 = x6401 + x6403;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6405 = args[2][19 * steps + ((cycle - 0) & mask)];
assert(x6405 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6406 = x6405 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6407 = x6404 + x6406;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6408 = args[2][20 * steps + ((cycle - 0) & mask)];
assert(x6408 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6409 = x6408 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6410 = x6407 + x6409;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6411 = args[2][21 * steps + ((cycle - 0) & mask)];
assert(x6411 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6412 = x6411 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6413 = x6410 + x6412;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6414 = args[2][22 * steps + ((cycle - 0) & mask)];
assert(x6414 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6415 = x6414 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6416 = x6413 + x6415;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6417 = args[2][23 * steps + ((cycle - 0) & mask)];
assert(x6417 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6418 = x6417 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6419 = x6416 + x6418;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6420 = args[2][24 * steps + ((cycle - 0) & mask)];
assert(x6420 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6421 = x6420 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6422 = x6419 + x6421;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x6423 = x6343 - x6422;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x6424 = x6423 * x16;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6424);
reg = x6424;
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6425 = args[2][80 * steps + ((cycle - 0) & mask)];
assert(x6425 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":117:30)
auto x6426 = x6345 + x6425;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6427 = Fp(x6426.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6427);
reg = x6427;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6428 = Fp(x6426.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6429 = x6428 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6429);
reg = x6429;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6430 = Fp(x6426.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6431 = x6430 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6431);
reg = x6431;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6432 = Fp(x6426.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6433 = x6432 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6433);
reg = x6433;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6434 = Fp(x6426.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6435 = x6434 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6435);
reg = x6435;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6436 = Fp(x6426.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6437 = x6436 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6437);
reg = x6437;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6438 = Fp(x6426.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6439 = x6438 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6439);
reg = x6439;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6440 = Fp(x6426.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6441 = x6440 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6441);
reg = x6441;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6442 = Fp(x6426.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6443 = x6442 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6443);
reg = x6443;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6444 = Fp(x6426.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6445 = x6444 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6445);
reg = x6445;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6446 = Fp(x6426.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6447 = x6446 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6447);
reg = x6447;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6448 = Fp(x6426.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6449 = x6448 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6449);
reg = x6449;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6450 = Fp(x6426.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6451 = x6450 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6451);
reg = x6451;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6452 = Fp(x6426.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6453 = x6452 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6453);
reg = x6453;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6454 = Fp(x6426.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6455 = x6454 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6455);
reg = x6455;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x6456 = Fp(x6426.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x6457 = x6456 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6457);
reg = x6457;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6458 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x6458 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6459 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x6459 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6460 = x6459 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6461 = x6458 + x6460;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6462 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x6462 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6463 = x6462 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6464 = x6461 + x6463;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6465 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x6465 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6466 = x6465 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6467 = x6464 + x6466;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6468 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x6468 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6469 = x6468 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6470 = x6467 + x6469;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6471 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x6471 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6472 = x6471 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6473 = x6470 + x6472;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6474 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x6474 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6475 = x6474 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6476 = x6473 + x6475;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6477 = args[2][32 * steps + ((cycle - 0) & mask)];
assert(x6477 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6478 = x6477 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6479 = x6476 + x6478;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6480 = args[2][33 * steps + ((cycle - 0) & mask)];
assert(x6480 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6481 = x6480 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6482 = x6479 + x6481;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6483 = args[2][34 * steps + ((cycle - 0) & mask)];
assert(x6483 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6484 = x6483 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6485 = x6482 + x6484;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6486 = args[2][35 * steps + ((cycle - 0) & mask)];
assert(x6486 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6487 = x6486 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6488 = x6485 + x6487;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6489 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x6489 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6490 = x6489 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6491 = x6488 + x6490;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6492 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x6492 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6493 = x6492 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6494 = x6491 + x6493;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6495 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x6495 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6496 = x6495 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6497 = x6494 + x6496;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6498 = args[2][39 * steps + ((cycle - 0) & mask)];
assert(x6498 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6499 = x6498 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6500 = x6497 + x6499;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6501 = args[2][40 * steps + ((cycle - 0) & mask)];
assert(x6501 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x6502 = x6501 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x6503 = x6500 + x6502;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x6504 = x6426 - x6503;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x6505 = x6504 * x16;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x6505);
reg = x6505;
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6506 = args[2][150 * steps + ((cycle - 1) & mask)];
assert(x6506 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6507 = args[2][151 * steps + ((cycle - 1) & mask)];
assert(x6507 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6508 = args[2][152 * steps + ((cycle - 1) & mask)];
assert(x6508 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6509 = args[2][153 * steps + ((cycle - 1) & mask)];
assert(x6509 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6510 = args[2][154 * steps + ((cycle - 1) & mask)];
assert(x6510 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6511 = args[2][155 * steps + ((cycle - 1) & mask)];
assert(x6511 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6512 = args[2][156 * steps + ((cycle - 1) & mask)];
assert(x6512 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6513 = args[2][157 * steps + ((cycle - 1) & mask)];
assert(x6513 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6514 = args[2][158 * steps + ((cycle - 1) & mask)];
assert(x6514 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6515 = args[2][159 * steps + ((cycle - 1) & mask)];
assert(x6515 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6516 = args[2][160 * steps + ((cycle - 1) & mask)];
assert(x6516 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6517 = args[2][161 * steps + ((cycle - 1) & mask)];
assert(x6517 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6518 = args[2][162 * steps + ((cycle - 1) & mask)];
assert(x6518 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6519 = args[2][163 * steps + ((cycle - 1) & mask)];
assert(x6519 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6520 = args[2][164 * steps + ((cycle - 1) & mask)];
assert(x6520 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6521 = args[2][165 * steps + ((cycle - 1) & mask)];
assert(x6521 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6522 = args[2][166 * steps + ((cycle - 1) & mask)];
assert(x6522 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6523 = args[2][167 * steps + ((cycle - 1) & mask)];
assert(x6523 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6524 = args[2][168 * steps + ((cycle - 1) & mask)];
assert(x6524 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6525 = args[2][169 * steps + ((cycle - 1) & mask)];
assert(x6525 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6526 = args[2][170 * steps + ((cycle - 1) & mask)];
assert(x6526 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6527 = args[2][171 * steps + ((cycle - 1) & mask)];
assert(x6527 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6528 = args[2][172 * steps + ((cycle - 1) & mask)];
assert(x6528 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6529 = args[2][173 * steps + ((cycle - 1) & mask)];
assert(x6529 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6530 = args[2][174 * steps + ((cycle - 1) & mask)];
assert(x6530 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6531 = args[2][175 * steps + ((cycle - 1) & mask)];
assert(x6531 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6532 = args[2][176 * steps + ((cycle - 1) & mask)];
assert(x6532 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6533 = args[2][177 * steps + ((cycle - 1) & mask)];
assert(x6533 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6534 = args[2][178 * steps + ((cycle - 1) & mask)];
assert(x6534 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6535 = args[2][179 * steps + ((cycle - 1) & mask)];
assert(x6535 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6536 = args[2][180 * steps + ((cycle - 1) & mask)];
assert(x6536 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6537 = args[2][181 * steps + ((cycle - 1) & mask)];
assert(x6537 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6538 = args[2][150 * steps + ((cycle - 2) & mask)];
assert(x6538 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6539 = args[2][151 * steps + ((cycle - 2) & mask)];
assert(x6539 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6540 = args[2][152 * steps + ((cycle - 2) & mask)];
assert(x6540 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6541 = args[2][153 * steps + ((cycle - 2) & mask)];
assert(x6541 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6542 = args[2][154 * steps + ((cycle - 2) & mask)];
assert(x6542 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6543 = args[2][155 * steps + ((cycle - 2) & mask)];
assert(x6543 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6544 = args[2][156 * steps + ((cycle - 2) & mask)];
assert(x6544 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6545 = args[2][157 * steps + ((cycle - 2) & mask)];
assert(x6545 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6546 = args[2][158 * steps + ((cycle - 2) & mask)];
assert(x6546 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6547 = args[2][159 * steps + ((cycle - 2) & mask)];
assert(x6547 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6548 = args[2][160 * steps + ((cycle - 2) & mask)];
assert(x6548 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6549 = args[2][161 * steps + ((cycle - 2) & mask)];
assert(x6549 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6550 = args[2][162 * steps + ((cycle - 2) & mask)];
assert(x6550 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6551 = args[2][163 * steps + ((cycle - 2) & mask)];
assert(x6551 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6552 = args[2][164 * steps + ((cycle - 2) & mask)];
assert(x6552 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6553 = args[2][165 * steps + ((cycle - 2) & mask)];
assert(x6553 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6554 = args[2][166 * steps + ((cycle - 2) & mask)];
assert(x6554 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6555 = args[2][167 * steps + ((cycle - 2) & mask)];
assert(x6555 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6556 = args[2][168 * steps + ((cycle - 2) & mask)];
assert(x6556 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6557 = args[2][169 * steps + ((cycle - 2) & mask)];
assert(x6557 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6558 = args[2][170 * steps + ((cycle - 2) & mask)];
assert(x6558 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6559 = args[2][171 * steps + ((cycle - 2) & mask)];
assert(x6559 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6560 = args[2][172 * steps + ((cycle - 2) & mask)];
assert(x6560 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6561 = args[2][173 * steps + ((cycle - 2) & mask)];
assert(x6561 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6562 = args[2][174 * steps + ((cycle - 2) & mask)];
assert(x6562 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6563 = args[2][175 * steps + ((cycle - 2) & mask)];
assert(x6563 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6564 = args[2][176 * steps + ((cycle - 2) & mask)];
assert(x6564 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6565 = args[2][177 * steps + ((cycle - 2) & mask)];
assert(x6565 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6566 = args[2][178 * steps + ((cycle - 2) & mask)];
assert(x6566 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6567 = args[2][179 * steps + ((cycle - 2) & mask)];
assert(x6567 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6568 = args[2][180 * steps + ((cycle - 2) & mask)];
assert(x6568 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6569 = args[2][181 * steps + ((cycle - 2) & mask)];
assert(x6569 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6570 = args[2][150 * steps + ((cycle - 3) & mask)];
assert(x6570 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6571 = args[2][151 * steps + ((cycle - 3) & mask)];
assert(x6571 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6572 = args[2][152 * steps + ((cycle - 3) & mask)];
assert(x6572 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6573 = args[2][153 * steps + ((cycle - 3) & mask)];
assert(x6573 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6574 = args[2][154 * steps + ((cycle - 3) & mask)];
assert(x6574 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6575 = args[2][155 * steps + ((cycle - 3) & mask)];
assert(x6575 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6576 = args[2][156 * steps + ((cycle - 3) & mask)];
assert(x6576 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6577 = args[2][157 * steps + ((cycle - 3) & mask)];
assert(x6577 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6578 = args[2][158 * steps + ((cycle - 3) & mask)];
assert(x6578 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6579 = args[2][159 * steps + ((cycle - 3) & mask)];
assert(x6579 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6580 = args[2][160 * steps + ((cycle - 3) & mask)];
assert(x6580 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6581 = args[2][161 * steps + ((cycle - 3) & mask)];
assert(x6581 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6582 = args[2][162 * steps + ((cycle - 3) & mask)];
assert(x6582 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6583 = args[2][163 * steps + ((cycle - 3) & mask)];
assert(x6583 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6584 = args[2][164 * steps + ((cycle - 3) & mask)];
assert(x6584 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6585 = args[2][165 * steps + ((cycle - 3) & mask)];
assert(x6585 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6586 = args[2][166 * steps + ((cycle - 3) & mask)];
assert(x6586 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6587 = args[2][167 * steps + ((cycle - 3) & mask)];
assert(x6587 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6588 = args[2][168 * steps + ((cycle - 3) & mask)];
assert(x6588 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6589 = args[2][169 * steps + ((cycle - 3) & mask)];
assert(x6589 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6590 = args[2][170 * steps + ((cycle - 3) & mask)];
assert(x6590 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6591 = args[2][171 * steps + ((cycle - 3) & mask)];
assert(x6591 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6592 = args[2][172 * steps + ((cycle - 3) & mask)];
assert(x6592 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6593 = args[2][173 * steps + ((cycle - 3) & mask)];
assert(x6593 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6594 = args[2][174 * steps + ((cycle - 3) & mask)];
assert(x6594 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6595 = args[2][175 * steps + ((cycle - 3) & mask)];
assert(x6595 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6596 = args[2][176 * steps + ((cycle - 3) & mask)];
assert(x6596 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6597 = args[2][177 * steps + ((cycle - 3) & mask)];
assert(x6597 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6598 = args[2][178 * steps + ((cycle - 3) & mask)];
assert(x6598 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6599 = args[2][179 * steps + ((cycle - 3) & mask)];
assert(x6599 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6600 = args[2][180 * steps + ((cycle - 3) & mask)];
assert(x6600 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6601 = args[2][181 * steps + ((cycle - 3) & mask)];
assert(x6601 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6602 = args[2][150 * steps + ((cycle - 4) & mask)];
assert(x6602 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6603 = args[2][151 * steps + ((cycle - 4) & mask)];
assert(x6603 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6604 = args[2][152 * steps + ((cycle - 4) & mask)];
assert(x6604 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6605 = args[2][153 * steps + ((cycle - 4) & mask)];
assert(x6605 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6606 = args[2][154 * steps + ((cycle - 4) & mask)];
assert(x6606 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6607 = args[2][155 * steps + ((cycle - 4) & mask)];
assert(x6607 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6608 = args[2][156 * steps + ((cycle - 4) & mask)];
assert(x6608 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6609 = args[2][157 * steps + ((cycle - 4) & mask)];
assert(x6609 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6610 = args[2][158 * steps + ((cycle - 4) & mask)];
assert(x6610 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6611 = args[2][159 * steps + ((cycle - 4) & mask)];
assert(x6611 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6612 = args[2][160 * steps + ((cycle - 4) & mask)];
assert(x6612 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6613 = args[2][161 * steps + ((cycle - 4) & mask)];
assert(x6613 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6614 = args[2][162 * steps + ((cycle - 4) & mask)];
assert(x6614 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6615 = args[2][163 * steps + ((cycle - 4) & mask)];
assert(x6615 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6616 = args[2][164 * steps + ((cycle - 4) & mask)];
assert(x6616 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6617 = args[2][165 * steps + ((cycle - 4) & mask)];
assert(x6617 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6618 = args[2][166 * steps + ((cycle - 4) & mask)];
assert(x6618 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6619 = args[2][167 * steps + ((cycle - 4) & mask)];
assert(x6619 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6620 = args[2][168 * steps + ((cycle - 4) & mask)];
assert(x6620 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6621 = args[2][169 * steps + ((cycle - 4) & mask)];
assert(x6621 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6622 = args[2][170 * steps + ((cycle - 4) & mask)];
assert(x6622 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6623 = args[2][171 * steps + ((cycle - 4) & mask)];
assert(x6623 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6624 = args[2][172 * steps + ((cycle - 4) & mask)];
assert(x6624 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6625 = args[2][173 * steps + ((cycle - 4) & mask)];
assert(x6625 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6626 = args[2][174 * steps + ((cycle - 4) & mask)];
assert(x6626 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6627 = args[2][175 * steps + ((cycle - 4) & mask)];
assert(x6627 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6628 = args[2][176 * steps + ((cycle - 4) & mask)];
assert(x6628 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6629 = args[2][177 * steps + ((cycle - 4) & mask)];
assert(x6629 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6630 = args[2][178 * steps + ((cycle - 4) & mask)];
assert(x6630 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6631 = args[2][179 * steps + ((cycle - 4) & mask)];
assert(x6631 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6632 = args[2][180 * steps + ((cycle - 4) & mask)];
assert(x6632 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6633 = args[2][181 * steps + ((cycle - 4) & mask)];
assert(x6633 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6634 = args[2][182 * steps + ((cycle - 1) & mask)];
assert(x6634 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6635 = args[2][183 * steps + ((cycle - 1) & mask)];
assert(x6635 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6636 = args[2][184 * steps + ((cycle - 1) & mask)];
assert(x6636 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6637 = args[2][185 * steps + ((cycle - 1) & mask)];
assert(x6637 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6638 = args[2][186 * steps + ((cycle - 1) & mask)];
assert(x6638 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6639 = args[2][187 * steps + ((cycle - 1) & mask)];
assert(x6639 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6640 = args[2][188 * steps + ((cycle - 1) & mask)];
assert(x6640 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6641 = args[2][189 * steps + ((cycle - 1) & mask)];
assert(x6641 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6642 = args[2][190 * steps + ((cycle - 1) & mask)];
assert(x6642 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6643 = args[2][191 * steps + ((cycle - 1) & mask)];
assert(x6643 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6644 = args[2][192 * steps + ((cycle - 1) & mask)];
assert(x6644 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6645 = args[2][193 * steps + ((cycle - 1) & mask)];
assert(x6645 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6646 = args[2][194 * steps + ((cycle - 1) & mask)];
assert(x6646 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6647 = args[2][195 * steps + ((cycle - 1) & mask)];
assert(x6647 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6648 = args[2][196 * steps + ((cycle - 1) & mask)];
assert(x6648 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6649 = args[2][197 * steps + ((cycle - 1) & mask)];
assert(x6649 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6650 = args[2][198 * steps + ((cycle - 1) & mask)];
assert(x6650 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6651 = args[2][199 * steps + ((cycle - 1) & mask)];
assert(x6651 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6652 = args[2][200 * steps + ((cycle - 1) & mask)];
assert(x6652 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6653 = args[2][201 * steps + ((cycle - 1) & mask)];
assert(x6653 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6654 = args[2][202 * steps + ((cycle - 1) & mask)];
assert(x6654 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6655 = args[2][203 * steps + ((cycle - 1) & mask)];
assert(x6655 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6656 = args[2][204 * steps + ((cycle - 1) & mask)];
assert(x6656 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6657 = args[2][205 * steps + ((cycle - 1) & mask)];
assert(x6657 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6658 = args[2][206 * steps + ((cycle - 1) & mask)];
assert(x6658 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6659 = args[2][207 * steps + ((cycle - 1) & mask)];
assert(x6659 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6660 = args[2][208 * steps + ((cycle - 1) & mask)];
assert(x6660 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6661 = args[2][209 * steps + ((cycle - 1) & mask)];
assert(x6661 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6662 = args[2][210 * steps + ((cycle - 1) & mask)];
assert(x6662 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6663 = args[2][211 * steps + ((cycle - 1) & mask)];
assert(x6663 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6664 = args[2][212 * steps + ((cycle - 1) & mask)];
assert(x6664 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6665 = args[2][213 * steps + ((cycle - 1) & mask)];
assert(x6665 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6666 = args[2][182 * steps + ((cycle - 2) & mask)];
assert(x6666 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6667 = args[2][183 * steps + ((cycle - 2) & mask)];
assert(x6667 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6668 = args[2][184 * steps + ((cycle - 2) & mask)];
assert(x6668 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6669 = args[2][185 * steps + ((cycle - 2) & mask)];
assert(x6669 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6670 = args[2][186 * steps + ((cycle - 2) & mask)];
assert(x6670 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6671 = args[2][187 * steps + ((cycle - 2) & mask)];
assert(x6671 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6672 = args[2][188 * steps + ((cycle - 2) & mask)];
assert(x6672 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6673 = args[2][189 * steps + ((cycle - 2) & mask)];
assert(x6673 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6674 = args[2][190 * steps + ((cycle - 2) & mask)];
assert(x6674 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6675 = args[2][191 * steps + ((cycle - 2) & mask)];
assert(x6675 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6676 = args[2][192 * steps + ((cycle - 2) & mask)];
assert(x6676 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6677 = args[2][193 * steps + ((cycle - 2) & mask)];
assert(x6677 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6678 = args[2][194 * steps + ((cycle - 2) & mask)];
assert(x6678 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6679 = args[2][195 * steps + ((cycle - 2) & mask)];
assert(x6679 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6680 = args[2][196 * steps + ((cycle - 2) & mask)];
assert(x6680 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6681 = args[2][197 * steps + ((cycle - 2) & mask)];
assert(x6681 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6682 = args[2][198 * steps + ((cycle - 2) & mask)];
assert(x6682 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6683 = args[2][199 * steps + ((cycle - 2) & mask)];
assert(x6683 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6684 = args[2][200 * steps + ((cycle - 2) & mask)];
assert(x6684 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6685 = args[2][201 * steps + ((cycle - 2) & mask)];
assert(x6685 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6686 = args[2][202 * steps + ((cycle - 2) & mask)];
assert(x6686 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6687 = args[2][203 * steps + ((cycle - 2) & mask)];
assert(x6687 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6688 = args[2][204 * steps + ((cycle - 2) & mask)];
assert(x6688 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6689 = args[2][205 * steps + ((cycle - 2) & mask)];
assert(x6689 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6690 = args[2][206 * steps + ((cycle - 2) & mask)];
assert(x6690 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6691 = args[2][207 * steps + ((cycle - 2) & mask)];
assert(x6691 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6692 = args[2][208 * steps + ((cycle - 2) & mask)];
assert(x6692 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6693 = args[2][209 * steps + ((cycle - 2) & mask)];
assert(x6693 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6694 = args[2][210 * steps + ((cycle - 2) & mask)];
assert(x6694 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6695 = args[2][211 * steps + ((cycle - 2) & mask)];
assert(x6695 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6696 = args[2][212 * steps + ((cycle - 2) & mask)];
assert(x6696 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6697 = args[2][213 * steps + ((cycle - 2) & mask)];
assert(x6697 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6698 = args[2][182 * steps + ((cycle - 3) & mask)];
assert(x6698 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6699 = args[2][183 * steps + ((cycle - 3) & mask)];
assert(x6699 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6700 = args[2][184 * steps + ((cycle - 3) & mask)];
assert(x6700 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6701 = args[2][185 * steps + ((cycle - 3) & mask)];
assert(x6701 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6702 = args[2][186 * steps + ((cycle - 3) & mask)];
assert(x6702 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6703 = args[2][187 * steps + ((cycle - 3) & mask)];
assert(x6703 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6704 = args[2][188 * steps + ((cycle - 3) & mask)];
assert(x6704 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6705 = args[2][189 * steps + ((cycle - 3) & mask)];
assert(x6705 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6706 = args[2][190 * steps + ((cycle - 3) & mask)];
assert(x6706 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6707 = args[2][191 * steps + ((cycle - 3) & mask)];
assert(x6707 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6708 = args[2][192 * steps + ((cycle - 3) & mask)];
assert(x6708 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6709 = args[2][193 * steps + ((cycle - 3) & mask)];
assert(x6709 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6710 = args[2][194 * steps + ((cycle - 3) & mask)];
assert(x6710 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6711 = args[2][195 * steps + ((cycle - 3) & mask)];
assert(x6711 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6712 = args[2][196 * steps + ((cycle - 3) & mask)];
assert(x6712 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6713 = args[2][197 * steps + ((cycle - 3) & mask)];
assert(x6713 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6714 = args[2][198 * steps + ((cycle - 3) & mask)];
assert(x6714 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6715 = args[2][199 * steps + ((cycle - 3) & mask)];
assert(x6715 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6716 = args[2][200 * steps + ((cycle - 3) & mask)];
assert(x6716 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6717 = args[2][201 * steps + ((cycle - 3) & mask)];
assert(x6717 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6718 = args[2][202 * steps + ((cycle - 3) & mask)];
assert(x6718 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6719 = args[2][203 * steps + ((cycle - 3) & mask)];
assert(x6719 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6720 = args[2][204 * steps + ((cycle - 3) & mask)];
assert(x6720 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6721 = args[2][205 * steps + ((cycle - 3) & mask)];
assert(x6721 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6722 = args[2][206 * steps + ((cycle - 3) & mask)];
assert(x6722 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6723 = args[2][207 * steps + ((cycle - 3) & mask)];
assert(x6723 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6724 = args[2][208 * steps + ((cycle - 3) & mask)];
assert(x6724 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6725 = args[2][209 * steps + ((cycle - 3) & mask)];
assert(x6725 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6726 = args[2][210 * steps + ((cycle - 3) & mask)];
assert(x6726 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6727 = args[2][211 * steps + ((cycle - 3) & mask)];
assert(x6727 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6728 = args[2][212 * steps + ((cycle - 3) & mask)];
assert(x6728 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6729 = args[2][213 * steps + ((cycle - 3) & mask)];
assert(x6729 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6730 = args[2][182 * steps + ((cycle - 4) & mask)];
assert(x6730 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6731 = args[2][183 * steps + ((cycle - 4) & mask)];
assert(x6731 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6732 = args[2][184 * steps + ((cycle - 4) & mask)];
assert(x6732 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6733 = args[2][185 * steps + ((cycle - 4) & mask)];
assert(x6733 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6734 = args[2][186 * steps + ((cycle - 4) & mask)];
assert(x6734 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6735 = args[2][187 * steps + ((cycle - 4) & mask)];
assert(x6735 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6736 = args[2][188 * steps + ((cycle - 4) & mask)];
assert(x6736 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6737 = args[2][189 * steps + ((cycle - 4) & mask)];
assert(x6737 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6738 = args[2][190 * steps + ((cycle - 4) & mask)];
assert(x6738 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6739 = args[2][191 * steps + ((cycle - 4) & mask)];
assert(x6739 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6740 = args[2][192 * steps + ((cycle - 4) & mask)];
assert(x6740 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6741 = args[2][193 * steps + ((cycle - 4) & mask)];
assert(x6741 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6742 = args[2][194 * steps + ((cycle - 4) & mask)];
assert(x6742 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6743 = args[2][195 * steps + ((cycle - 4) & mask)];
assert(x6743 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6744 = args[2][196 * steps + ((cycle - 4) & mask)];
assert(x6744 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6745 = args[2][197 * steps + ((cycle - 4) & mask)];
assert(x6745 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6746 = args[2][198 * steps + ((cycle - 4) & mask)];
assert(x6746 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6747 = args[2][199 * steps + ((cycle - 4) & mask)];
assert(x6747 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6748 = args[2][200 * steps + ((cycle - 4) & mask)];
assert(x6748 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6749 = args[2][201 * steps + ((cycle - 4) & mask)];
assert(x6749 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6750 = args[2][202 * steps + ((cycle - 4) & mask)];
assert(x6750 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6751 = args[2][203 * steps + ((cycle - 4) & mask)];
assert(x6751 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6752 = args[2][204 * steps + ((cycle - 4) & mask)];
assert(x6752 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6753 = args[2][205 * steps + ((cycle - 4) & mask)];
assert(x6753 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6754 = args[2][206 * steps + ((cycle - 4) & mask)];
assert(x6754 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6755 = args[2][207 * steps + ((cycle - 4) & mask)];
assert(x6755 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6756 = args[2][208 * steps + ((cycle - 4) & mask)];
assert(x6756 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6757 = args[2][209 * steps + ((cycle - 4) & mask)];
assert(x6757 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6758 = args[2][210 * steps + ((cycle - 4) & mask)];
assert(x6758 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6759 = args[2][211 * steps + ((cycle - 4) & mask)];
assert(x6759 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6760 = args[2][212 * steps + ((cycle - 4) & mask)];
assert(x6760 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6761 = args[2][213 * steps + ((cycle - 4) & mask)];
assert(x6761 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x6762 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x6762 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x6763 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x6763 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x6764 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x6764 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x6765 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x6765 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":132:26)
auto x6766 = x6763 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":132:11)
auto x6767 = x6762 + x6766;
// loc("cirgen/circuit/rv32im/sha.cpp":132:61)
auto x6768 = x6765 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":132:46)
auto x6769 = x6764 + x6768;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6770 = x6519 + x6528;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6771 = x6519 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6772 = x6771 * x6528;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6773 = x6770 - x6772;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6774 = x6520 + x6529;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6775 = x6520 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6776 = x6775 * x6529;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6777 = x6774 - x6776;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6778 = x6521 + x6530;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6779 = x6521 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6780 = x6779 * x6530;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6781 = x6778 - x6780;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6782 = x6522 + x6531;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6783 = x6522 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6784 = x6783 * x6531;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6785 = x6782 - x6784;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6786 = x6523 + x6532;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6787 = x6523 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6788 = x6787 * x6532;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6789 = x6786 - x6788;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6790 = x6524 + x6533;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6791 = x6524 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6792 = x6791 * x6533;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6793 = x6790 - x6792;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6794 = x6525 + x6534;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6795 = x6525 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6796 = x6795 * x6534;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6797 = x6794 - x6796;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6798 = x6526 + x6535;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6799 = x6526 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6800 = x6799 * x6535;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6801 = x6798 - x6800;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6802 = x6527 + x6536;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6803 = x6527 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6804 = x6803 * x6536;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6805 = x6802 - x6804;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6806 = x6528 + x6537;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6807 = x6528 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6808 = x6807 * x6537;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6809 = x6806 - x6808;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6810 = x6529 + x6506;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6811 = x6529 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6812 = x6811 * x6506;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6813 = x6810 - x6812;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6814 = x6530 + x6507;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6815 = x6530 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6816 = x6815 * x6507;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6817 = x6814 - x6816;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6818 = x6531 + x6508;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6819 = x6531 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6820 = x6819 * x6508;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6821 = x6818 - x6820;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6822 = x6532 + x6509;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6823 = x6532 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6824 = x6823 * x6509;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6825 = x6822 - x6824;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6826 = x6533 + x6510;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6827 = x6533 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6828 = x6827 * x6510;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6829 = x6826 - x6828;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6830 = x6534 + x6511;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6831 = x6534 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6832 = x6831 * x6511;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6833 = x6830 - x6832;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6834 = x6535 + x6512;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6835 = x6535 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6836 = x6835 * x6512;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6837 = x6834 - x6836;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6838 = x6536 + x6513;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6839 = x6536 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6840 = x6839 * x6513;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6841 = x6838 - x6840;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6842 = x6537 + x6514;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6843 = x6537 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6844 = x6843 * x6514;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6845 = x6842 - x6844;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6846 = x6506 + x6515;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6847 = x6506 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6848 = x6847 * x6515;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6849 = x6846 - x6848;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6850 = x6507 + x6516;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6851 = x6507 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6852 = x6851 * x6516;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6853 = x6850 - x6852;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6854 = x6508 + x6517;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6855 = x6508 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6856 = x6855 * x6517;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6857 = x6854 - x6856;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6858 = x6509 + x6518;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6859 = x6509 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6860 = x6859 * x6518;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6861 = x6858 - x6860;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6862 = x6510 + x6519;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6863 = x6510 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6864 = x6863 * x6519;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6865 = x6862 - x6864;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6866 = x6511 + x6520;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6867 = x6511 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6868 = x6867 * x6520;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6869 = x6866 - x6868;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6870 = x6512 + x6521;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6871 = x6512 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6872 = x6871 * x6521;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6873 = x6870 - x6872;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6874 = x6513 + x6522;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6875 = x6513 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6876 = x6875 * x6522;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6877 = x6874 - x6876;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6878 = x6514 + x6523;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6879 = x6514 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6880 = x6879 * x6523;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6881 = x6878 - x6880;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6882 = x6515 + x6524;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6883 = x6515 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6884 = x6883 * x6524;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6885 = x6882 - x6884;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6886 = x6516 + x6525;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6887 = x6516 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6888 = x6887 * x6525;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6889 = x6886 - x6888;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6890 = x6517 + x6526;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6891 = x6517 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6892 = x6891 * x6526;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6893 = x6890 - x6892;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6894 = x6518 + x6527;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6895 = x6518 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6896 = x6895 * x6527;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6897 = x6894 - x6896;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6898 = x6508 + x6773;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6899 = x6855 * x6773;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6900 = x6898 - x6899;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6901 = x6509 + x6777;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6902 = x6859 * x6777;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6903 = x6901 - x6902;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6904 = x6510 + x6781;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6905 = x6863 * x6781;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6906 = x6904 - x6905;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6907 = x6511 + x6785;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6908 = x6867 * x6785;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6909 = x6907 - x6908;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6910 = x6512 + x6789;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6911 = x6871 * x6789;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6912 = x6910 - x6911;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6913 = x6513 + x6793;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6914 = x6875 * x6793;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6915 = x6913 - x6914;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6916 = x6514 + x6797;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6917 = x6879 * x6797;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6918 = x6916 - x6917;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6919 = x6515 + x6801;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6920 = x6883 * x6801;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6921 = x6919 - x6920;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6922 = x6516 + x6805;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6923 = x6887 * x6805;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6924 = x6922 - x6923;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6925 = x6517 + x6809;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6926 = x6891 * x6809;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6927 = x6925 - x6926;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6928 = x6518 + x6813;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6929 = x6895 * x6813;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6930 = x6928 - x6929;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6931 = x6519 + x6817;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6932 = x6771 * x6817;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6933 = x6931 - x6932;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6934 = x6520 + x6821;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6935 = x6775 * x6821;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6936 = x6934 - x6935;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6937 = x6521 + x6825;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6938 = x6779 * x6825;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6939 = x6937 - x6938;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6940 = x6522 + x6829;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6941 = x6783 * x6829;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6942 = x6940 - x6941;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6943 = x6523 + x6833;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6944 = x6787 * x6833;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6945 = x6943 - x6944;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6946 = x6524 + x6837;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6947 = x6791 * x6837;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6948 = x6946 - x6947;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6949 = x6525 + x6841;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6950 = x6795 * x6841;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6951 = x6949 - x6950;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6952 = x6526 + x6845;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6953 = x6799 * x6845;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6954 = x6952 - x6953;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6955 = x6527 + x6849;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6956 = x6803 * x6849;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6957 = x6955 - x6956;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6958 = x6528 + x6853;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6959 = x6807 * x6853;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6960 = x6958 - x6959;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6961 = x6529 + x6857;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6962 = x6811 * x6857;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6963 = x6961 - x6962;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6964 = x6530 + x6861;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6965 = x6815 * x6861;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6966 = x6964 - x6965;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6967 = x6531 + x6865;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6968 = x6819 * x6865;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6969 = x6967 - x6968;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6970 = x6532 + x6869;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6971 = x6823 * x6869;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6972 = x6970 - x6971;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6973 = x6533 + x6873;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6974 = x6827 * x6873;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6975 = x6973 - x6974;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6976 = x6534 + x6877;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6977 = x6831 * x6877;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6978 = x6976 - x6977;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6979 = x6535 + x6881;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6980 = x6835 * x6881;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6981 = x6979 - x6980;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6982 = x6536 + x6885;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6983 = x6839 * x6885;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6984 = x6982 - x6983;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6985 = x6537 + x6889;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6986 = x6843 * x6889;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6987 = x6985 - x6986;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6988 = x6506 + x6893;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6989 = x6847 * x6893;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6990 = x6988 - x6989;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6991 = x6507 + x6897;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6992 = x6851 * x6897;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6993 = x6991 - x6992;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6994 = x6645 + x6659;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6995 = x6645 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6996 = x6995 * x6659;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6997 = x6994 - x6996;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x6998 = x6646 + x6660;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x6999 = x6646 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7000 = x6999 * x6660;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7001 = x6998 - x7000;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7002 = x6647 + x6661;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7003 = x6647 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7004 = x7003 * x6661;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7005 = x7002 - x7004;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7006 = x6648 + x6662;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7007 = x6648 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7008 = x7007 * x6662;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7009 = x7006 - x7008;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7010 = x6649 + x6663;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7011 = x6649 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7012 = x7011 * x6663;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7013 = x7010 - x7012;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7014 = x6650 + x6664;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7015 = x6650 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7016 = x7015 * x6664;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7017 = x7014 - x7016;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7018 = x6651 + x6665;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7019 = x6651 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7020 = x7019 * x6665;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7021 = x7018 - x7020;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7022 = x6652 + x6634;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7023 = x6652 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7024 = x7023 * x6634;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7025 = x7022 - x7024;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7026 = x6653 + x6635;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7027 = x6653 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7028 = x7027 * x6635;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7029 = x7026 - x7028;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7030 = x6654 + x6636;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7031 = x6654 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7032 = x7031 * x6636;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7033 = x7030 - x7032;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7034 = x6655 + x6637;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7035 = x6655 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7036 = x7035 * x6637;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7037 = x7034 - x7036;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7038 = x6656 + x6638;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7039 = x6656 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7040 = x7039 * x6638;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7041 = x7038 - x7040;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7042 = x6657 + x6639;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7043 = x6657 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7044 = x7043 * x6639;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7045 = x7042 - x7044;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7046 = x6658 + x6640;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7047 = x6658 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7048 = x7047 * x6640;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7049 = x7046 - x7048;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7050 = x6659 + x6641;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7051 = x6659 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7052 = x7051 * x6641;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7053 = x7050 - x7052;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7054 = x6660 + x6642;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7055 = x6660 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7056 = x7055 * x6642;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7057 = x7054 - x7056;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7058 = x6661 + x6643;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7059 = x6661 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7060 = x7059 * x6643;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7061 = x7058 - x7060;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7062 = x6662 + x6644;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7063 = x6662 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7064 = x7063 * x6644;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7065 = x7062 - x7064;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7066 = x6663 + x6645;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7067 = x6663 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7068 = x7067 * x6645;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7069 = x7066 - x7068;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7070 = x6664 + x6646;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7071 = x6664 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7072 = x7071 * x6646;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7073 = x7070 - x7072;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7074 = x6665 + x6647;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7075 = x6665 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7076 = x7075 * x6647;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7077 = x7074 - x7076;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7078 = x6634 + x6648;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7079 = x6634 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7080 = x7079 * x6648;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7081 = x7078 - x7080;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7082 = x6635 + x6649;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7083 = x6635 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7084 = x7083 * x6649;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7085 = x7082 - x7084;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7086 = x6636 + x6650;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7087 = x6636 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7088 = x7087 * x6650;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7089 = x7086 - x7088;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7090 = x6637 + x6651;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7091 = x6637 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7092 = x7091 * x6651;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7093 = x7090 - x7092;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7094 = x6638 + x6652;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7095 = x6638 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7096 = x7095 * x6652;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7097 = x7094 - x7096;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7098 = x6639 + x6653;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7099 = x6639 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7100 = x7099 * x6653;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7101 = x7098 - x7100;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7102 = x6640 + x6654;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7103 = x6640 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7104 = x7103 * x6654;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7105 = x7102 - x7104;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7106 = x6641 + x6655;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7107 = x6641 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7108 = x7107 * x6655;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7109 = x7106 - x7108;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7110 = x6642 + x6656;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7111 = x6642 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7112 = x7111 * x6656;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7113 = x7110 - x7112;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7114 = x6643 + x6657;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7115 = x6643 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7116 = x7115 * x6657;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7117 = x7114 - x7116;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7118 = x6644 + x6658;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7119 = x6644 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7120 = x7119 * x6658;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7121 = x7118 - x7120;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7122 = x6640 + x6997;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7123 = x7103 * x6997;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7124 = x7122 - x7123;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7125 = x6641 + x7001;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7126 = x7107 * x7001;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7127 = x7125 - x7126;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7128 = x6642 + x7005;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7129 = x7111 * x7005;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7130 = x7128 - x7129;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7131 = x6643 + x7009;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7132 = x7115 * x7009;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7133 = x7131 - x7132;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7134 = x6644 + x7013;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7135 = x7119 * x7013;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7136 = x7134 - x7135;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7137 = x6645 + x7017;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7138 = x6995 * x7017;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7139 = x7137 - x7138;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7140 = x6646 + x7021;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7141 = x6999 * x7021;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7142 = x7140 - x7141;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7143 = x6647 + x7025;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7144 = x7003 * x7025;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7145 = x7143 - x7144;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7146 = x6648 + x7029;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7147 = x7007 * x7029;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7148 = x7146 - x7147;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7149 = x6649 + x7033;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7150 = x7011 * x7033;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7151 = x7149 - x7150;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7152 = x6650 + x7037;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7153 = x7015 * x7037;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7154 = x7152 - x7153;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7155 = x6651 + x7041;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7156 = x7019 * x7041;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7157 = x7155 - x7156;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7158 = x6652 + x7045;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7159 = x7023 * x7045;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7160 = x7158 - x7159;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7161 = x6653 + x7049;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7162 = x7027 * x7049;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7163 = x7161 - x7162;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7164 = x6654 + x7053;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7165 = x7031 * x7053;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7166 = x7164 - x7165;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7167 = x6655 + x7057;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7168 = x7035 * x7057;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7169 = x7167 - x7168;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7170 = x6656 + x7061;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7171 = x7039 * x7061;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7172 = x7170 - x7171;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7173 = x6657 + x7065;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7174 = x7043 * x7065;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7175 = x7173 - x7174;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7176 = x6658 + x7069;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7177 = x7047 * x7069;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7178 = x7176 - x7177;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7179 = x6659 + x7073;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7180 = x7051 * x7073;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7181 = x7179 - x7180;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7182 = x6660 + x7077;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7183 = x7055 * x7077;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7184 = x7182 - x7183;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7185 = x6661 + x7081;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7186 = x7059 * x7081;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7187 = x7185 - x7186;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7188 = x6662 + x7085;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7189 = x7063 * x7085;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7190 = x7188 - x7189;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7191 = x6663 + x7089;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7192 = x7067 * x7089;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7193 = x7191 - x7192;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7194 = x6664 + x7093;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7195 = x7071 * x7093;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7196 = x7194 - x7195;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7197 = x6665 + x7097;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7198 = x7075 * x7097;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7199 = x7197 - x7198;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7200 = x6634 + x7101;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7201 = x7079 * x7101;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7202 = x7200 - x7201;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7203 = x6635 + x7105;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7204 = x7083 * x7105;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7205 = x7203 - x7204;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7206 = x6636 + x7109;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7207 = x7087 * x7109;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7208 = x7206 - x7207;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7209 = x6637 + x7113;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7210 = x7091 * x7113;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7211 = x7209 - x7210;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7212 = x6638 + x7117;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7213 = x7095 * x7117;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7214 = x7212 - x7213;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7215 = x6639 + x7121;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x7216 = x7099 * x7121;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x7217 = x7215 - x7216;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7218 = x6731 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7219 = x6730 + x7218;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7220 = x6732 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7221 = x7219 + x7220;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7222 = x6733 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7223 = x7221 + x7222;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7224 = x6734 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7225 = x7223 + x7224;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7226 = x6735 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7227 = x7225 + x7226;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7228 = x6736 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7229 = x7227 + x7228;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7230 = x6737 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7231 = x7229 + x7230;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7232 = x6738 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7233 = x7231 + x7232;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7234 = x6739 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7235 = x7233 + x7234;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7236 = x6740 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7237 = x7235 + x7236;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7238 = x6741 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7239 = x7237 + x7238;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7240 = x6742 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7241 = x7239 + x7240;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7242 = x6743 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7243 = x7241 + x7242;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7244 = x6744 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7245 = x7243 + x7244;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7246 = x6745 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7247 = x7245 + x7246;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7248 = x6747 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7249 = x6746 + x7248;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7250 = x6748 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7251 = x7249 + x7250;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7252 = x6749 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7253 = x7251 + x7252;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7254 = x6750 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7255 = x7253 + x7254;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7256 = x6751 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7257 = x7255 + x7256;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7258 = x6752 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7259 = x7257 + x7258;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7260 = x6753 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7261 = x7259 + x7260;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7262 = x6754 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7263 = x7261 + x7262;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7264 = x6755 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7265 = x7263 + x7264;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7266 = x6756 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7267 = x7265 + x7266;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7268 = x6757 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7269 = x7267 + x7268;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7270 = x6758 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7271 = x7269 + x7270;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7272 = x6759 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7273 = x7271 + x7272;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7274 = x6760 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7275 = x7273 + x7274;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7276 = x6761 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7277 = x7275 + x7276;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7278 = x6634 * x6666;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7279 = x102 - x6634;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7280 = x7279 * x6698;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7281 = x7278 + x7280;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7282 = x6635 * x6667;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7283 = x102 - x6635;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7284 = x7283 * x6699;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7285 = x7282 + x7284;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7286 = x6636 * x6668;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7287 = x102 - x6636;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7288 = x7287 * x6700;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7289 = x7286 + x7288;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7290 = x6637 * x6669;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7291 = x102 - x6637;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7292 = x7291 * x6701;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7293 = x7290 + x7292;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7294 = x6638 * x6670;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7295 = x102 - x6638;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7296 = x7295 * x6702;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7297 = x7294 + x7296;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7298 = x6639 * x6671;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7299 = x102 - x6639;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7300 = x7299 * x6703;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7301 = x7298 + x7300;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7302 = x6640 * x6672;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7303 = x102 - x6640;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7304 = x7303 * x6704;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7305 = x7302 + x7304;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7306 = x6641 * x6673;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7307 = x102 - x6641;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7308 = x7307 * x6705;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7309 = x7306 + x7308;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7310 = x6642 * x6674;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7311 = x102 - x6642;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7312 = x7311 * x6706;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7313 = x7310 + x7312;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7314 = x6643 * x6675;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7315 = x102 - x6643;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7316 = x7315 * x6707;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7317 = x7314 + x7316;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7318 = x6644 * x6676;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7319 = x102 - x6644;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7320 = x7319 * x6708;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7321 = x7318 + x7320;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7322 = x6645 * x6677;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7323 = x102 - x6645;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7324 = x7323 * x6709;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7325 = x7322 + x7324;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7326 = x6646 * x6678;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7327 = x102 - x6646;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7328 = x7327 * x6710;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7329 = x7326 + x7328;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7330 = x6647 * x6679;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7331 = x102 - x6647;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7332 = x7331 * x6711;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7333 = x7330 + x7332;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7334 = x6648 * x6680;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7335 = x102 - x6648;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7336 = x7335 * x6712;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7337 = x7334 + x7336;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7338 = x6649 * x6681;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7339 = x102 - x6649;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7340 = x7339 * x6713;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7341 = x7338 + x7340;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7342 = x6650 * x6682;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7343 = x102 - x6650;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7344 = x7343 * x6714;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7345 = x7342 + x7344;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7346 = x6651 * x6683;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7347 = x102 - x6651;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7348 = x7347 * x6715;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7349 = x7346 + x7348;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7350 = x6652 * x6684;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7351 = x102 - x6652;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7352 = x7351 * x6716;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7353 = x7350 + x7352;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7354 = x6653 * x6685;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7355 = x102 - x6653;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7356 = x7355 * x6717;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7357 = x7354 + x7356;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7358 = x6654 * x6686;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7359 = x102 - x6654;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7360 = x7359 * x6718;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7361 = x7358 + x7360;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7362 = x6655 * x6687;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7363 = x102 - x6655;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7364 = x7363 * x6719;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7365 = x7362 + x7364;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7366 = x6656 * x6688;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7367 = x102 - x6656;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7368 = x7367 * x6720;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7369 = x7366 + x7368;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7370 = x6657 * x6689;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7371 = x102 - x6657;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7372 = x7371 * x6721;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7373 = x7370 + x7372;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7374 = x6658 * x6690;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7375 = x102 - x6658;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7376 = x7375 * x6722;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7377 = x7374 + x7376;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7378 = x6659 * x6691;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7379 = x102 - x6659;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7380 = x7379 * x6723;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7381 = x7378 + x7380;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7382 = x6660 * x6692;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7383 = x102 - x6660;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7384 = x7383 * x6724;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7385 = x7382 + x7384;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7386 = x6661 * x6693;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7387 = x102 - x6661;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7388 = x7387 * x6725;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7389 = x7386 + x7388;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7390 = x6662 * x6694;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7391 = x102 - x6662;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7392 = x7391 * x6726;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7393 = x7390 + x7392;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7394 = x6663 * x6695;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7395 = x102 - x6663;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7396 = x7395 * x6727;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7397 = x7394 + x7396;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7398 = x6664 * x6696;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7399 = x102 - x6664;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7400 = x7399 * x6728;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7401 = x7398 + x7400;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7402 = x6665 * x6697;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x7403 = x102 - x6665;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x7404 = x7403 * x6729;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x7405 = x7402 + x7404;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7406 = x7285 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7407 = x7281 + x7406;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7408 = x7289 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7409 = x7407 + x7408;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7410 = x7293 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7411 = x7409 + x7410;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7412 = x7297 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7413 = x7411 + x7412;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7414 = x7301 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7415 = x7413 + x7414;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7416 = x7305 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7417 = x7415 + x7416;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7418 = x7309 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7419 = x7417 + x7418;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7420 = x7313 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7421 = x7419 + x7420;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7422 = x7317 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7423 = x7421 + x7422;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7424 = x7321 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7425 = x7423 + x7424;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7426 = x7325 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7427 = x7425 + x7426;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7428 = x7329 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7429 = x7427 + x7428;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7430 = x7333 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7431 = x7429 + x7430;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7432 = x7337 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7433 = x7431 + x7432;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7434 = x7341 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7435 = x7433 + x7434;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7436 = x7349 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7437 = x7345 + x7436;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7438 = x7353 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7439 = x7437 + x7438;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7440 = x7357 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7441 = x7439 + x7440;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7442 = x7361 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7443 = x7441 + x7442;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7444 = x7365 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7445 = x7443 + x7444;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7446 = x7369 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7447 = x7445 + x7446;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7448 = x7373 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7449 = x7447 + x7448;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7450 = x7377 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7451 = x7449 + x7450;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7452 = x7381 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7453 = x7451 + x7452;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7454 = x7385 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7455 = x7453 + x7454;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7456 = x7389 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7457 = x7455 + x7456;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7458 = x7393 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7459 = x7457 + x7458;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7460 = x7397 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7461 = x7459 + x7460;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7462 = x7401 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7463 = x7461 + x7462;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7464 = x7405 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7465 = x7463 + x7464;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7466 = x7127 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7467 = x7124 + x7466;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7468 = x7130 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7469 = x7467 + x7468;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7470 = x7133 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7471 = x7469 + x7470;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7472 = x7136 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7473 = x7471 + x7472;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7474 = x7139 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7475 = x7473 + x7474;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7476 = x7142 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7477 = x7475 + x7476;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7478 = x7145 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7479 = x7477 + x7478;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7480 = x7148 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7481 = x7479 + x7480;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7482 = x7151 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7483 = x7481 + x7482;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7484 = x7154 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7485 = x7483 + x7484;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7486 = x7157 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7487 = x7485 + x7486;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7488 = x7160 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7489 = x7487 + x7488;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7490 = x7163 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7491 = x7489 + x7490;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7492 = x7166 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7493 = x7491 + x7492;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7494 = x7169 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7495 = x7493 + x7494;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7496 = x7175 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7497 = x7172 + x7496;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7498 = x7178 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7499 = x7497 + x7498;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7500 = x7181 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7501 = x7499 + x7500;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7502 = x7184 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7503 = x7501 + x7502;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7504 = x7187 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7505 = x7503 + x7504;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7506 = x7190 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7507 = x7505 + x7506;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7508 = x7193 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7509 = x7507 + x7508;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7510 = x7196 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7511 = x7509 + x7510;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7512 = x7199 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7513 = x7511 + x7512;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7514 = x7202 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7515 = x7513 + x7514;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7516 = x7205 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7517 = x7515 + x7516;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7518 = x7208 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7519 = x7517 + x7518;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7520 = x7211 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7521 = x7519 + x7520;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7522 = x7214 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7523 = x7521 + x7522;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7524 = x7217 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7525 = x7523 + x7524;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x7526 = x7435 + x7495;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x7527 = x7465 + x7525;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x7528 = x7247 + x7526;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x7529 = x7277 + x7527;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x7530 = x6767 + x7528;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x7531 = x6769 + x7529;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x7532 = x6422 + x7530;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x7533 = x6503 + x7531;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7534 = x6506 * x6538;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7535 = x102 - x6570;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7536 = x7534 * x7535;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7537 = x102 - x6538;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7538 = x6506 * x7537;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7539 = x7538 * x6570;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7540 = x7536 + x7539;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7541 = x102 - x6506;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7542 = x7541 * x6538;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7543 = x7542 * x6570;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7544 = x7540 + x7543;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7545 = x7534 * x6570;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7546 = x7544 + x7545;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7547 = x6507 * x6539;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7548 = x102 - x6571;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7549 = x7547 * x7548;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7550 = x102 - x6539;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7551 = x6507 * x7550;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7552 = x7551 * x6571;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7553 = x7549 + x7552;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7554 = x102 - x6507;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7555 = x7554 * x6539;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7556 = x7555 * x6571;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7557 = x7553 + x7556;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7558 = x7547 * x6571;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7559 = x7557 + x7558;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7560 = x6508 * x6540;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7561 = x102 - x6572;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7562 = x7560 * x7561;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7563 = x102 - x6540;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7564 = x6508 * x7563;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7565 = x7564 * x6572;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7566 = x7562 + x7565;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7567 = x102 - x6508;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7568 = x7567 * x6540;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7569 = x7568 * x6572;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7570 = x7566 + x7569;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7571 = x7560 * x6572;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7572 = x7570 + x7571;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7573 = x6509 * x6541;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7574 = x102 - x6573;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7575 = x7573 * x7574;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7576 = x102 - x6541;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7577 = x6509 * x7576;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7578 = x7577 * x6573;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7579 = x7575 + x7578;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7580 = x102 - x6509;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7581 = x7580 * x6541;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7582 = x7581 * x6573;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7583 = x7579 + x7582;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7584 = x7573 * x6573;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7585 = x7583 + x7584;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7586 = x6510 * x6542;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7587 = x102 - x6574;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7588 = x7586 * x7587;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7589 = x102 - x6542;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7590 = x6510 * x7589;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7591 = x7590 * x6574;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7592 = x7588 + x7591;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7593 = x102 - x6510;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7594 = x7593 * x6542;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7595 = x7594 * x6574;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7596 = x7592 + x7595;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7597 = x7586 * x6574;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7598 = x7596 + x7597;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7599 = x6511 * x6543;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7600 = x102 - x6575;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7601 = x7599 * x7600;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7602 = x102 - x6543;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7603 = x6511 * x7602;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7604 = x7603 * x6575;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7605 = x7601 + x7604;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7606 = x102 - x6511;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7607 = x7606 * x6543;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7608 = x7607 * x6575;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7609 = x7605 + x7608;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7610 = x7599 * x6575;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7611 = x7609 + x7610;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7612 = x6512 * x6544;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7613 = x102 - x6576;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7614 = x7612 * x7613;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7615 = x102 - x6544;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7616 = x6512 * x7615;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7617 = x7616 * x6576;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7618 = x7614 + x7617;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7619 = x102 - x6512;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7620 = x7619 * x6544;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7621 = x7620 * x6576;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7622 = x7618 + x7621;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7623 = x7612 * x6576;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7624 = x7622 + x7623;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7625 = x6513 * x6545;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7626 = x102 - x6577;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7627 = x7625 * x7626;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7628 = x102 - x6545;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7629 = x6513 * x7628;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7630 = x7629 * x6577;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7631 = x7627 + x7630;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7632 = x102 - x6513;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7633 = x7632 * x6545;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7634 = x7633 * x6577;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7635 = x7631 + x7634;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7636 = x7625 * x6577;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7637 = x7635 + x7636;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7638 = x6514 * x6546;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7639 = x102 - x6578;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7640 = x7638 * x7639;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7641 = x102 - x6546;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7642 = x6514 * x7641;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7643 = x7642 * x6578;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7644 = x7640 + x7643;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7645 = x102 - x6514;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7646 = x7645 * x6546;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7647 = x7646 * x6578;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7648 = x7644 + x7647;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7649 = x7638 * x6578;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7650 = x7648 + x7649;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7651 = x6515 * x6547;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7652 = x102 - x6579;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7653 = x7651 * x7652;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7654 = x102 - x6547;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7655 = x6515 * x7654;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7656 = x7655 * x6579;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7657 = x7653 + x7656;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7658 = x102 - x6515;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7659 = x7658 * x6547;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7660 = x7659 * x6579;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7661 = x7657 + x7660;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7662 = x7651 * x6579;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7663 = x7661 + x7662;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7664 = x6516 * x6548;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7665 = x102 - x6580;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7666 = x7664 * x7665;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7667 = x102 - x6548;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7668 = x6516 * x7667;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7669 = x7668 * x6580;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7670 = x7666 + x7669;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7671 = x102 - x6516;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7672 = x7671 * x6548;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7673 = x7672 * x6580;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7674 = x7670 + x7673;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7675 = x7664 * x6580;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7676 = x7674 + x7675;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7677 = x6517 * x6549;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7678 = x102 - x6581;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7679 = x7677 * x7678;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7680 = x102 - x6549;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7681 = x6517 * x7680;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7682 = x7681 * x6581;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7683 = x7679 + x7682;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7684 = x102 - x6517;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7685 = x7684 * x6549;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7686 = x7685 * x6581;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7687 = x7683 + x7686;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7688 = x7677 * x6581;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7689 = x7687 + x7688;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7690 = x6518 * x6550;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7691 = x102 - x6582;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7692 = x7690 * x7691;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7693 = x102 - x6550;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7694 = x6518 * x7693;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7695 = x7694 * x6582;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7696 = x7692 + x7695;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7697 = x102 - x6518;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7698 = x7697 * x6550;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7699 = x7698 * x6582;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7700 = x7696 + x7699;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7701 = x7690 * x6582;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7702 = x7700 + x7701;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7703 = x6519 * x6551;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7704 = x102 - x6583;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7705 = x7703 * x7704;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7706 = x102 - x6551;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7707 = x6519 * x7706;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7708 = x7707 * x6583;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7709 = x7705 + x7708;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7710 = x102 - x6519;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7711 = x7710 * x6551;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7712 = x7711 * x6583;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7713 = x7709 + x7712;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7714 = x7703 * x6583;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7715 = x7713 + x7714;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7716 = x6520 * x6552;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7717 = x102 - x6584;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7718 = x7716 * x7717;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7719 = x102 - x6552;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7720 = x6520 * x7719;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7721 = x7720 * x6584;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7722 = x7718 + x7721;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7723 = x102 - x6520;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7724 = x7723 * x6552;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7725 = x7724 * x6584;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7726 = x7722 + x7725;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7727 = x7716 * x6584;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7728 = x7726 + x7727;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7729 = x6521 * x6553;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7730 = x102 - x6585;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7731 = x7729 * x7730;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7732 = x102 - x6553;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7733 = x6521 * x7732;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7734 = x7733 * x6585;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7735 = x7731 + x7734;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7736 = x102 - x6521;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7737 = x7736 * x6553;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7738 = x7737 * x6585;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7739 = x7735 + x7738;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7740 = x7729 * x6585;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7741 = x7739 + x7740;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7742 = x6522 * x6554;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7743 = x102 - x6586;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7744 = x7742 * x7743;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7745 = x102 - x6554;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7746 = x6522 * x7745;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7747 = x7746 * x6586;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7748 = x7744 + x7747;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7749 = x102 - x6522;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7750 = x7749 * x6554;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7751 = x7750 * x6586;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7752 = x7748 + x7751;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7753 = x7742 * x6586;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7754 = x7752 + x7753;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7755 = x6523 * x6555;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7756 = x102 - x6587;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7757 = x7755 * x7756;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7758 = x102 - x6555;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7759 = x6523 * x7758;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7760 = x7759 * x6587;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7761 = x7757 + x7760;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7762 = x102 - x6523;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7763 = x7762 * x6555;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7764 = x7763 * x6587;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7765 = x7761 + x7764;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7766 = x7755 * x6587;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7767 = x7765 + x7766;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7768 = x6524 * x6556;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7769 = x102 - x6588;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7770 = x7768 * x7769;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7771 = x102 - x6556;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7772 = x6524 * x7771;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7773 = x7772 * x6588;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7774 = x7770 + x7773;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7775 = x102 - x6524;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7776 = x7775 * x6556;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7777 = x7776 * x6588;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7778 = x7774 + x7777;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7779 = x7768 * x6588;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7780 = x7778 + x7779;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7781 = x6525 * x6557;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7782 = x102 - x6589;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7783 = x7781 * x7782;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7784 = x102 - x6557;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7785 = x6525 * x7784;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7786 = x7785 * x6589;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7787 = x7783 + x7786;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7788 = x102 - x6525;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7789 = x7788 * x6557;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7790 = x7789 * x6589;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7791 = x7787 + x7790;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7792 = x7781 * x6589;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7793 = x7791 + x7792;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7794 = x6526 * x6558;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7795 = x102 - x6590;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7796 = x7794 * x7795;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7797 = x102 - x6558;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7798 = x6526 * x7797;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7799 = x7798 * x6590;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7800 = x7796 + x7799;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7801 = x102 - x6526;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7802 = x7801 * x6558;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7803 = x7802 * x6590;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7804 = x7800 + x7803;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7805 = x7794 * x6590;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7806 = x7804 + x7805;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7807 = x6527 * x6559;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7808 = x102 - x6591;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7809 = x7807 * x7808;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7810 = x102 - x6559;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7811 = x6527 * x7810;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7812 = x7811 * x6591;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7813 = x7809 + x7812;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7814 = x102 - x6527;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7815 = x7814 * x6559;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7816 = x7815 * x6591;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7817 = x7813 + x7816;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7818 = x7807 * x6591;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7819 = x7817 + x7818;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7820 = x6528 * x6560;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7821 = x102 - x6592;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7822 = x7820 * x7821;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7823 = x102 - x6560;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7824 = x6528 * x7823;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7825 = x7824 * x6592;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7826 = x7822 + x7825;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7827 = x102 - x6528;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7828 = x7827 * x6560;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7829 = x7828 * x6592;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7830 = x7826 + x7829;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7831 = x7820 * x6592;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7832 = x7830 + x7831;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7833 = x6529 * x6561;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7834 = x102 - x6593;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7835 = x7833 * x7834;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7836 = x102 - x6561;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7837 = x6529 * x7836;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7838 = x7837 * x6593;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7839 = x7835 + x7838;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7840 = x102 - x6529;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7841 = x7840 * x6561;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7842 = x7841 * x6593;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7843 = x7839 + x7842;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7844 = x7833 * x6593;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7845 = x7843 + x7844;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7846 = x6530 * x6562;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7847 = x102 - x6594;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7848 = x7846 * x7847;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7849 = x102 - x6562;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7850 = x6530 * x7849;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7851 = x7850 * x6594;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7852 = x7848 + x7851;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7853 = x102 - x6530;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7854 = x7853 * x6562;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7855 = x7854 * x6594;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7856 = x7852 + x7855;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7857 = x7846 * x6594;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7858 = x7856 + x7857;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7859 = x6531 * x6563;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7860 = x102 - x6595;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7861 = x7859 * x7860;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7862 = x102 - x6563;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7863 = x6531 * x7862;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7864 = x7863 * x6595;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7865 = x7861 + x7864;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7866 = x102 - x6531;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7867 = x7866 * x6563;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7868 = x7867 * x6595;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7869 = x7865 + x7868;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7870 = x7859 * x6595;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7871 = x7869 + x7870;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7872 = x6532 * x6564;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7873 = x102 - x6596;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7874 = x7872 * x7873;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7875 = x102 - x6564;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7876 = x6532 * x7875;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7877 = x7876 * x6596;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7878 = x7874 + x7877;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7879 = x102 - x6532;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7880 = x7879 * x6564;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7881 = x7880 * x6596;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7882 = x7878 + x7881;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7883 = x7872 * x6596;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7884 = x7882 + x7883;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7885 = x6533 * x6565;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7886 = x102 - x6597;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7887 = x7885 * x7886;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7888 = x102 - x6565;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7889 = x6533 * x7888;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7890 = x7889 * x6597;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7891 = x7887 + x7890;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7892 = x102 - x6533;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7893 = x7892 * x6565;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7894 = x7893 * x6597;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7895 = x7891 + x7894;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7896 = x7885 * x6597;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7897 = x7895 + x7896;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7898 = x6534 * x6566;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7899 = x102 - x6598;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7900 = x7898 * x7899;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7901 = x102 - x6566;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7902 = x6534 * x7901;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7903 = x7902 * x6598;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7904 = x7900 + x7903;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7905 = x102 - x6534;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7906 = x7905 * x6566;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7907 = x7906 * x6598;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7908 = x7904 + x7907;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7909 = x7898 * x6598;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7910 = x7908 + x7909;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7911 = x6535 * x6567;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7912 = x102 - x6599;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7913 = x7911 * x7912;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7914 = x102 - x6567;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7915 = x6535 * x7914;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7916 = x7915 * x6599;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7917 = x7913 + x7916;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7918 = x102 - x6535;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7919 = x7918 * x6567;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7920 = x7919 * x6599;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7921 = x7917 + x7920;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7922 = x7911 * x6599;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7923 = x7921 + x7922;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7924 = x6536 * x6568;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7925 = x102 - x6600;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7926 = x7924 * x7925;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7927 = x102 - x6568;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7928 = x6536 * x7927;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7929 = x7928 * x6600;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7930 = x7926 + x7929;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7931 = x102 - x6536;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7932 = x7931 * x6568;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7933 = x7932 * x6600;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7934 = x7930 + x7933;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7935 = x7924 * x6600;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7936 = x7934 + x7935;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7937 = x6537 * x6569;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x7938 = x102 - x6601;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7939 = x7937 * x7938;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x7940 = x102 - x6569;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7941 = x6537 * x7940;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x7942 = x7941 * x6601;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7943 = x7939 + x7942;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x7944 = x102 - x6537;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7945 = x7944 * x6569;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x7946 = x7945 * x6601;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7947 = x7943 + x7946;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x7948 = x7937 * x6601;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x7949 = x7947 + x7948;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7950 = x7559 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7951 = x7546 + x7950;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7952 = x7572 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7953 = x7951 + x7952;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7954 = x7585 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7955 = x7953 + x7954;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7956 = x7598 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7957 = x7955 + x7956;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7958 = x7611 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7959 = x7957 + x7958;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7960 = x7624 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7961 = x7959 + x7960;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7962 = x7637 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7963 = x7961 + x7962;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7964 = x7650 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7965 = x7963 + x7964;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7966 = x7663 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7967 = x7965 + x7966;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7968 = x7676 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7969 = x7967 + x7968;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7970 = x7689 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7971 = x7969 + x7970;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7972 = x7702 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7973 = x7971 + x7972;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7974 = x7715 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7975 = x7973 + x7974;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7976 = x7728 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7977 = x7975 + x7976;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7978 = x7741 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7979 = x7977 + x7978;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7980 = x7767 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7981 = x7754 + x7980;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7982 = x7780 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7983 = x7981 + x7982;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7984 = x7793 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7985 = x7983 + x7984;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7986 = x7806 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7987 = x7985 + x7986;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7988 = x7819 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7989 = x7987 + x7988;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7990 = x7832 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7991 = x7989 + x7990;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7992 = x7845 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7993 = x7991 + x7992;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7994 = x7858 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7995 = x7993 + x7994;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7996 = x7871 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7997 = x7995 + x7996;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x7998 = x7884 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x7999 = x7997 + x7998;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8000 = x7897 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8001 = x7999 + x8000;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8002 = x7910 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8003 = x8001 + x8002;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8004 = x7923 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8005 = x8003 + x8004;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8006 = x7936 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8007 = x8005 + x8006;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8008 = x7949 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8009 = x8007 + x8008;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8010 = x6903 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8011 = x6900 + x8010;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8012 = x6906 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8013 = x8011 + x8012;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8014 = x6909 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8015 = x8013 + x8014;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8016 = x6912 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8017 = x8015 + x8016;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8018 = x6915 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8019 = x8017 + x8018;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8020 = x6918 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8021 = x8019 + x8020;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8022 = x6921 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8023 = x8021 + x8022;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8024 = x6924 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8025 = x8023 + x8024;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8026 = x6927 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8027 = x8025 + x8026;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8028 = x6930 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8029 = x8027 + x8028;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8030 = x6933 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8031 = x8029 + x8030;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8032 = x6936 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8033 = x8031 + x8032;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8034 = x6939 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8035 = x8033 + x8034;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8036 = x6942 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8037 = x8035 + x8036;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8038 = x6945 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8039 = x8037 + x8038;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8040 = x6951 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8041 = x6948 + x8040;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8042 = x6954 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8043 = x8041 + x8042;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8044 = x6957 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8045 = x8043 + x8044;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8046 = x6960 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8047 = x8045 + x8046;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8048 = x6963 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8049 = x8047 + x8048;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8050 = x6966 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8051 = x8049 + x8050;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8052 = x6969 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8053 = x8051 + x8052;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8054 = x6972 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8055 = x8053 + x8054;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8056 = x6975 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8057 = x8055 + x8056;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8058 = x6978 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8059 = x8057 + x8058;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8060 = x6981 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8061 = x8059 + x8060;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8062 = x6984 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8063 = x8061 + x8062;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8064 = x6987 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8065 = x8063 + x8064;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8066 = x6990 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8067 = x8065 + x8066;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8068 = x6993 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8069 = x8067 + x8068;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x8070 = x7979 + x8039;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x8071 = x8009 + x8069;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x8072 = x7532 + x8070;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x8073 = x7533 + x8071;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8074 = x6603 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8075 = x6602 + x8074;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8076 = x6604 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8077 = x8075 + x8076;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8078 = x6605 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8079 = x8077 + x8078;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8080 = x6606 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8081 = x8079 + x8080;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8082 = x6607 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8083 = x8081 + x8082;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8084 = x6608 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8085 = x8083 + x8084;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8086 = x6609 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8087 = x8085 + x8086;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8088 = x6610 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8089 = x8087 + x8088;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8090 = x6611 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8091 = x8089 + x8090;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8092 = x6612 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8093 = x8091 + x8092;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8094 = x6613 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8095 = x8093 + x8094;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8096 = x6614 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8097 = x8095 + x8096;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8098 = x6615 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8099 = x8097 + x8098;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8100 = x6616 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8101 = x8099 + x8100;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8102 = x6617 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8103 = x8101 + x8102;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8104 = x6619 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8105 = x6618 + x8104;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8106 = x6620 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8107 = x8105 + x8106;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8108 = x6621 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8109 = x8107 + x8108;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8110 = x6622 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8111 = x8109 + x8110;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8112 = x6623 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8113 = x8111 + x8112;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8114 = x6624 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8115 = x8113 + x8114;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8116 = x6625 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8117 = x8115 + x8116;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8118 = x6626 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8119 = x8117 + x8118;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8120 = x6627 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8121 = x8119 + x8120;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8122 = x6628 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8123 = x8121 + x8122;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8124 = x6629 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8125 = x8123 + x8124;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8126 = x6630 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8127 = x8125 + x8126;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8128 = x6631 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8129 = x8127 + x8128;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8130 = x6632 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8131 = x8129 + x8130;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x8132 = x6633 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x8133 = x8131 + x8132;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x8134 = x7532 + x8103;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x8135 = x7533 + x8133;
// loc("cirgen/circuit/rv32im/sha.cpp":488:5)
{
auto& reg = args[2][144 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8072);
reg = x8072;
}
// loc("cirgen/circuit/rv32im/sha.cpp":489:5)
{
auto& reg = args[2][146 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8134);
reg = x8134;
}
// loc("cirgen/circuit/rv32im/sha.cpp":488:5)
{
auto& reg = args[2][145 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8073);
reg = x8073;
}
// loc("cirgen/circuit/rv32im/sha.cpp":489:5)
{
auto& reg = args[2][147 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8135);
reg = x8135;
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg6"("cirgen/circuit/rv32im/sha.cpp":140:11))
auto x8136 = args[2][144 * steps + ((cycle - 0) & mask)];
assert(x8136 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg7"("cirgen/circuit/rv32im/sha.cpp":140:26))
auto x8137 = args[2][145 * steps + ((cycle - 0) & mask)];
assert(x8137 != Fp::invalid());
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8138 = Fp(x8136.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][150 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8138);
reg = x8138;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8139 = Fp(x8136.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8140 = x8139 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][151 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8140);
reg = x8140;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8141 = Fp(x8136.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8142 = x8141 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][152 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8142);
reg = x8142;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8143 = Fp(x8136.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8144 = x8143 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][153 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8144);
reg = x8144;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8145 = Fp(x8136.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8146 = x8145 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][154 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8146);
reg = x8146;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8147 = Fp(x8136.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8148 = x8147 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][155 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8148);
reg = x8148;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8149 = Fp(x8136.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8150 = x8149 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][156 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8150);
reg = x8150;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8151 = Fp(x8136.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8152 = x8151 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][157 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8152);
reg = x8152;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8153 = Fp(x8136.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8154 = x8153 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][158 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8154);
reg = x8154;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8155 = Fp(x8136.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8156 = x8155 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][159 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8156);
reg = x8156;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8157 = Fp(x8136.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8158 = x8157 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][160 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8158);
reg = x8158;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8159 = Fp(x8136.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8160 = x8159 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8160);
reg = x8160;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8161 = Fp(x8136.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8162 = x8161 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8162);
reg = x8162;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8163 = Fp(x8136.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8164 = x8163 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8164);
reg = x8164;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8165 = Fp(x8136.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8166 = x8165 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8166);
reg = x8166;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8167 = Fp(x8136.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8168 = x8167 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8168);
reg = x8168;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8169 = args[2][150 * steps + ((cycle - 0) & mask)];
assert(x8169 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8170 = args[2][151 * steps + ((cycle - 0) & mask)];
assert(x8170 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8171 = x8170 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8172 = x8169 + x8171;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8173 = args[2][152 * steps + ((cycle - 0) & mask)];
assert(x8173 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8174 = x8173 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8175 = x8172 + x8174;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8176 = args[2][153 * steps + ((cycle - 0) & mask)];
assert(x8176 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8177 = x8176 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8178 = x8175 + x8177;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8179 = args[2][154 * steps + ((cycle - 0) & mask)];
assert(x8179 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8180 = x8179 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8181 = x8178 + x8180;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8182 = args[2][155 * steps + ((cycle - 0) & mask)];
assert(x8182 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8183 = x8182 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8184 = x8181 + x8183;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8185 = args[2][156 * steps + ((cycle - 0) & mask)];
assert(x8185 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8186 = x8185 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8187 = x8184 + x8186;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8188 = args[2][157 * steps + ((cycle - 0) & mask)];
assert(x8188 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8189 = x8188 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8190 = x8187 + x8189;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8191 = args[2][158 * steps + ((cycle - 0) & mask)];
assert(x8191 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8192 = x8191 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8193 = x8190 + x8192;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8194 = args[2][159 * steps + ((cycle - 0) & mask)];
assert(x8194 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8195 = x8194 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8196 = x8193 + x8195;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8197 = args[2][160 * steps + ((cycle - 0) & mask)];
assert(x8197 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8198 = x8197 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8199 = x8196 + x8198;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8200 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x8200 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8201 = x8200 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8202 = x8199 + x8201;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8203 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x8203 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8204 = x8203 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8205 = x8202 + x8204;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8206 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x8206 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8207 = x8206 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8208 = x8205 + x8207;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8209 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x8209 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8210 = x8209 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8211 = x8208 + x8210;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8212 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x8212 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8213 = x8212 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8214 = x8211 + x8213;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x8215 = x8136 - x8214;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x8216 = x8215 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":122:26)
auto x8217 = Fp(x8216.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][76 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8217);
reg = x8217;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8218 = args[2][76 * steps + ((cycle - 0) & mask)];
assert(x8218 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":123:20)
auto x8219 = x8216 - x8218;
// loc("cirgen/circuit/rv32im/sha.cpp":123:19)
auto x8220 = x8219 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":124:20)
auto x8221 = x102 - x8220;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
auto x8222 = x8220 * x8221;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
if (x8222 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:124");
// loc("cirgen/circuit/rv32im/sha.cpp":125:32)
auto x8223 = x8137 + x8216;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8224 = Fp(x8223.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8224);
reg = x8224;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8225 = Fp(x8223.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8226 = x8225 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8226);
reg = x8226;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8227 = Fp(x8223.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8228 = x8227 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8228);
reg = x8228;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8229 = Fp(x8223.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8230 = x8229 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][169 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8230);
reg = x8230;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8231 = Fp(x8223.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8232 = x8231 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][170 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8232);
reg = x8232;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8233 = Fp(x8223.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8234 = x8233 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][171 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8234);
reg = x8234;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8235 = Fp(x8223.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8236 = x8235 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][172 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8236);
reg = x8236;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8237 = Fp(x8223.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8238 = x8237 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8238);
reg = x8238;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8239 = Fp(x8223.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8240 = x8239 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][174 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8240);
reg = x8240;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8241 = Fp(x8223.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8242 = x8241 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][175 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8242);
reg = x8242;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8243 = Fp(x8223.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8244 = x8243 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8244);
reg = x8244;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8245 = Fp(x8223.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8246 = x8245 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8246);
reg = x8246;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8247 = Fp(x8223.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8248 = x8247 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8248);
reg = x8248;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8249 = Fp(x8223.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8250 = x8249 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8250);
reg = x8250;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8251 = Fp(x8223.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8252 = x8251 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8252);
reg = x8252;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8253 = Fp(x8223.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8254 = x8253 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8254);
reg = x8254;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8255 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x8255 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8256 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x8256 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8257 = x8256 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8258 = x8255 + x8257;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8259 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x8259 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8260 = x8259 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8261 = x8258 + x8260;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8262 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x8262 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8263 = x8262 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8264 = x8261 + x8263;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8265 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x8265 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8266 = x8265 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8267 = x8264 + x8266;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8268 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x8268 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8269 = x8268 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8270 = x8267 + x8269;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8271 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x8271 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8272 = x8271 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8273 = x8270 + x8272;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8274 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x8274 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8275 = x8274 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8276 = x8273 + x8275;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8277 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x8277 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8278 = x8277 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8279 = x8276 + x8278;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8280 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x8280 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8281 = x8280 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8282 = x8279 + x8281;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8283 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x8283 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8284 = x8283 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8285 = x8282 + x8284;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8286 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x8286 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8287 = x8286 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8288 = x8285 + x8287;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8289 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x8289 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8290 = x8289 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8291 = x8288 + x8290;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8292 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x8292 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8293 = x8292 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8294 = x8291 + x8293;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8295 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x8295 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8296 = x8295 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8297 = x8294 + x8296;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8298 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x8298 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8299 = x8298 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8300 = x8297 + x8299;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x8301 = x8223 - x8300;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x8302 = x8301 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":126:27)
auto x8303 = Fp(x8302.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][77 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8303);
reg = x8303;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8304 = args[2][77 * steps + ((cycle - 0) & mask)];
assert(x8304 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":127:21)
auto x8305 = x8302 - x8304;
// loc("cirgen/circuit/rv32im/sha.cpp":127:20)
auto x8306 = x8305 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":128:21)
auto x8307 = x102 - x8306;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
auto x8308 = x8306 * x8307;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
if (x8308 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:128");
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg8"("cirgen/circuit/rv32im/sha.cpp":140:11))
auto x8309 = args[2][146 * steps + ((cycle - 0) & mask)];
assert(x8309 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Reg9"("cirgen/circuit/rv32im/sha.cpp":140:26))
auto x8310 = args[2][147 * steps + ((cycle - 0) & mask)];
assert(x8310 != Fp::invalid());
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8311 = Fp(x8309.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8311);
reg = x8311;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8312 = Fp(x8309.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8313 = x8312 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8313);
reg = x8313;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8314 = Fp(x8309.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8315 = x8314 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8315);
reg = x8315;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8316 = Fp(x8309.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8317 = x8316 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8317);
reg = x8317;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8318 = Fp(x8309.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8319 = x8318 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8319);
reg = x8319;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8320 = Fp(x8309.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8321 = x8320 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8321);
reg = x8321;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8322 = Fp(x8309.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8323 = x8322 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8323);
reg = x8323;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8324 = Fp(x8309.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8325 = x8324 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8325);
reg = x8325;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8326 = Fp(x8309.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8327 = x8326 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][190 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8327);
reg = x8327;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8328 = Fp(x8309.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8329 = x8328 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][191 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8329);
reg = x8329;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8330 = Fp(x8309.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8331 = x8330 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][192 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8331);
reg = x8331;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8332 = Fp(x8309.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8333 = x8332 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][193 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8333);
reg = x8333;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8334 = Fp(x8309.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8335 = x8334 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][194 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8335);
reg = x8335;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8336 = Fp(x8309.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8337 = x8336 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][195 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8337);
reg = x8337;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8338 = Fp(x8309.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8339 = x8338 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][196 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8339);
reg = x8339;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8340 = Fp(x8309.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8341 = x8340 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][197 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8341);
reg = x8341;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8342 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x8342 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8343 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x8343 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8344 = x8343 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8345 = x8342 + x8344;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8346 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x8346 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8347 = x8346 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8348 = x8345 + x8347;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8349 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x8349 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8350 = x8349 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8351 = x8348 + x8350;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8352 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x8352 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8353 = x8352 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8354 = x8351 + x8353;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8355 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x8355 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8356 = x8355 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8357 = x8354 + x8356;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8358 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x8358 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8359 = x8358 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8360 = x8357 + x8359;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8361 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x8361 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8362 = x8361 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8363 = x8360 + x8362;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8364 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x8364 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8365 = x8364 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8366 = x8363 + x8365;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8367 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x8367 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8368 = x8367 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8369 = x8366 + x8368;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8370 = args[2][192 * steps + ((cycle - 0) & mask)];
assert(x8370 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8371 = x8370 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8372 = x8369 + x8371;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8373 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x8373 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8374 = x8373 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8375 = x8372 + x8374;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8376 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x8376 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8377 = x8376 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8378 = x8375 + x8377;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8379 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x8379 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8380 = x8379 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8381 = x8378 + x8380;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8382 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x8382 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8383 = x8382 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8384 = x8381 + x8383;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8385 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x8385 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8386 = x8385 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8387 = x8384 + x8386;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x8388 = x8309 - x8387;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x8389 = x8388 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":122:26)
auto x8390 = Fp(x8389.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][78 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8390);
reg = x8390;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8391 = args[2][78 * steps + ((cycle - 0) & mask)];
assert(x8391 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":123:20)
auto x8392 = x8389 - x8391;
// loc("cirgen/circuit/rv32im/sha.cpp":123:19)
auto x8393 = x8392 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":124:20)
auto x8394 = x102 - x8393;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
auto x8395 = x8393 * x8394;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
if (x8395 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:124");
// loc("cirgen/circuit/rv32im/sha.cpp":125:32)
auto x8396 = x8310 + x8389;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8397 = Fp(x8396.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][198 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8397);
reg = x8397;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8398 = Fp(x8396.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8399 = x8398 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][199 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8399);
reg = x8399;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8400 = Fp(x8396.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8401 = x8400 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][200 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8401);
reg = x8401;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8402 = Fp(x8396.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8403 = x8402 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][201 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8403);
reg = x8403;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8404 = Fp(x8396.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8405 = x8404 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][202 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8405);
reg = x8405;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8406 = Fp(x8396.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8407 = x8406 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][203 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8407);
reg = x8407;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8408 = Fp(x8396.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8409 = x8408 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8409);
reg = x8409;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8410 = Fp(x8396.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8411 = x8410 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8411);
reg = x8411;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8412 = Fp(x8396.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8413 = x8412 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8413);
reg = x8413;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8414 = Fp(x8396.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8415 = x8414 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8415);
reg = x8415;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8416 = Fp(x8396.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8417 = x8416 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][208 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8417);
reg = x8417;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8418 = Fp(x8396.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8419 = x8418 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][209 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8419);
reg = x8419;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8420 = Fp(x8396.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8421 = x8420 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][210 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8421);
reg = x8421;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8422 = Fp(x8396.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8423 = x8422 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][211 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8423);
reg = x8423;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8424 = Fp(x8396.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8425 = x8424 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][212 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8425);
reg = x8425;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x8426 = Fp(x8396.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x8427 = x8426 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][213 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8427);
reg = x8427;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8428 = args[2][198 * steps + ((cycle - 0) & mask)];
assert(x8428 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8429 = args[2][199 * steps + ((cycle - 0) & mask)];
assert(x8429 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8430 = x8429 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8431 = x8428 + x8430;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8432 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x8432 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8433 = x8432 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8434 = x8431 + x8433;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8435 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x8435 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8436 = x8435 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8437 = x8434 + x8436;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8438 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x8438 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8439 = x8438 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8440 = x8437 + x8439;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8441 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x8441 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8442 = x8441 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8443 = x8440 + x8442;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8444 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x8444 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8445 = x8444 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8446 = x8443 + x8445;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8447 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x8447 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8448 = x8447 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8449 = x8446 + x8448;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8450 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x8450 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8451 = x8450 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8452 = x8449 + x8451;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8453 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x8453 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8454 = x8453 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8455 = x8452 + x8454;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8456 = args[2][208 * steps + ((cycle - 0) & mask)];
assert(x8456 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8457 = x8456 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8458 = x8455 + x8457;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8459 = args[2][209 * steps + ((cycle - 0) & mask)];
assert(x8459 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8460 = x8459 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8461 = x8458 + x8460;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8462 = args[2][210 * steps + ((cycle - 0) & mask)];
assert(x8462 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8463 = x8462 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8464 = x8461 + x8463;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8465 = args[2][211 * steps + ((cycle - 0) & mask)];
assert(x8465 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8466 = x8465 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8467 = x8464 + x8466;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8468 = args[2][212 * steps + ((cycle - 0) & mask)];
assert(x8468 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8469 = x8468 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8470 = x8467 + x8469;
// loc("Top/Mux/4/Mux/10/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8471 = args[2][213 * steps + ((cycle - 0) & mask)];
assert(x8471 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x8472 = x8471 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x8473 = x8470 + x8472;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x8474 = x8396 - x8473;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x8475 = x8474 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":126:27)
auto x8476 = Fp(x8475.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8476);
reg = x8476;
}
}
// loc("Top/Mux/4/Mux/10/ShaCycle/Twit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8477 = args[2][79 * steps + ((cycle - 0) & mask)];
assert(x8477 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":127:21)
auto x8478 = x8475 - x8477;
// loc("cirgen/circuit/rv32im/sha.cpp":127:20)
auto x8479 = x8478 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":128:21)
auto x8480 = x102 - x8479;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
auto x8481 = x8479 * x8480;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
if (x8481 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:128");
}
// loc("Top/Mux/4/OneHot/Reg11"("./cirgen/components/mux.h":37:25))
auto x8482 = args[2][105 * steps + ((cycle - 0) & mask)];
assert(x8482 != Fp::invalid());
if (x8482 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8483 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x8483 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8484 = args[2][136 * steps + ((cycle - 1) & mask)];
assert(x8484 != Fp::invalid());
if (x8484 != 0) {
// loc("Top/Mux/4/OneHot/Reg10"("cirgen/circuit/rv32im/sha.cpp":339:72))
auto x8485 = args[2][104 * steps + ((cycle - 1) & mask)];
assert(x8485 != Fp::invalid());
if (x8485 != 0) {
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/sha.cpp":342:7)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13);
reg = x13;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg5"("cirgen/circuit/rv32im/sha.cpp":343:40))
auto x8486 = args[2][138 * steps + ((cycle - 1) & mask)];
assert(x8486 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":343:7)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8486);
reg = x8486;
}
}
// loc("cirgen/circuit/rv32im/sha.cpp":345:22)
auto x8487 = x102 - x8485;
if (x8487 != 0) {
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/circuit/rv32im/sha.cpp":347:7)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x84);
reg = x84;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg5"("cirgen/circuit/rv32im/sha.cpp":348:44))
auto x8488 = args[2][138 * steps + ((cycle - 1) & mask)];
assert(x8488 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":348:44)
auto x8489 = x8488 - x102;
// loc("cirgen/circuit/rv32im/sha.cpp":348:7)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8489);
reg = x8489;
}
}
}
// loc("cirgen/circuit/rv32im/sha.cpp":351:18)
auto x8490 = x102 - x8484;
if (x8490 != 0) {
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8491 = args[2][141 * steps + ((cycle - 1) & mask)];
assert(x8491 != Fp::invalid());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8491);
reg = x8491;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg4"("cirgen/circuit/rv32im/sha.cpp":354:40))
auto x8492 = args[2][135 * steps + ((cycle - 1) & mask)];
assert(x8492 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":354:40)
auto x8493 = x8492 - x102;
// loc("cirgen/circuit/rv32im/sha.cpp":354:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8493);
reg = x8493;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg5"("cirgen/circuit/rv32im/sha.cpp":355:38))
auto x8494 = args[2][138 * steps + ((cycle - 1) & mask)];
assert(x8494 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":355:5)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8494);
reg = x8494;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg4"("./cirgen/compiler/edsl/component.h":85:27))
auto x8495 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x8495 != Fp::invalid());
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x8496 = (x8495 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8496);
reg = x8496;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x8497 = inv(x8495);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8497);
reg = x8497;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8498 = args[2][136 * steps + ((cycle - 0) & mask)];
assert(x8498 != Fp::invalid());
if (x8498 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x8495 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x8499 = x102 - x8498;
if (x8499 != 0) {
// loc("Top/Mux/4/Mux/11/ShaCycle/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x8500 = args[2][137 * steps + ((cycle - 0) & mask)];
assert(x8500 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x8501 = x8495 * x8500;
// loc("cirgen/components/iszero.cpp":15:26)
auto x8502 = x8501 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x8502 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8503 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x8503 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":359:15)
auto x8504 = x102 - x8503;
if (x8498 != 0) {
if (x8504 != 0) {
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
if (x8503 != 0) {
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
}
}
if (x8499 != 0) {
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg1"("cirgen/circuit/rv32im/sha.cpp":369:38))
auto x8505 = args[2][132 * steps + ((cycle - 1) & mask)];
assert(x8505 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":369:3)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8505);
reg = x8505;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg"("cirgen/circuit/rv32im/sha.cpp":370:40))
auto x8506 = args[2][131 * steps + ((cycle - 1) & mask)];
assert(x8506 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":370:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8506);
reg = x8506;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8507 = args[2][143 * steps + ((cycle - 1) & mask)];
assert(x8507 != Fp::invalid());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][143 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8507);
reg = x8507;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg5"("./cirgen/compiler/edsl/component.h":85:27))
auto x8508 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x8508 != Fp::invalid());
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x8509 = (x8508 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8509);
reg = x8509;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x8510 = inv(x8508);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8510);
reg = x8510;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/IsZero1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8511 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x8511 != Fp::invalid());
if (x8511 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x8508 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x8512 = x102 - x8511;
if (x8512 != 0) {
// loc("Top/Mux/4/Mux/11/ShaCycle/IsZero1/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x8513 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x8513 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x8514 = x8508 * x8513;
// loc("cirgen/components/iszero.cpp":15:26)
auto x8515 = x8514 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x8515 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x8516 = x603 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x8517 = Fp(x8516.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8517);
reg = x8517;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x8518 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x8518 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x8519 = x8516 - x8518;
// loc("cirgen/components/bytes.cpp":83:10)
auto x8520 = x8519 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x8521 = Fp(x8520.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8521);
reg = x8521;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x8522 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x8522 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x8523 = x8520 - x8522;
// loc("cirgen/components/bytes.cpp":83:10)
auto x8524 = x8523 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x8525 = Fp(x8524.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8525);
reg = x8525;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x8526 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x8526 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x8527 = x8524 - x8526;
// loc("cirgen/components/bytes.cpp":83:10)
auto x8528 = x8527 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x8529 = Fp(x8528.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8529);
reg = x8529;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8530 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x8530 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x8531 = x8528 - x8530;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x8532 = x8531 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8532);
reg = x8532;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8533 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x8533 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x8534 = x102 - x8533;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x8535 = x8533 * x8534;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8535);
reg = x8535;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x8536 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x8536 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x8537 = x99 - x8533;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x8538 = x8536 * x8537;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x8538 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
host_args.at(0) = x74;
host_args.at(1) = x8503;
host_args.at(2) = x8495;
host_args.at(3) = x8508;
host(ctx, "log", "SHA_MAIN: major = %u, minor = %u, count = %u, repeat = %u", host_args.data(), 4, host_outs.data(), 0);
if (x8504 != 0) {
// loc("cirgen/circuit/rv32im/sha.cpp":381:24)
auto x8539 = x12 - x8495;
{
host_args.at(0) = x8539;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x8540 = host_outs.at(0);
auto x8541 = host_outs.at(1);
auto x8542 = host_outs.at(2);
auto x8543 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8540);
reg = x8540;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8541);
reg = x8541;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8542);
reg = x8542;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8543);
reg = x8543;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8544 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x8544 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8545 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x8545 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x8546 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x8546 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x8547 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x8547 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8539);
reg = x8539;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8483);
reg = x8483;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8544);
reg = x8544;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8545);
reg = x8545;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8546);
reg = x8546;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8547);
reg = x8547;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8548 = args[2][82 * steps + ((cycle - 2) & mask)];
assert(x8548 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8549 = args[2][83 * steps + ((cycle - 2) & mask)];
assert(x8549 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8550 = args[2][84 * steps + ((cycle - 2) & mask)];
assert(x8550 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8551 = args[2][85 * steps + ((cycle - 2) & mask)];
assert(x8551 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8552 = args[2][86 * steps + ((cycle - 2) & mask)];
assert(x8552 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8553 = args[2][87 * steps + ((cycle - 2) & mask)];
assert(x8553 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8554 = args[2][88 * steps + ((cycle - 2) & mask)];
assert(x8554 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8555 = args[2][89 * steps + ((cycle - 2) & mask)];
assert(x8555 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8556 = args[2][90 * steps + ((cycle - 2) & mask)];
assert(x8556 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8557 = args[2][91 * steps + ((cycle - 2) & mask)];
assert(x8557 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8558 = args[2][19 * steps + ((cycle - 2) & mask)];
assert(x8558 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8559 = args[2][20 * steps + ((cycle - 2) & mask)];
assert(x8559 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8560 = args[2][21 * steps + ((cycle - 2) & mask)];
assert(x8560 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8561 = args[2][22 * steps + ((cycle - 2) & mask)];
assert(x8561 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8562 = args[2][23 * steps + ((cycle - 2) & mask)];
assert(x8562 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8563 = args[2][24 * steps + ((cycle - 2) & mask)];
assert(x8563 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8564 = args[2][25 * steps + ((cycle - 2) & mask)];
assert(x8564 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8565 = args[2][26 * steps + ((cycle - 2) & mask)];
assert(x8565 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8566 = args[2][27 * steps + ((cycle - 2) & mask)];
assert(x8566 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8567 = args[2][28 * steps + ((cycle - 2) & mask)];
assert(x8567 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8568 = args[2][29 * steps + ((cycle - 2) & mask)];
assert(x8568 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8569 = args[2][30 * steps + ((cycle - 2) & mask)];
assert(x8569 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8570 = args[2][31 * steps + ((cycle - 2) & mask)];
assert(x8570 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8571 = args[2][32 * steps + ((cycle - 2) & mask)];
assert(x8571 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8572 = args[2][33 * steps + ((cycle - 2) & mask)];
assert(x8572 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8573 = args[2][34 * steps + ((cycle - 2) & mask)];
assert(x8573 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8574 = args[2][35 * steps + ((cycle - 2) & mask)];
assert(x8574 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8575 = args[2][36 * steps + ((cycle - 2) & mask)];
assert(x8575 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8576 = args[2][37 * steps + ((cycle - 2) & mask)];
assert(x8576 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8577 = args[2][38 * steps + ((cycle - 2) & mask)];
assert(x8577 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8578 = args[2][39 * steps + ((cycle - 2) & mask)];
assert(x8578 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8579 = args[2][40 * steps + ((cycle - 2) & mask)];
assert(x8579 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8580 = args[2][82 * steps + ((cycle - 7) & mask)];
assert(x8580 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8581 = args[2][83 * steps + ((cycle - 7) & mask)];
assert(x8581 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8582 = args[2][84 * steps + ((cycle - 7) & mask)];
assert(x8582 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8583 = args[2][85 * steps + ((cycle - 7) & mask)];
assert(x8583 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8584 = args[2][86 * steps + ((cycle - 7) & mask)];
assert(x8584 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8585 = args[2][87 * steps + ((cycle - 7) & mask)];
assert(x8585 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8586 = args[2][88 * steps + ((cycle - 7) & mask)];
assert(x8586 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8587 = args[2][89 * steps + ((cycle - 7) & mask)];
assert(x8587 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8588 = args[2][90 * steps + ((cycle - 7) & mask)];
assert(x8588 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8589 = args[2][91 * steps + ((cycle - 7) & mask)];
assert(x8589 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8590 = args[2][19 * steps + ((cycle - 7) & mask)];
assert(x8590 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8591 = args[2][20 * steps + ((cycle - 7) & mask)];
assert(x8591 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8592 = args[2][21 * steps + ((cycle - 7) & mask)];
assert(x8592 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8593 = args[2][22 * steps + ((cycle - 7) & mask)];
assert(x8593 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8594 = args[2][23 * steps + ((cycle - 7) & mask)];
assert(x8594 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8595 = args[2][24 * steps + ((cycle - 7) & mask)];
assert(x8595 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8596 = args[2][25 * steps + ((cycle - 7) & mask)];
assert(x8596 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8597 = args[2][26 * steps + ((cycle - 7) & mask)];
assert(x8597 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8598 = args[2][27 * steps + ((cycle - 7) & mask)];
assert(x8598 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8599 = args[2][28 * steps + ((cycle - 7) & mask)];
assert(x8599 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8600 = args[2][29 * steps + ((cycle - 7) & mask)];
assert(x8600 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8601 = args[2][30 * steps + ((cycle - 7) & mask)];
assert(x8601 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8602 = args[2][31 * steps + ((cycle - 7) & mask)];
assert(x8602 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8603 = args[2][32 * steps + ((cycle - 7) & mask)];
assert(x8603 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8604 = args[2][33 * steps + ((cycle - 7) & mask)];
assert(x8604 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8605 = args[2][34 * steps + ((cycle - 7) & mask)];
assert(x8605 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8606 = args[2][35 * steps + ((cycle - 7) & mask)];
assert(x8606 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8607 = args[2][36 * steps + ((cycle - 7) & mask)];
assert(x8607 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8608 = args[2][37 * steps + ((cycle - 7) & mask)];
assert(x8608 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8609 = args[2][38 * steps + ((cycle - 7) & mask)];
assert(x8609 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8610 = args[2][39 * steps + ((cycle - 7) & mask)];
assert(x8610 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8611 = args[2][40 * steps + ((cycle - 7) & mask)];
assert(x8611 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8612 = args[2][82 * steps + ((cycle - 15) & mask)];
assert(x8612 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8613 = args[2][83 * steps + ((cycle - 15) & mask)];
assert(x8613 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8614 = args[2][84 * steps + ((cycle - 15) & mask)];
assert(x8614 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8615 = args[2][85 * steps + ((cycle - 15) & mask)];
assert(x8615 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8616 = args[2][86 * steps + ((cycle - 15) & mask)];
assert(x8616 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8617 = args[2][87 * steps + ((cycle - 15) & mask)];
assert(x8617 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8618 = args[2][88 * steps + ((cycle - 15) & mask)];
assert(x8618 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8619 = args[2][89 * steps + ((cycle - 15) & mask)];
assert(x8619 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8620 = args[2][90 * steps + ((cycle - 15) & mask)];
assert(x8620 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8621 = args[2][91 * steps + ((cycle - 15) & mask)];
assert(x8621 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8622 = args[2][19 * steps + ((cycle - 15) & mask)];
assert(x8622 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8623 = args[2][20 * steps + ((cycle - 15) & mask)];
assert(x8623 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8624 = args[2][21 * steps + ((cycle - 15) & mask)];
assert(x8624 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8625 = args[2][22 * steps + ((cycle - 15) & mask)];
assert(x8625 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8626 = args[2][23 * steps + ((cycle - 15) & mask)];
assert(x8626 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8627 = args[2][24 * steps + ((cycle - 15) & mask)];
assert(x8627 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8628 = args[2][25 * steps + ((cycle - 15) & mask)];
assert(x8628 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8629 = args[2][26 * steps + ((cycle - 15) & mask)];
assert(x8629 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8630 = args[2][27 * steps + ((cycle - 15) & mask)];
assert(x8630 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8631 = args[2][28 * steps + ((cycle - 15) & mask)];
assert(x8631 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8632 = args[2][29 * steps + ((cycle - 15) & mask)];
assert(x8632 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8633 = args[2][30 * steps + ((cycle - 15) & mask)];
assert(x8633 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8634 = args[2][31 * steps + ((cycle - 15) & mask)];
assert(x8634 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8635 = args[2][32 * steps + ((cycle - 15) & mask)];
assert(x8635 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8636 = args[2][33 * steps + ((cycle - 15) & mask)];
assert(x8636 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8637 = args[2][34 * steps + ((cycle - 15) & mask)];
assert(x8637 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8638 = args[2][35 * steps + ((cycle - 15) & mask)];
assert(x8638 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8639 = args[2][36 * steps + ((cycle - 15) & mask)];
assert(x8639 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8640 = args[2][37 * steps + ((cycle - 15) & mask)];
assert(x8640 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8641 = args[2][38 * steps + ((cycle - 15) & mask)];
assert(x8641 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8642 = args[2][39 * steps + ((cycle - 15) & mask)];
assert(x8642 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8643 = args[2][40 * steps + ((cycle - 15) & mask)];
assert(x8643 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8644 = args[2][82 * steps + ((cycle - 16) & mask)];
assert(x8644 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8645 = args[2][83 * steps + ((cycle - 16) & mask)];
assert(x8645 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8646 = args[2][84 * steps + ((cycle - 16) & mask)];
assert(x8646 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8647 = args[2][85 * steps + ((cycle - 16) & mask)];
assert(x8647 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8648 = args[2][86 * steps + ((cycle - 16) & mask)];
assert(x8648 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8649 = args[2][87 * steps + ((cycle - 16) & mask)];
assert(x8649 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8650 = args[2][88 * steps + ((cycle - 16) & mask)];
assert(x8650 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8651 = args[2][89 * steps + ((cycle - 16) & mask)];
assert(x8651 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8652 = args[2][90 * steps + ((cycle - 16) & mask)];
assert(x8652 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8653 = args[2][91 * steps + ((cycle - 16) & mask)];
assert(x8653 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8654 = args[2][19 * steps + ((cycle - 16) & mask)];
assert(x8654 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8655 = args[2][20 * steps + ((cycle - 16) & mask)];
assert(x8655 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8656 = args[2][21 * steps + ((cycle - 16) & mask)];
assert(x8656 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8657 = args[2][22 * steps + ((cycle - 16) & mask)];
assert(x8657 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8658 = args[2][23 * steps + ((cycle - 16) & mask)];
assert(x8658 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8659 = args[2][24 * steps + ((cycle - 16) & mask)];
assert(x8659 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8660 = args[2][25 * steps + ((cycle - 16) & mask)];
assert(x8660 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8661 = args[2][26 * steps + ((cycle - 16) & mask)];
assert(x8661 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8662 = args[2][27 * steps + ((cycle - 16) & mask)];
assert(x8662 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8663 = args[2][28 * steps + ((cycle - 16) & mask)];
assert(x8663 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8664 = args[2][29 * steps + ((cycle - 16) & mask)];
assert(x8664 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8665 = args[2][30 * steps + ((cycle - 16) & mask)];
assert(x8665 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8666 = args[2][31 * steps + ((cycle - 16) & mask)];
assert(x8666 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8667 = args[2][32 * steps + ((cycle - 16) & mask)];
assert(x8667 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8668 = args[2][33 * steps + ((cycle - 16) & mask)];
assert(x8668 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8669 = args[2][34 * steps + ((cycle - 16) & mask)];
assert(x8669 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8670 = args[2][35 * steps + ((cycle - 16) & mask)];
assert(x8670 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8671 = args[2][36 * steps + ((cycle - 16) & mask)];
assert(x8671 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8672 = args[2][37 * steps + ((cycle - 16) & mask)];
assert(x8672 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8673 = args[2][38 * steps + ((cycle - 16) & mask)];
assert(x8673 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x8674 = args[2][39 * steps + ((cycle - 16) & mask)];
assert(x8674 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x8675 = args[2][40 * steps + ((cycle - 16) & mask)];
assert(x8675 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8676 = x8630 + x8615;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8677 = x8630 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8678 = x8677 * x8615;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8679 = x8676 - x8678;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8680 = x8631 + x8616;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8681 = x8631 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8682 = x8681 * x8616;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8683 = x8680 - x8682;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8684 = x8632 + x8617;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8685 = x8632 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8686 = x8685 * x8617;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8687 = x8684 - x8686;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8688 = x8633 + x8618;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8689 = x8633 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8690 = x8689 * x8618;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8691 = x8688 - x8690;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8692 = x8634 + x8619;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8693 = x8634 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8694 = x8693 * x8619;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8695 = x8692 - x8694;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8696 = x8635 + x8620;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8697 = x8635 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8698 = x8697 * x8620;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8699 = x8696 - x8698;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8700 = x8636 + x8621;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8701 = x8636 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8702 = x8701 * x8621;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8703 = x8700 - x8702;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8704 = x8637 + x8622;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8705 = x8637 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8706 = x8705 * x8622;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8707 = x8704 - x8706;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8708 = x8638 + x8623;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8709 = x8638 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8710 = x8709 * x8623;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8711 = x8708 - x8710;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8712 = x8639 + x8624;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8713 = x8639 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8714 = x8713 * x8624;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8715 = x8712 - x8714;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8716 = x8640 + x8625;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8717 = x8640 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8718 = x8717 * x8625;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8719 = x8716 - x8718;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8720 = x8641 + x8626;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8721 = x8641 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8722 = x8721 * x8626;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8723 = x8720 - x8722;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8724 = x8642 + x8627;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8725 = x8642 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8726 = x8725 * x8627;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8727 = x8724 - x8726;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8728 = x8643 + x8628;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8729 = x8643 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8730 = x8729 * x8628;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8731 = x8728 - x8730;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8732 = x8612 + x8629;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8733 = x8612 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8734 = x8733 * x8629;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8735 = x8732 - x8734;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8736 = x8613 + x8630;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8737 = x8613 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8738 = x8737 * x8630;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8739 = x8736 - x8738;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8740 = x8614 + x8631;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8741 = x8614 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8742 = x8741 * x8631;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8743 = x8740 - x8742;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8744 = x8615 + x8632;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8745 = x8615 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8746 = x8745 * x8632;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8747 = x8744 - x8746;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8748 = x8616 + x8633;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8749 = x8616 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8750 = x8749 * x8633;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8751 = x8748 - x8750;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8752 = x8617 + x8634;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8753 = x8617 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8754 = x8753 * x8634;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8755 = x8752 - x8754;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8756 = x8618 + x8635;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8757 = x8618 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8758 = x8757 * x8635;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8759 = x8756 - x8758;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8760 = x8619 + x8636;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8761 = x8619 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8762 = x8761 * x8636;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8763 = x8760 - x8762;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8764 = x8620 + x8637;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8765 = x8620 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8766 = x8765 * x8637;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8767 = x8764 - x8766;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8768 = x8621 + x8638;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8769 = x8621 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8770 = x8769 * x8638;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8771 = x8768 - x8770;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8772 = x8622 + x8639;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8773 = x8622 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8774 = x8773 * x8639;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8775 = x8772 - x8774;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8776 = x8623 + x8640;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8777 = x8623 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8778 = x8777 * x8640;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8779 = x8776 - x8778;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8780 = x8624 + x8641;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8781 = x8624 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8782 = x8781 * x8641;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8783 = x8780 - x8782;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8784 = x8625 + x8642;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8785 = x8625 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8786 = x8785 * x8642;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8787 = x8784 - x8786;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8788 = x8626 + x8643;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8789 = x8626 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8790 = x8789 * x8643;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8791 = x8788 - x8790;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8792 = x8619 + x8679;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8793 = x8761 * x8679;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8794 = x8792 - x8793;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8795 = x8620 + x8683;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8796 = x8765 * x8683;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8797 = x8795 - x8796;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8798 = x8621 + x8687;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8799 = x8769 * x8687;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8800 = x8798 - x8799;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8801 = x8622 + x8691;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8802 = x8773 * x8691;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8803 = x8801 - x8802;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8804 = x8623 + x8695;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8805 = x8777 * x8695;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8806 = x8804 - x8805;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8807 = x8624 + x8699;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8808 = x8781 * x8699;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8809 = x8807 - x8808;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8810 = x8625 + x8703;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8811 = x8785 * x8703;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8812 = x8810 - x8811;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8813 = x8626 + x8707;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8814 = x8789 * x8707;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8815 = x8813 - x8814;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8816 = x8627 + x8711;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8817 = x8627 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8818 = x8817 * x8711;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8819 = x8816 - x8818;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8820 = x8628 + x8715;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8821 = x8628 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8822 = x8821 * x8715;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8823 = x8820 - x8822;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8824 = x8629 + x8719;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8825 = x8629 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8826 = x8825 * x8719;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8827 = x8824 - x8826;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8828 = x8630 + x8723;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8829 = x8677 * x8723;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8830 = x8828 - x8829;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8831 = x8631 + x8727;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8832 = x8681 * x8727;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8833 = x8831 - x8832;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8834 = x8632 + x8731;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8835 = x8685 * x8731;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8836 = x8834 - x8835;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8837 = x8633 + x8735;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8838 = x8689 * x8735;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8839 = x8837 - x8838;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8840 = x8634 + x8739;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8841 = x8693 * x8739;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8842 = x8840 - x8841;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8843 = x8635 + x8743;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8844 = x8697 * x8743;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8845 = x8843 - x8844;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8846 = x8636 + x8747;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8847 = x8701 * x8747;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8848 = x8846 - x8847;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8849 = x8637 + x8751;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8850 = x8705 * x8751;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8851 = x8849 - x8850;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8852 = x8638 + x8755;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8853 = x8709 * x8755;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8854 = x8852 - x8853;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8855 = x8639 + x8759;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8856 = x8713 * x8759;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8857 = x8855 - x8856;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8858 = x8640 + x8763;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8859 = x8717 * x8763;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8860 = x8858 - x8859;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8861 = x8641 + x8767;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8862 = x8721 * x8767;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8863 = x8861 - x8862;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8864 = x8642 + x8771;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8865 = x8725 * x8771;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8866 = x8864 - x8865;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8867 = x8643 + x8775;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8868 = x8729 * x8775;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8869 = x8867 - x8868;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8870 = x8612 + x8779;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8871 = x8733 * x8779;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8872 = x8870 - x8871;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8873 = x8613 + x8783;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8874 = x8737 * x8783;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8875 = x8873 - x8874;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8876 = x8614 + x8787;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8877 = x8741 * x8787;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8878 = x8876 - x8877;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8879 = x8615 + x8791;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8880 = x8745 * x8791;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8881 = x8879 - x8880;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8882 = x8616 + x8627;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8883 = x8749 * x8627;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8884 = x8882 - x8883;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8885 = x8617 + x8628;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8886 = x8753 * x8628;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8887 = x8885 - x8886;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8888 = x8618 + x8629;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8889 = x8757 * x8629;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8890 = x8888 - x8889;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8891 = x8567 + x8558;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8892 = x8567 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8893 = x8892 * x8558;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8894 = x8891 - x8893;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8895 = x8568 + x8559;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8896 = x8568 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8897 = x8896 * x8559;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8898 = x8895 - x8897;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8899 = x8569 + x8560;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8900 = x8569 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8901 = x8900 * x8560;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8902 = x8899 - x8901;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8903 = x8570 + x8561;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8904 = x8570 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8905 = x8904 * x8561;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8906 = x8903 - x8905;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8907 = x8571 + x8562;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8908 = x8571 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8909 = x8908 * x8562;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8910 = x8907 - x8909;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8911 = x8572 + x8563;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8912 = x8572 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8913 = x8912 * x8563;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8914 = x8911 - x8913;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8915 = x8573 + x8564;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8916 = x8573 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8917 = x8916 * x8564;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8918 = x8915 - x8917;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8919 = x8574 + x8565;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8920 = x8574 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8921 = x8920 * x8565;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8922 = x8919 - x8921;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8923 = x8575 + x8566;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8924 = x8575 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8925 = x8924 * x8566;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8926 = x8923 - x8925;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8927 = x8576 + x8567;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8928 = x8576 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8929 = x8928 * x8567;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8930 = x8927 - x8929;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8931 = x8577 + x8568;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8932 = x8577 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8933 = x8932 * x8568;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8934 = x8931 - x8933;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8935 = x8578 + x8569;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8936 = x8578 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8937 = x8936 * x8569;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8938 = x8935 - x8937;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8939 = x8579 + x8570;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8940 = x8579 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8941 = x8940 * x8570;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8942 = x8939 - x8941;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8943 = x8548 + x8571;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8944 = x8548 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8945 = x8944 * x8571;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8946 = x8943 - x8945;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8947 = x8549 + x8572;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8948 = x8549 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8949 = x8948 * x8572;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8950 = x8947 - x8949;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8951 = x8550 + x8573;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8952 = x8550 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8953 = x8952 * x8573;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8954 = x8951 - x8953;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8955 = x8551 + x8574;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8956 = x8551 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8957 = x8956 * x8574;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8958 = x8955 - x8957;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8959 = x8552 + x8575;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8960 = x8552 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8961 = x8960 * x8575;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8962 = x8959 - x8961;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8963 = x8553 + x8576;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8964 = x8553 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8965 = x8964 * x8576;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8966 = x8963 - x8965;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8967 = x8554 + x8577;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8968 = x8554 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8969 = x8968 * x8577;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8970 = x8967 - x8969;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8971 = x8555 + x8578;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8972 = x8555 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8973 = x8972 * x8578;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8974 = x8971 - x8973;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8975 = x8556 + x8579;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8976 = x8556 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8977 = x8976 * x8579;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8978 = x8975 - x8977;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8979 = x8565 + x8894;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8980 = x8565 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8981 = x8980 * x8894;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8982 = x8979 - x8981;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8983 = x8566 + x8898;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8984 = x8566 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8985 = x8984 * x8898;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8986 = x8983 - x8985;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8987 = x8567 + x8902;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8988 = x8892 * x8902;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8989 = x8987 - x8988;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8990 = x8568 + x8906;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8991 = x8896 * x8906;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8992 = x8990 - x8991;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8993 = x8569 + x8910;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8994 = x8900 * x8910;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8995 = x8993 - x8994;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8996 = x8570 + x8914;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x8997 = x8904 * x8914;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8998 = x8996 - x8997;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x8999 = x8571 + x8918;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9000 = x8908 * x8918;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9001 = x8999 - x9000;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9002 = x8572 + x8922;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9003 = x8912 * x8922;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9004 = x9002 - x9003;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9005 = x8573 + x8926;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9006 = x8916 * x8926;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9007 = x9005 - x9006;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9008 = x8574 + x8930;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9009 = x8920 * x8930;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9010 = x9008 - x9009;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9011 = x8575 + x8934;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9012 = x8924 * x8934;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9013 = x9011 - x9012;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9014 = x8576 + x8938;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9015 = x8928 * x8938;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9016 = x9014 - x9015;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9017 = x8577 + x8942;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9018 = x8932 * x8942;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9019 = x9017 - x9018;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9020 = x8578 + x8946;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9021 = x8936 * x8946;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9022 = x9020 - x9021;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9023 = x8579 + x8950;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9024 = x8940 * x8950;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9025 = x9023 - x9024;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9026 = x8548 + x8954;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9027 = x8944 * x8954;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9028 = x9026 - x9027;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9029 = x8549 + x8958;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9030 = x8948 * x8958;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9031 = x9029 - x9030;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9032 = x8550 + x8962;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9033 = x8952 * x8962;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9034 = x9032 - x9033;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9035 = x8551 + x8966;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9036 = x8956 * x8966;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9037 = x9035 - x9036;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9038 = x8552 + x8970;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9039 = x8960 * x8970;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9040 = x9038 - x9039;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9041 = x8553 + x8974;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9042 = x8964 * x8974;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9043 = x9041 - x9042;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9044 = x8554 + x8978;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9045 = x8968 * x8978;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9046 = x9044 - x9045;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9047 = x8555 + x8557;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9048 = x8972 * x8557;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9049 = x9047 - x9048;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9050 = x8556 + x8558;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9051 = x8976 * x8558;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9052 = x9050 - x9051;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9053 = x8557 + x8559;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9054 = x8557 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9055 = x9054 * x8559;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9056 = x9053 - x9055;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9057 = x8558 + x8560;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9058 = x8558 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9059 = x9058 * x8560;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9060 = x9057 - x9059;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9061 = x8559 + x8561;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9062 = x8559 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9063 = x9062 * x8561;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9064 = x9061 - x9063;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9065 = x8560 + x8562;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9066 = x8560 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9067 = x9066 * x8562;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9068 = x9065 - x9067;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9069 = x8561 + x8563;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9070 = x8561 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9071 = x9070 * x8563;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9072 = x9069 - x9071;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9073 = x8562 + x8564;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9074 = x8562 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9075 = x9074 * x8564;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9076 = x9073 - x9075;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9077 = x8563 + x8565;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9078 = x8563 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9079 = x9078 * x8565;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9080 = x9077 - x9079;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9081 = x8564 + x8566;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9082 = x8564 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x9083 = x9082 * x8566;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x9084 = x9081 - x9083;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9085 = x8645 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9086 = x8644 + x9085;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9087 = x8646 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9088 = x9086 + x9087;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9089 = x8647 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9090 = x9088 + x9089;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9091 = x8648 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9092 = x9090 + x9091;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9093 = x8649 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9094 = x9092 + x9093;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9095 = x8650 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9096 = x9094 + x9095;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9097 = x8651 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9098 = x9096 + x9097;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9099 = x8652 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9100 = x9098 + x9099;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9101 = x8653 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9102 = x9100 + x9101;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9103 = x8654 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9104 = x9102 + x9103;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9105 = x8655 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9106 = x9104 + x9105;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9107 = x8656 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9108 = x9106 + x9107;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9109 = x8657 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9110 = x9108 + x9109;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9111 = x8658 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9112 = x9110 + x9111;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9113 = x8659 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9114 = x9112 + x9113;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9115 = x8661 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9116 = x8660 + x9115;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9117 = x8662 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9118 = x9116 + x9117;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9119 = x8663 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9120 = x9118 + x9119;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9121 = x8664 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9122 = x9120 + x9121;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9123 = x8665 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9124 = x9122 + x9123;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9125 = x8666 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9126 = x9124 + x9125;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9127 = x8667 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9128 = x9126 + x9127;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9129 = x8668 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9130 = x9128 + x9129;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9131 = x8669 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9132 = x9130 + x9131;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9133 = x8670 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9134 = x9132 + x9133;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9135 = x8671 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9136 = x9134 + x9135;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9137 = x8672 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9138 = x9136 + x9137;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9139 = x8673 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9140 = x9138 + x9139;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9141 = x8674 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9142 = x9140 + x9141;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9143 = x8675 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9144 = x9142 + x9143;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9145 = x8797 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9146 = x8794 + x9145;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9147 = x8800 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9148 = x9146 + x9147;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9149 = x8803 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9150 = x9148 + x9149;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9151 = x8806 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9152 = x9150 + x9151;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9153 = x8809 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9154 = x9152 + x9153;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9155 = x8812 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9156 = x9154 + x9155;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9157 = x8815 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9158 = x9156 + x9157;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9159 = x8819 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9160 = x9158 + x9159;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9161 = x8823 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9162 = x9160 + x9161;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9163 = x8827 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9164 = x9162 + x9163;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9165 = x8830 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9166 = x9164 + x9165;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9167 = x8833 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9168 = x9166 + x9167;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9169 = x8836 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9170 = x9168 + x9169;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9171 = x8839 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9172 = x9170 + x9171;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9173 = x8842 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9174 = x9172 + x9173;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9175 = x8848 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9176 = x8845 + x9175;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9177 = x8851 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9178 = x9176 + x9177;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9179 = x8854 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9180 = x9178 + x9179;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9181 = x8857 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9182 = x9180 + x9181;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9183 = x8860 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9184 = x9182 + x9183;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9185 = x8863 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9186 = x9184 + x9185;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9187 = x8866 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9188 = x9186 + x9187;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9189 = x8869 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9190 = x9188 + x9189;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9191 = x8872 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9192 = x9190 + x9191;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9193 = x8875 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9194 = x9192 + x9193;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9195 = x8878 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9196 = x9194 + x9195;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9197 = x8881 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9198 = x9196 + x9197;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9199 = x8884 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9200 = x9198 + x9199;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9201 = x8887 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9202 = x9200 + x9201;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9203 = x8890 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9204 = x9202 + x9203;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9205 = x8581 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9206 = x8580 + x9205;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9207 = x8582 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9208 = x9206 + x9207;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9209 = x8583 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9210 = x9208 + x9209;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9211 = x8584 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9212 = x9210 + x9211;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9213 = x8585 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9214 = x9212 + x9213;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9215 = x8586 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9216 = x9214 + x9215;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9217 = x8587 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9218 = x9216 + x9217;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9219 = x8588 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9220 = x9218 + x9219;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9221 = x8589 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9222 = x9220 + x9221;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9223 = x8590 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9224 = x9222 + x9223;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9225 = x8591 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9226 = x9224 + x9225;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9227 = x8592 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9228 = x9226 + x9227;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9229 = x8593 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9230 = x9228 + x9229;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9231 = x8594 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9232 = x9230 + x9231;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9233 = x8595 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9234 = x9232 + x9233;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9235 = x8597 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9236 = x8596 + x9235;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9237 = x8598 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9238 = x9236 + x9237;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9239 = x8599 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9240 = x9238 + x9239;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9241 = x8600 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9242 = x9240 + x9241;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9243 = x8601 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9244 = x9242 + x9243;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9245 = x8602 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9246 = x9244 + x9245;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9247 = x8603 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9248 = x9246 + x9247;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9249 = x8604 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9250 = x9248 + x9249;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9251 = x8605 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9252 = x9250 + x9251;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9253 = x8606 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9254 = x9252 + x9253;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9255 = x8607 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9256 = x9254 + x9255;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9257 = x8608 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9258 = x9256 + x9257;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9259 = x8609 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9260 = x9258 + x9259;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9261 = x8610 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9262 = x9260 + x9261;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9263 = x8611 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9264 = x9262 + x9263;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9265 = x8986 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9266 = x8982 + x9265;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9267 = x8989 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9268 = x9266 + x9267;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9269 = x8992 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9270 = x9268 + x9269;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9271 = x8995 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9272 = x9270 + x9271;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9273 = x8998 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9274 = x9272 + x9273;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9275 = x9001 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9276 = x9274 + x9275;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9277 = x9004 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9278 = x9276 + x9277;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9279 = x9007 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9280 = x9278 + x9279;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9281 = x9010 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9282 = x9280 + x9281;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9283 = x9013 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9284 = x9282 + x9283;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9285 = x9016 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9286 = x9284 + x9285;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9287 = x9019 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9288 = x9286 + x9287;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9289 = x9022 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9290 = x9288 + x9289;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9291 = x9025 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9292 = x9290 + x9291;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9293 = x9028 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9294 = x9292 + x9293;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9295 = x9034 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9296 = x9031 + x9295;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9297 = x9037 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9298 = x9296 + x9297;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9299 = x9040 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9300 = x9298 + x9299;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9301 = x9043 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9302 = x9300 + x9301;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9303 = x9046 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9304 = x9302 + x9303;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9305 = x9049 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9306 = x9304 + x9305;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9307 = x9052 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9308 = x9306 + x9307;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9309 = x9056 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9310 = x9308 + x9309;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9311 = x9060 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9312 = x9310 + x9311;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9313 = x9064 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9314 = x9312 + x9313;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9315 = x9068 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9316 = x9314 + x9315;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9317 = x9072 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9318 = x9316 + x9317;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9319 = x9076 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9320 = x9318 + x9319;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9321 = x9080 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9322 = x9320 + x9321;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9323 = x9084 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9324 = x9322 + x9323;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x9325 = x9234 + x9294;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x9326 = x9264 + x9324;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x9327 = x9174 + x9325;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x9328 = x9204 + x9326;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x9329 = x9114 + x9327;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x9330 = x9144 + x9328;
// loc("cirgen/circuit/rv32im/sha.cpp":457:5)
{
auto& reg = args[2][148 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9329);
reg = x9329;
}
// loc("cirgen/circuit/rv32im/sha.cpp":457:5)
{
auto& reg = args[2][149 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9330);
reg = x9330;
}
if (x8503 != 0) {
{
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][19 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][20 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][21 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][22 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][23 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][24 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9331 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x9331 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9332 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x9332 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9333 = x9332 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9334 = x9331 + x9333;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9335 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x9335 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9336 = x9335 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9337 = x9334 + x9336;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9338 = args[2][85 * steps + ((cycle - 0) & mask)];
assert(x9338 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9339 = x9338 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9340 = x9337 + x9339;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9341 = args[2][86 * steps + ((cycle - 0) & mask)];
assert(x9341 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9342 = x9341 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9343 = x9340 + x9342;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9344 = args[2][87 * steps + ((cycle - 0) & mask)];
assert(x9344 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9345 = x9344 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9346 = x9343 + x9345;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9347 = args[2][88 * steps + ((cycle - 0) & mask)];
assert(x9347 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9348 = x9347 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9349 = x9346 + x9348;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9350 = args[2][89 * steps + ((cycle - 0) & mask)];
assert(x9350 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9351 = x9350 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9352 = x9349 + x9351;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9353 = args[2][90 * steps + ((cycle - 0) & mask)];
assert(x9353 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9354 = x9353 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9355 = x9352 + x9354;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9356 = args[2][91 * steps + ((cycle - 0) & mask)];
assert(x9356 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9357 = x9356 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9358 = x9355 + x9357;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9359 = args[2][19 * steps + ((cycle - 0) & mask)];
assert(x9359 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9360 = x9359 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9361 = x9358 + x9360;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9362 = args[2][20 * steps + ((cycle - 0) & mask)];
assert(x9362 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9363 = x9362 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9364 = x9361 + x9363;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9365 = args[2][21 * steps + ((cycle - 0) & mask)];
assert(x9365 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9366 = x9365 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9367 = x9364 + x9366;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9368 = args[2][22 * steps + ((cycle - 0) & mask)];
assert(x9368 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9369 = x9368 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9370 = x9367 + x9369;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9371 = args[2][23 * steps + ((cycle - 0) & mask)];
assert(x9371 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9372 = x9371 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9373 = x9370 + x9372;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9374 = args[2][24 * steps + ((cycle - 0) & mask)];
assert(x9374 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9375 = x9374 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9376 = x9373 + x9375;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x9377 = x101 - x9376;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x9378 = x9377 * x16;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9378);
reg = x9378;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9379 = args[2][80 * steps + ((cycle - 0) & mask)];
assert(x9379 != Fp::invalid());
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9380 = Fp(x9379.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9380);
reg = x9380;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9381 = Fp(x9379.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9382 = x9381 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9382);
reg = x9382;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9383 = Fp(x9379.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9384 = x9383 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9384);
reg = x9384;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9385 = Fp(x9379.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9386 = x9385 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9386);
reg = x9386;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9387 = Fp(x9379.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9388 = x9387 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9388);
reg = x9388;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9389 = Fp(x9379.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9390 = x9389 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9390);
reg = x9390;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9391 = Fp(x9379.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9392 = x9391 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9392);
reg = x9392;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9393 = Fp(x9379.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9394 = x9393 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9394);
reg = x9394;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9395 = Fp(x9379.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9396 = x9395 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9396);
reg = x9396;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9397 = Fp(x9379.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9398 = x9397 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9398);
reg = x9398;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9399 = Fp(x9379.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9400 = x9399 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9400);
reg = x9400;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9401 = Fp(x9379.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9402 = x9401 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9402);
reg = x9402;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9403 = Fp(x9379.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9404 = x9403 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9404);
reg = x9404;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9405 = Fp(x9379.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9406 = x9405 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9406);
reg = x9406;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9407 = Fp(x9379.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9408 = x9407 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9408);
reg = x9408;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9409 = Fp(x9379.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9410 = x9409 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9410);
reg = x9410;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9411 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x9411 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9412 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x9412 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9413 = x9412 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9414 = x9411 + x9413;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9415 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x9415 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9416 = x9415 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9417 = x9414 + x9416;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9418 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x9418 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9419 = x9418 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9420 = x9417 + x9419;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9421 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x9421 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9422 = x9421 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9423 = x9420 + x9422;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9424 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x9424 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9425 = x9424 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9426 = x9423 + x9425;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9427 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x9427 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9428 = x9427 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9429 = x9426 + x9428;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9430 = args[2][32 * steps + ((cycle - 0) & mask)];
assert(x9430 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9431 = x9430 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9432 = x9429 + x9431;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9433 = args[2][33 * steps + ((cycle - 0) & mask)];
assert(x9433 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9434 = x9433 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9435 = x9432 + x9434;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9436 = args[2][34 * steps + ((cycle - 0) & mask)];
assert(x9436 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9437 = x9436 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9438 = x9435 + x9437;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9439 = args[2][35 * steps + ((cycle - 0) & mask)];
assert(x9439 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9440 = x9439 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9441 = x9438 + x9440;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9442 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x9442 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9443 = x9442 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9444 = x9441 + x9443;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9445 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x9445 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9446 = x9445 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9447 = x9444 + x9446;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9448 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x9448 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9449 = x9448 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9450 = x9447 + x9449;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9451 = args[2][39 * steps + ((cycle - 0) & mask)];
assert(x9451 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9452 = x9451 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9453 = x9450 + x9452;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9454 = args[2][40 * steps + ((cycle - 0) & mask)];
assert(x9454 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9455 = x9454 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9456 = x9453 + x9455;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x9457 = x9379 - x9456;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x9458 = x9457 * x16;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9458);
reg = x9458;
}
}
if (x8504 != 0) {
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg10"("cirgen/circuit/rv32im/sha.cpp":140:11))
auto x9459 = args[2][148 * steps + ((cycle - 0) & mask)];
assert(x9459 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg11"("cirgen/circuit/rv32im/sha.cpp":140:26))
auto x9460 = args[2][149 * steps + ((cycle - 0) & mask)];
assert(x9460 != Fp::invalid());
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9461 = Fp(x9459.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9461);
reg = x9461;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9462 = Fp(x9459.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9463 = x9462 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9463);
reg = x9463;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9464 = Fp(x9459.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9465 = x9464 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9465);
reg = x9465;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9466 = Fp(x9459.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9467 = x9466 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9467);
reg = x9467;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9468 = Fp(x9459.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9469 = x9468 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9469);
reg = x9469;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9470 = Fp(x9459.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9471 = x9470 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9471);
reg = x9471;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9472 = Fp(x9459.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9473 = x9472 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9473);
reg = x9473;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9474 = Fp(x9459.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9475 = x9474 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9475);
reg = x9475;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9476 = Fp(x9459.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9477 = x9476 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9477);
reg = x9477;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9478 = Fp(x9459.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9479 = x9478 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9479);
reg = x9479;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9480 = Fp(x9459.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9481 = x9480 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][19 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9481);
reg = x9481;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9482 = Fp(x9459.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9483 = x9482 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][20 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9483);
reg = x9483;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9484 = Fp(x9459.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9485 = x9484 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][21 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9485);
reg = x9485;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9486 = Fp(x9459.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9487 = x9486 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][22 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9487);
reg = x9487;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9488 = Fp(x9459.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9489 = x9488 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][23 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9489);
reg = x9489;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9490 = Fp(x9459.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9491 = x9490 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][24 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9491);
reg = x9491;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9492 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x9492 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9493 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x9493 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9494 = x9493 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9495 = x9492 + x9494;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9496 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x9496 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9497 = x9496 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9498 = x9495 + x9497;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9499 = args[2][85 * steps + ((cycle - 0) & mask)];
assert(x9499 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9500 = x9499 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9501 = x9498 + x9500;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9502 = args[2][86 * steps + ((cycle - 0) & mask)];
assert(x9502 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9503 = x9502 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9504 = x9501 + x9503;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9505 = args[2][87 * steps + ((cycle - 0) & mask)];
assert(x9505 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9506 = x9505 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9507 = x9504 + x9506;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9508 = args[2][88 * steps + ((cycle - 0) & mask)];
assert(x9508 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9509 = x9508 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9510 = x9507 + x9509;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9511 = args[2][89 * steps + ((cycle - 0) & mask)];
assert(x9511 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9512 = x9511 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9513 = x9510 + x9512;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9514 = args[2][90 * steps + ((cycle - 0) & mask)];
assert(x9514 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9515 = x9514 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9516 = x9513 + x9515;
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9517 = args[2][91 * steps + ((cycle - 0) & mask)];
assert(x9517 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9518 = x9517 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9519 = x9516 + x9518;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9520 = args[2][19 * steps + ((cycle - 0) & mask)];
assert(x9520 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9521 = x9520 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9522 = x9519 + x9521;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9523 = args[2][20 * steps + ((cycle - 0) & mask)];
assert(x9523 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9524 = x9523 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9525 = x9522 + x9524;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9526 = args[2][21 * steps + ((cycle - 0) & mask)];
assert(x9526 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9527 = x9526 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9528 = x9525 + x9527;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9529 = args[2][22 * steps + ((cycle - 0) & mask)];
assert(x9529 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9530 = x9529 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9531 = x9528 + x9530;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9532 = args[2][23 * steps + ((cycle - 0) & mask)];
assert(x9532 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9533 = x9532 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9534 = x9531 + x9533;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9535 = args[2][24 * steps + ((cycle - 0) & mask)];
assert(x9535 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9536 = x9535 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9537 = x9534 + x9536;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x9538 = x9459 - x9537;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x9539 = x9538 * x16;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9539);
reg = x9539;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9540 = args[2][80 * steps + ((cycle - 0) & mask)];
assert(x9540 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":117:30)
auto x9541 = x9460 + x9540;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9542 = Fp(x9541.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9542);
reg = x9542;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9543 = Fp(x9541.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9544 = x9543 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9544);
reg = x9544;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9545 = Fp(x9541.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9546 = x9545 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9546);
reg = x9546;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9547 = Fp(x9541.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9548 = x9547 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9548);
reg = x9548;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9549 = Fp(x9541.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9550 = x9549 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9550);
reg = x9550;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9551 = Fp(x9541.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9552 = x9551 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9552);
reg = x9552;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9553 = Fp(x9541.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9554 = x9553 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9554);
reg = x9554;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9555 = Fp(x9541.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9556 = x9555 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9556);
reg = x9556;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9557 = Fp(x9541.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9558 = x9557 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9558);
reg = x9558;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9559 = Fp(x9541.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9560 = x9559 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9560);
reg = x9560;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9561 = Fp(x9541.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9562 = x9561 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9562);
reg = x9562;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9563 = Fp(x9541.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9564 = x9563 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9564);
reg = x9564;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9565 = Fp(x9541.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9566 = x9565 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9566);
reg = x9566;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9567 = Fp(x9541.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9568 = x9567 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9568);
reg = x9568;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9569 = Fp(x9541.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9570 = x9569 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9570);
reg = x9570;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9571 = Fp(x9541.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9572 = x9571 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9572);
reg = x9572;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9573 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x9573 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9574 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x9574 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9575 = x9574 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9576 = x9573 + x9575;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9577 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x9577 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9578 = x9577 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9579 = x9576 + x9578;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9580 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x9580 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9581 = x9580 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9582 = x9579 + x9581;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9583 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x9583 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9584 = x9583 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9585 = x9582 + x9584;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9586 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x9586 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9587 = x9586 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9588 = x9585 + x9587;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9589 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x9589 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9590 = x9589 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9591 = x9588 + x9590;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9592 = args[2][32 * steps + ((cycle - 0) & mask)];
assert(x9592 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9593 = x9592 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9594 = x9591 + x9593;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9595 = args[2][33 * steps + ((cycle - 0) & mask)];
assert(x9595 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9596 = x9595 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9597 = x9594 + x9596;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9598 = args[2][34 * steps + ((cycle - 0) & mask)];
assert(x9598 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9599 = x9598 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9600 = x9597 + x9599;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9601 = args[2][35 * steps + ((cycle - 0) & mask)];
assert(x9601 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9602 = x9601 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9603 = x9600 + x9602;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9604 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x9604 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9605 = x9604 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9606 = x9603 + x9605;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9607 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x9607 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9608 = x9607 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9609 = x9606 + x9608;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9610 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x9610 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9611 = x9610 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9612 = x9609 + x9611;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x9613 = args[2][39 * steps + ((cycle - 0) & mask)];
assert(x9613 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9614 = x9613 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9615 = x9612 + x9614;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9616 = args[2][40 * steps + ((cycle - 0) & mask)];
assert(x9616 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9617 = x9616 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9618 = x9615 + x9617;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x9619 = x9541 - x9618;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x9620 = x9619 * x16;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9620);
reg = x9620;
}
}
if (x8503 != 0) {
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9621 = args[2][150 * steps + ((cycle - 4) & mask)];
assert(x9621 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9622 = args[2][151 * steps + ((cycle - 4) & mask)];
assert(x9622 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9623 = args[2][152 * steps + ((cycle - 4) & mask)];
assert(x9623 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9624 = args[2][153 * steps + ((cycle - 4) & mask)];
assert(x9624 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9625 = args[2][154 * steps + ((cycle - 4) & mask)];
assert(x9625 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9626 = args[2][155 * steps + ((cycle - 4) & mask)];
assert(x9626 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9627 = args[2][156 * steps + ((cycle - 4) & mask)];
assert(x9627 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9628 = args[2][157 * steps + ((cycle - 4) & mask)];
assert(x9628 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9629 = args[2][158 * steps + ((cycle - 4) & mask)];
assert(x9629 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9630 = args[2][159 * steps + ((cycle - 4) & mask)];
assert(x9630 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9631 = args[2][160 * steps + ((cycle - 4) & mask)];
assert(x9631 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9632 = args[2][161 * steps + ((cycle - 4) & mask)];
assert(x9632 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9633 = args[2][162 * steps + ((cycle - 4) & mask)];
assert(x9633 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9634 = args[2][163 * steps + ((cycle - 4) & mask)];
assert(x9634 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9635 = args[2][164 * steps + ((cycle - 4) & mask)];
assert(x9635 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9636 = args[2][165 * steps + ((cycle - 4) & mask)];
assert(x9636 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9637 = args[2][166 * steps + ((cycle - 4) & mask)];
assert(x9637 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9638 = args[2][167 * steps + ((cycle - 4) & mask)];
assert(x9638 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9639 = args[2][168 * steps + ((cycle - 4) & mask)];
assert(x9639 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9640 = args[2][169 * steps + ((cycle - 4) & mask)];
assert(x9640 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9641 = args[2][170 * steps + ((cycle - 4) & mask)];
assert(x9641 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9642 = args[2][171 * steps + ((cycle - 4) & mask)];
assert(x9642 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9643 = args[2][172 * steps + ((cycle - 4) & mask)];
assert(x9643 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9644 = args[2][173 * steps + ((cycle - 4) & mask)];
assert(x9644 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9645 = args[2][174 * steps + ((cycle - 4) & mask)];
assert(x9645 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9646 = args[2][175 * steps + ((cycle - 4) & mask)];
assert(x9646 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9647 = args[2][176 * steps + ((cycle - 4) & mask)];
assert(x9647 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9648 = args[2][177 * steps + ((cycle - 4) & mask)];
assert(x9648 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9649 = args[2][178 * steps + ((cycle - 4) & mask)];
assert(x9649 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9650 = args[2][179 * steps + ((cycle - 4) & mask)];
assert(x9650 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9651 = args[2][180 * steps + ((cycle - 4) & mask)];
assert(x9651 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9652 = args[2][181 * steps + ((cycle - 4) & mask)];
assert(x9652 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9653 = x9622 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9654 = x9621 + x9653;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9655 = x9623 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9656 = x9654 + x9655;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9657 = x9624 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9658 = x9656 + x9657;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9659 = x9625 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9660 = x9658 + x9659;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9661 = x9626 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9662 = x9660 + x9661;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9663 = x9627 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9664 = x9662 + x9663;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9665 = x9628 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9666 = x9664 + x9665;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9667 = x9629 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9668 = x9666 + x9667;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9669 = x9630 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9670 = x9668 + x9669;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9671 = x9631 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9672 = x9670 + x9671;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9673 = x9632 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9674 = x9672 + x9673;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9675 = x9633 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9676 = x9674 + x9675;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9677 = x9634 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9678 = x9676 + x9677;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9679 = x9635 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9680 = x9678 + x9679;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9681 = x9636 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9682 = x9680 + x9681;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9683 = x9638 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9684 = x9637 + x9683;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9685 = x9639 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9686 = x9684 + x9685;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9687 = x9640 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9688 = x9686 + x9687;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9689 = x9641 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9690 = x9688 + x9689;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9691 = x9642 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9692 = x9690 + x9691;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9693 = x9643 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9694 = x9692 + x9693;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9695 = x9644 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9696 = x9694 + x9695;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9697 = x9645 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9698 = x9696 + x9697;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9699 = x9646 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9700 = x9698 + x9699;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9701 = x9647 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9702 = x9700 + x9701;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9703 = x9648 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9704 = x9702 + x9703;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9705 = x9649 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9706 = x9704 + x9705;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9707 = x9650 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9708 = x9706 + x9707;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9709 = x9651 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9710 = x9708 + x9709;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9711 = x9652 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9712 = x9710 + x9711;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9713 = args[2][150 * steps + ((cycle - 68) & mask)];
assert(x9713 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9714 = args[2][151 * steps + ((cycle - 68) & mask)];
assert(x9714 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9715 = args[2][152 * steps + ((cycle - 68) & mask)];
assert(x9715 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9716 = args[2][153 * steps + ((cycle - 68) & mask)];
assert(x9716 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9717 = args[2][154 * steps + ((cycle - 68) & mask)];
assert(x9717 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9718 = args[2][155 * steps + ((cycle - 68) & mask)];
assert(x9718 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9719 = args[2][156 * steps + ((cycle - 68) & mask)];
assert(x9719 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9720 = args[2][157 * steps + ((cycle - 68) & mask)];
assert(x9720 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9721 = args[2][158 * steps + ((cycle - 68) & mask)];
assert(x9721 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9722 = args[2][159 * steps + ((cycle - 68) & mask)];
assert(x9722 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9723 = args[2][160 * steps + ((cycle - 68) & mask)];
assert(x9723 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9724 = args[2][161 * steps + ((cycle - 68) & mask)];
assert(x9724 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9725 = args[2][162 * steps + ((cycle - 68) & mask)];
assert(x9725 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9726 = args[2][163 * steps + ((cycle - 68) & mask)];
assert(x9726 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9727 = args[2][164 * steps + ((cycle - 68) & mask)];
assert(x9727 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9728 = args[2][165 * steps + ((cycle - 68) & mask)];
assert(x9728 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9729 = args[2][166 * steps + ((cycle - 68) & mask)];
assert(x9729 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9730 = args[2][167 * steps + ((cycle - 68) & mask)];
assert(x9730 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9731 = args[2][168 * steps + ((cycle - 68) & mask)];
assert(x9731 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9732 = args[2][169 * steps + ((cycle - 68) & mask)];
assert(x9732 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9733 = args[2][170 * steps + ((cycle - 68) & mask)];
assert(x9733 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9734 = args[2][171 * steps + ((cycle - 68) & mask)];
assert(x9734 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9735 = args[2][172 * steps + ((cycle - 68) & mask)];
assert(x9735 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9736 = args[2][173 * steps + ((cycle - 68) & mask)];
assert(x9736 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9737 = args[2][174 * steps + ((cycle - 68) & mask)];
assert(x9737 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9738 = args[2][175 * steps + ((cycle - 68) & mask)];
assert(x9738 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9739 = args[2][176 * steps + ((cycle - 68) & mask)];
assert(x9739 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9740 = args[2][177 * steps + ((cycle - 68) & mask)];
assert(x9740 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9741 = args[2][178 * steps + ((cycle - 68) & mask)];
assert(x9741 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9742 = args[2][179 * steps + ((cycle - 68) & mask)];
assert(x9742 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9743 = args[2][180 * steps + ((cycle - 68) & mask)];
assert(x9743 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9744 = args[2][181 * steps + ((cycle - 68) & mask)];
assert(x9744 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9745 = x9714 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9746 = x9713 + x9745;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9747 = x9715 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9748 = x9746 + x9747;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9749 = x9716 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9750 = x9748 + x9749;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9751 = x9717 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9752 = x9750 + x9751;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9753 = x9718 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9754 = x9752 + x9753;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9755 = x9719 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9756 = x9754 + x9755;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9757 = x9720 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9758 = x9756 + x9757;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9759 = x9721 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9760 = x9758 + x9759;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9761 = x9722 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9762 = x9760 + x9761;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9763 = x9723 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9764 = x9762 + x9763;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9765 = x9724 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9766 = x9764 + x9765;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9767 = x9725 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9768 = x9766 + x9767;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9769 = x9726 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9770 = x9768 + x9769;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9771 = x9727 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9772 = x9770 + x9771;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9773 = x9728 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9774 = x9772 + x9773;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9775 = x9730 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9776 = x9729 + x9775;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9777 = x9731 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9778 = x9776 + x9777;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9779 = x9732 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9780 = x9778 + x9779;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9781 = x9733 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9782 = x9780 + x9781;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9783 = x9734 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9784 = x9782 + x9783;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9785 = x9735 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9786 = x9784 + x9785;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9787 = x9736 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9788 = x9786 + x9787;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9789 = x9737 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9790 = x9788 + x9789;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9791 = x9738 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9792 = x9790 + x9791;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9793 = x9739 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9794 = x9792 + x9793;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9795 = x9740 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9796 = x9794 + x9795;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9797 = x9741 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9798 = x9796 + x9797;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9799 = x9742 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9800 = x9798 + x9799;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9801 = x9743 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9802 = x9800 + x9801;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x9803 = x9744 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x9804 = x9802 + x9803;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x9805 = x9682 + x9774;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x9806 = x9712 + x9804;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9807 = Fp(x9805.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][150 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9807);
reg = x9807;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9808 = Fp(x9805.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9809 = x9808 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][151 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9809);
reg = x9809;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9810 = Fp(x9805.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9811 = x9810 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][152 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9811);
reg = x9811;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9812 = Fp(x9805.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9813 = x9812 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][153 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9813);
reg = x9813;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9814 = Fp(x9805.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9815 = x9814 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][154 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9815);
reg = x9815;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9816 = Fp(x9805.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9817 = x9816 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][155 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9817);
reg = x9817;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9818 = Fp(x9805.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9819 = x9818 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][156 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9819);
reg = x9819;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9820 = Fp(x9805.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9821 = x9820 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][157 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9821);
reg = x9821;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9822 = Fp(x9805.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9823 = x9822 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][158 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9823);
reg = x9823;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9824 = Fp(x9805.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9825 = x9824 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][159 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9825);
reg = x9825;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9826 = Fp(x9805.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9827 = x9826 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][160 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9827);
reg = x9827;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9828 = Fp(x9805.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9829 = x9828 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9829);
reg = x9829;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9830 = Fp(x9805.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9831 = x9830 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9831);
reg = x9831;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9832 = Fp(x9805.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9833 = x9832 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9833);
reg = x9833;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9834 = Fp(x9805.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9835 = x9834 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9835);
reg = x9835;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9836 = Fp(x9805.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9837 = x9836 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9837);
reg = x9837;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9838 = args[2][150 * steps + ((cycle - 0) & mask)];
assert(x9838 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9839 = args[2][151 * steps + ((cycle - 0) & mask)];
assert(x9839 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9840 = x9839 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9841 = x9838 + x9840;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9842 = args[2][152 * steps + ((cycle - 0) & mask)];
assert(x9842 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9843 = x9842 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9844 = x9841 + x9843;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9845 = args[2][153 * steps + ((cycle - 0) & mask)];
assert(x9845 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9846 = x9845 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9847 = x9844 + x9846;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9848 = args[2][154 * steps + ((cycle - 0) & mask)];
assert(x9848 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9849 = x9848 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9850 = x9847 + x9849;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9851 = args[2][155 * steps + ((cycle - 0) & mask)];
assert(x9851 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9852 = x9851 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9853 = x9850 + x9852;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9854 = args[2][156 * steps + ((cycle - 0) & mask)];
assert(x9854 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9855 = x9854 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9856 = x9853 + x9855;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9857 = args[2][157 * steps + ((cycle - 0) & mask)];
assert(x9857 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9858 = x9857 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9859 = x9856 + x9858;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9860 = args[2][158 * steps + ((cycle - 0) & mask)];
assert(x9860 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9861 = x9860 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9862 = x9859 + x9861;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9863 = args[2][159 * steps + ((cycle - 0) & mask)];
assert(x9863 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9864 = x9863 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9865 = x9862 + x9864;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9866 = args[2][160 * steps + ((cycle - 0) & mask)];
assert(x9866 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9867 = x9866 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9868 = x9865 + x9867;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9869 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x9869 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9870 = x9869 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9871 = x9868 + x9870;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9872 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x9872 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9873 = x9872 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9874 = x9871 + x9873;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9875 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x9875 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9876 = x9875 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9877 = x9874 + x9876;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9878 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x9878 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9879 = x9878 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9880 = x9877 + x9879;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9881 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x9881 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9882 = x9881 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9883 = x9880 + x9882;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x9884 = x9805 - x9883;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x9885 = x9884 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":122:26)
auto x9886 = Fp(x9885.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][76 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9886);
reg = x9886;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9887 = args[2][76 * steps + ((cycle - 0) & mask)];
assert(x9887 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":123:20)
auto x9888 = x9885 - x9887;
// loc("cirgen/circuit/rv32im/sha.cpp":123:19)
auto x9889 = x9888 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":124:20)
auto x9890 = x102 - x9889;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
auto x9891 = x9889 * x9890;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
if (x9891 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:124");
// loc("cirgen/circuit/rv32im/sha.cpp":125:32)
auto x9892 = x9806 + x9885;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9893 = Fp(x9892.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9893);
reg = x9893;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9894 = Fp(x9892.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9895 = x9894 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9895);
reg = x9895;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9896 = Fp(x9892.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9897 = x9896 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9897);
reg = x9897;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9898 = Fp(x9892.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9899 = x9898 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][169 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9899);
reg = x9899;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9900 = Fp(x9892.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9901 = x9900 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][170 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9901);
reg = x9901;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9902 = Fp(x9892.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9903 = x9902 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][171 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9903);
reg = x9903;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9904 = Fp(x9892.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9905 = x9904 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][172 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9905);
reg = x9905;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9906 = Fp(x9892.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9907 = x9906 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9907);
reg = x9907;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9908 = Fp(x9892.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9909 = x9908 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][174 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9909);
reg = x9909;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9910 = Fp(x9892.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9911 = x9910 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][175 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9911);
reg = x9911;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9912 = Fp(x9892.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9913 = x9912 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9913);
reg = x9913;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9914 = Fp(x9892.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9915 = x9914 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9915);
reg = x9915;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9916 = Fp(x9892.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9917 = x9916 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9917);
reg = x9917;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9918 = Fp(x9892.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9919 = x9918 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9919);
reg = x9919;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9920 = Fp(x9892.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9921 = x9920 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9921);
reg = x9921;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x9922 = Fp(x9892.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x9923 = x9922 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9923);
reg = x9923;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9924 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x9924 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9925 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x9925 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9926 = x9925 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9927 = x9924 + x9926;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9928 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x9928 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9929 = x9928 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9930 = x9927 + x9929;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9931 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x9931 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9932 = x9931 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9933 = x9930 + x9932;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9934 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x9934 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9935 = x9934 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9936 = x9933 + x9935;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9937 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x9937 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9938 = x9937 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9939 = x9936 + x9938;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9940 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x9940 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9941 = x9940 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9942 = x9939 + x9941;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9943 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x9943 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9944 = x9943 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9945 = x9942 + x9944;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9946 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x9946 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9947 = x9946 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9948 = x9945 + x9947;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9949 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x9949 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9950 = x9949 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9951 = x9948 + x9950;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9952 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x9952 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9953 = x9952 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9954 = x9951 + x9953;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9955 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x9955 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9956 = x9955 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9957 = x9954 + x9956;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9958 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x9958 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9959 = x9958 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9960 = x9957 + x9959;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9961 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x9961 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9962 = x9961 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9963 = x9960 + x9962;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9964 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x9964 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9965 = x9964 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9966 = x9963 + x9965;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9967 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x9967 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x9968 = x9967 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x9969 = x9966 + x9968;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x9970 = x9892 - x9969;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x9971 = x9970 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":126:27)
auto x9972 = Fp(x9971.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][77 * steps + cycle];
assert(reg == Fp::invalid() || reg == x9972);
reg = x9972;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9973 = args[2][77 * steps + ((cycle - 0) & mask)];
assert(x9973 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":127:21)
auto x9974 = x9971 - x9973;
// loc("cirgen/circuit/rv32im/sha.cpp":127:20)
auto x9975 = x9974 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":128:21)
auto x9976 = x102 - x9975;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
auto x9977 = x9975 * x9976;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
if (x9977 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:128");
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9978 = args[2][182 * steps + ((cycle - 4) & mask)];
assert(x9978 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9979 = args[2][183 * steps + ((cycle - 4) & mask)];
assert(x9979 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9980 = args[2][184 * steps + ((cycle - 4) & mask)];
assert(x9980 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9981 = args[2][185 * steps + ((cycle - 4) & mask)];
assert(x9981 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9982 = args[2][186 * steps + ((cycle - 4) & mask)];
assert(x9982 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9983 = args[2][187 * steps + ((cycle - 4) & mask)];
assert(x9983 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9984 = args[2][188 * steps + ((cycle - 4) & mask)];
assert(x9984 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9985 = args[2][189 * steps + ((cycle - 4) & mask)];
assert(x9985 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9986 = args[2][190 * steps + ((cycle - 4) & mask)];
assert(x9986 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9987 = args[2][191 * steps + ((cycle - 4) & mask)];
assert(x9987 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9988 = args[2][192 * steps + ((cycle - 4) & mask)];
assert(x9988 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9989 = args[2][193 * steps + ((cycle - 4) & mask)];
assert(x9989 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9990 = args[2][194 * steps + ((cycle - 4) & mask)];
assert(x9990 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9991 = args[2][195 * steps + ((cycle - 4) & mask)];
assert(x9991 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9992 = args[2][196 * steps + ((cycle - 4) & mask)];
assert(x9992 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9993 = args[2][197 * steps + ((cycle - 4) & mask)];
assert(x9993 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9994 = args[2][198 * steps + ((cycle - 4) & mask)];
assert(x9994 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9995 = args[2][199 * steps + ((cycle - 4) & mask)];
assert(x9995 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9996 = args[2][200 * steps + ((cycle - 4) & mask)];
assert(x9996 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9997 = args[2][201 * steps + ((cycle - 4) & mask)];
assert(x9997 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9998 = args[2][202 * steps + ((cycle - 4) & mask)];
assert(x9998 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x9999 = args[2][203 * steps + ((cycle - 4) & mask)];
assert(x9999 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10000 = args[2][204 * steps + ((cycle - 4) & mask)];
assert(x10000 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10001 = args[2][205 * steps + ((cycle - 4) & mask)];
assert(x10001 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10002 = args[2][206 * steps + ((cycle - 4) & mask)];
assert(x10002 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10003 = args[2][207 * steps + ((cycle - 4) & mask)];
assert(x10003 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10004 = args[2][208 * steps + ((cycle - 4) & mask)];
assert(x10004 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10005 = args[2][209 * steps + ((cycle - 4) & mask)];
assert(x10005 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10006 = args[2][210 * steps + ((cycle - 4) & mask)];
assert(x10006 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10007 = args[2][211 * steps + ((cycle - 4) & mask)];
assert(x10007 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10008 = args[2][212 * steps + ((cycle - 4) & mask)];
assert(x10008 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10009 = args[2][213 * steps + ((cycle - 4) & mask)];
assert(x10009 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10010 = x9979 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10011 = x9978 + x10010;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10012 = x9980 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10013 = x10011 + x10012;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10014 = x9981 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10015 = x10013 + x10014;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10016 = x9982 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10017 = x10015 + x10016;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10018 = x9983 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10019 = x10017 + x10018;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10020 = x9984 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10021 = x10019 + x10020;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10022 = x9985 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10023 = x10021 + x10022;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10024 = x9986 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10025 = x10023 + x10024;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10026 = x9987 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10027 = x10025 + x10026;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10028 = x9988 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10029 = x10027 + x10028;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10030 = x9989 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10031 = x10029 + x10030;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10032 = x9990 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10033 = x10031 + x10032;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10034 = x9991 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10035 = x10033 + x10034;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10036 = x9992 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10037 = x10035 + x10036;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10038 = x9993 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10039 = x10037 + x10038;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10040 = x9995 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10041 = x9994 + x10040;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10042 = x9996 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10043 = x10041 + x10042;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10044 = x9997 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10045 = x10043 + x10044;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10046 = x9998 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10047 = x10045 + x10046;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10048 = x9999 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10049 = x10047 + x10048;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10050 = x10000 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10051 = x10049 + x10050;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10052 = x10001 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10053 = x10051 + x10052;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10054 = x10002 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10055 = x10053 + x10054;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10056 = x10003 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10057 = x10055 + x10056;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10058 = x10004 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10059 = x10057 + x10058;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10060 = x10005 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10061 = x10059 + x10060;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10062 = x10006 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10063 = x10061 + x10062;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10064 = x10007 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10065 = x10063 + x10064;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10066 = x10008 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10067 = x10065 + x10066;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10068 = x10009 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10069 = x10067 + x10068;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10070 = args[2][182 * steps + ((cycle - 68) & mask)];
assert(x10070 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10071 = args[2][183 * steps + ((cycle - 68) & mask)];
assert(x10071 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10072 = args[2][184 * steps + ((cycle - 68) & mask)];
assert(x10072 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10073 = args[2][185 * steps + ((cycle - 68) & mask)];
assert(x10073 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10074 = args[2][186 * steps + ((cycle - 68) & mask)];
assert(x10074 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10075 = args[2][187 * steps + ((cycle - 68) & mask)];
assert(x10075 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10076 = args[2][188 * steps + ((cycle - 68) & mask)];
assert(x10076 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10077 = args[2][189 * steps + ((cycle - 68) & mask)];
assert(x10077 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10078 = args[2][190 * steps + ((cycle - 68) & mask)];
assert(x10078 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10079 = args[2][191 * steps + ((cycle - 68) & mask)];
assert(x10079 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10080 = args[2][192 * steps + ((cycle - 68) & mask)];
assert(x10080 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10081 = args[2][193 * steps + ((cycle - 68) & mask)];
assert(x10081 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10082 = args[2][194 * steps + ((cycle - 68) & mask)];
assert(x10082 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10083 = args[2][195 * steps + ((cycle - 68) & mask)];
assert(x10083 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10084 = args[2][196 * steps + ((cycle - 68) & mask)];
assert(x10084 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10085 = args[2][197 * steps + ((cycle - 68) & mask)];
assert(x10085 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10086 = args[2][198 * steps + ((cycle - 68) & mask)];
assert(x10086 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10087 = args[2][199 * steps + ((cycle - 68) & mask)];
assert(x10087 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10088 = args[2][200 * steps + ((cycle - 68) & mask)];
assert(x10088 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10089 = args[2][201 * steps + ((cycle - 68) & mask)];
assert(x10089 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10090 = args[2][202 * steps + ((cycle - 68) & mask)];
assert(x10090 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10091 = args[2][203 * steps + ((cycle - 68) & mask)];
assert(x10091 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10092 = args[2][204 * steps + ((cycle - 68) & mask)];
assert(x10092 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10093 = args[2][205 * steps + ((cycle - 68) & mask)];
assert(x10093 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10094 = args[2][206 * steps + ((cycle - 68) & mask)];
assert(x10094 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10095 = args[2][207 * steps + ((cycle - 68) & mask)];
assert(x10095 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10096 = args[2][208 * steps + ((cycle - 68) & mask)];
assert(x10096 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10097 = args[2][209 * steps + ((cycle - 68) & mask)];
assert(x10097 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10098 = args[2][210 * steps + ((cycle - 68) & mask)];
assert(x10098 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10099 = args[2][211 * steps + ((cycle - 68) & mask)];
assert(x10099 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10100 = args[2][212 * steps + ((cycle - 68) & mask)];
assert(x10100 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10101 = args[2][213 * steps + ((cycle - 68) & mask)];
assert(x10101 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10102 = x10071 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10103 = x10070 + x10102;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10104 = x10072 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10105 = x10103 + x10104;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10106 = x10073 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10107 = x10105 + x10106;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10108 = x10074 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10109 = x10107 + x10108;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10110 = x10075 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10111 = x10109 + x10110;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10112 = x10076 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10113 = x10111 + x10112;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10114 = x10077 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10115 = x10113 + x10114;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10116 = x10078 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10117 = x10115 + x10116;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10118 = x10079 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10119 = x10117 + x10118;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10120 = x10080 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10121 = x10119 + x10120;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10122 = x10081 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10123 = x10121 + x10122;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10124 = x10082 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10125 = x10123 + x10124;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10126 = x10083 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10127 = x10125 + x10126;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10128 = x10084 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10129 = x10127 + x10128;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10130 = x10085 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10131 = x10129 + x10130;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10132 = x10087 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10133 = x10086 + x10132;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10134 = x10088 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10135 = x10133 + x10134;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10136 = x10089 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10137 = x10135 + x10136;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10138 = x10090 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10139 = x10137 + x10138;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10140 = x10091 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10141 = x10139 + x10140;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10142 = x10092 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10143 = x10141 + x10142;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10144 = x10093 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10145 = x10143 + x10144;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10146 = x10094 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10147 = x10145 + x10146;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10148 = x10095 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10149 = x10147 + x10148;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10150 = x10096 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10151 = x10149 + x10150;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10152 = x10097 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10153 = x10151 + x10152;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10154 = x10098 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10155 = x10153 + x10154;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10156 = x10099 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10157 = x10155 + x10156;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10158 = x10100 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10159 = x10157 + x10158;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x10160 = x10101 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x10161 = x10159 + x10160;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x10162 = x10039 + x10131;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x10163 = x10069 + x10161;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10164 = Fp(x10162.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10164);
reg = x10164;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10165 = Fp(x10162.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10166 = x10165 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10166);
reg = x10166;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10167 = Fp(x10162.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10168 = x10167 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10168);
reg = x10168;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10169 = Fp(x10162.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10170 = x10169 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10170);
reg = x10170;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10171 = Fp(x10162.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10172 = x10171 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10172);
reg = x10172;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10173 = Fp(x10162.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10174 = x10173 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10174);
reg = x10174;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10175 = Fp(x10162.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10176 = x10175 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10176);
reg = x10176;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10177 = Fp(x10162.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10178 = x10177 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10178);
reg = x10178;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10179 = Fp(x10162.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10180 = x10179 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][190 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10180);
reg = x10180;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10181 = Fp(x10162.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10182 = x10181 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][191 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10182);
reg = x10182;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10183 = Fp(x10162.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10184 = x10183 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][192 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10184);
reg = x10184;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10185 = Fp(x10162.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10186 = x10185 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][193 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10186);
reg = x10186;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10187 = Fp(x10162.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10188 = x10187 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][194 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10188);
reg = x10188;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10189 = Fp(x10162.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10190 = x10189 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][195 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10190);
reg = x10190;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10191 = Fp(x10162.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10192 = x10191 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][196 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10192);
reg = x10192;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10193 = Fp(x10162.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10194 = x10193 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][197 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10194);
reg = x10194;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10195 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x10195 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10196 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x10196 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10197 = x10196 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10198 = x10195 + x10197;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10199 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x10199 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10200 = x10199 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10201 = x10198 + x10200;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10202 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x10202 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10203 = x10202 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10204 = x10201 + x10203;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10205 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x10205 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10206 = x10205 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10207 = x10204 + x10206;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10208 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x10208 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10209 = x10208 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10210 = x10207 + x10209;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10211 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x10211 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10212 = x10211 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10213 = x10210 + x10212;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10214 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x10214 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10215 = x10214 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10216 = x10213 + x10215;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10217 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x10217 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10218 = x10217 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10219 = x10216 + x10218;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10220 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x10220 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10221 = x10220 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10222 = x10219 + x10221;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10223 = args[2][192 * steps + ((cycle - 0) & mask)];
assert(x10223 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10224 = x10223 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10225 = x10222 + x10224;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10226 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x10226 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10227 = x10226 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10228 = x10225 + x10227;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10229 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x10229 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10230 = x10229 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10231 = x10228 + x10230;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10232 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x10232 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10233 = x10232 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10234 = x10231 + x10233;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10235 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x10235 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10236 = x10235 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10237 = x10234 + x10236;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10238 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x10238 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10239 = x10238 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10240 = x10237 + x10239;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x10241 = x10162 - x10240;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x10242 = x10241 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":122:26)
auto x10243 = Fp(x10242.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][78 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10243);
reg = x10243;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10244 = args[2][78 * steps + ((cycle - 0) & mask)];
assert(x10244 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":123:20)
auto x10245 = x10242 - x10244;
// loc("cirgen/circuit/rv32im/sha.cpp":123:19)
auto x10246 = x10245 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":124:20)
auto x10247 = x102 - x10246;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
auto x10248 = x10246 * x10247;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
if (x10248 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:124");
// loc("cirgen/circuit/rv32im/sha.cpp":125:32)
auto x10249 = x10163 + x10242;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10250 = Fp(x10249.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][198 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10250);
reg = x10250;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10251 = Fp(x10249.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10252 = x10251 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][199 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10252);
reg = x10252;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10253 = Fp(x10249.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10254 = x10253 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][200 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10254);
reg = x10254;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10255 = Fp(x10249.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10256 = x10255 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][201 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10256);
reg = x10256;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10257 = Fp(x10249.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10258 = x10257 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][202 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10258);
reg = x10258;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10259 = Fp(x10249.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10260 = x10259 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][203 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10260);
reg = x10260;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10261 = Fp(x10249.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10262 = x10261 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10262);
reg = x10262;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10263 = Fp(x10249.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10264 = x10263 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10264);
reg = x10264;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10265 = Fp(x10249.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10266 = x10265 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10266);
reg = x10266;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10267 = Fp(x10249.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10268 = x10267 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10268);
reg = x10268;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10269 = Fp(x10249.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10270 = x10269 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][208 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10270);
reg = x10270;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10271 = Fp(x10249.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10272 = x10271 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][209 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10272);
reg = x10272;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10273 = Fp(x10249.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10274 = x10273 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][210 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10274);
reg = x10274;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10275 = Fp(x10249.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10276 = x10275 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][211 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10276);
reg = x10276;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10277 = Fp(x10249.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10278 = x10277 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][212 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10278);
reg = x10278;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x10279 = Fp(x10249.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x10280 = x10279 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][213 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10280);
reg = x10280;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10281 = args[2][198 * steps + ((cycle - 0) & mask)];
assert(x10281 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10282 = args[2][199 * steps + ((cycle - 0) & mask)];
assert(x10282 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10283 = x10282 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10284 = x10281 + x10283;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10285 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x10285 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10286 = x10285 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10287 = x10284 + x10286;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10288 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x10288 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10289 = x10288 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10290 = x10287 + x10289;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10291 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x10291 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10292 = x10291 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10293 = x10290 + x10292;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10294 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x10294 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10295 = x10294 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10296 = x10293 + x10295;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10297 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x10297 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10298 = x10297 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10299 = x10296 + x10298;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10300 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x10300 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10301 = x10300 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10302 = x10299 + x10301;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10303 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x10303 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10304 = x10303 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10305 = x10302 + x10304;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10306 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x10306 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10307 = x10306 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10308 = x10305 + x10307;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10309 = args[2][208 * steps + ((cycle - 0) & mask)];
assert(x10309 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10310 = x10309 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10311 = x10308 + x10310;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10312 = args[2][209 * steps + ((cycle - 0) & mask)];
assert(x10312 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10313 = x10312 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10314 = x10311 + x10313;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10315 = args[2][210 * steps + ((cycle - 0) & mask)];
assert(x10315 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10316 = x10315 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10317 = x10314 + x10316;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10318 = args[2][211 * steps + ((cycle - 0) & mask)];
assert(x10318 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10319 = x10318 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10320 = x10317 + x10319;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10321 = args[2][212 * steps + ((cycle - 0) & mask)];
assert(x10321 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10322 = x10321 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10323 = x10320 + x10322;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10324 = args[2][213 * steps + ((cycle - 0) & mask)];
assert(x10324 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x10325 = x10324 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x10326 = x10323 + x10325;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x10327 = x10249 - x10326;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x10328 = x10327 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":126:27)
auto x10329 = Fp(x10328.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10329);
reg = x10329;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10330 = args[2][79 * steps + ((cycle - 0) & mask)];
assert(x10330 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":127:21)
auto x10331 = x10328 - x10330;
// loc("cirgen/circuit/rv32im/sha.cpp":127:20)
auto x10332 = x10331 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":128:21)
auto x10333 = x102 - x10332;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
auto x10334 = x10332 * x10333;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
if (x10334 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:128");
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10335 = args[2][143 * steps + ((cycle - 0) & mask)];
assert(x10335 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":399:17)
auto x10336 = x102 - x10335;
if (x8511 != 0) {
if (x10335 != 0) {
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x10337 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x10337 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":403:26)
auto x10338 = x10337 + x8495;
{
host_args.at(0) = x10338;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x10339 = host_outs.at(0);
auto x10340 = host_outs.at(1);
auto x10341 = host_outs.at(2);
auto x10342 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10339);
reg = x10339;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10340);
reg = x10340;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10341);
reg = x10341;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10342);
reg = x10342;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10343 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x10343 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x10344 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x10344 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x10345 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x10345 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x10346 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x10346 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10338);
reg = x10338;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8483);
reg = x8483;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10343);
reg = x10343;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10344);
reg = x10344;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10345);
reg = x10345;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10346);
reg = x10346;
}
// loc("cirgen/circuit/rv32im/sha.cpp":404:26)
auto x10347 = x10337 + x85;
// loc("cirgen/circuit/rv32im/sha.cpp":404:26)
auto x10348 = x10347 + x8495;
{
host_args.at(0) = x10348;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x10349 = host_outs.at(0);
auto x10350 = host_outs.at(1);
auto x10351 = host_outs.at(2);
auto x10352 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10349);
reg = x10349;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10350);
reg = x10350;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10351);
reg = x10351;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10352);
reg = x10352;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10353 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x10353 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x10354 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x10354 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x10355 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x10355 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x10356 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x10356 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10348);
reg = x10348;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8483);
reg = x8483;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10353);
reg = x10353;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10354);
reg = x10354;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10355);
reg = x10355;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10356);
reg = x10356;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/Reg"("cirgen/components/ram.cpp":137:10))
auto x10357 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x10357 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":405:39)
auto x10358 = x10357 * x85;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10359 = args[2][150 * steps + ((cycle - 0) & mask)];
assert(x10359 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10360 = args[2][158 * steps + ((cycle - 0) & mask)];
assert(x10360 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10361 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x10361 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10362 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x10362 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10363 = args[2][151 * steps + ((cycle - 0) & mask)];
assert(x10363 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10364 = x10363 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10365 = x10359 + x10364;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10366 = args[2][159 * steps + ((cycle - 0) & mask)];
assert(x10366 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10367 = x10366 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10368 = x10360 + x10367;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10369 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x10369 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10370 = x10369 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10371 = x10361 + x10370;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10372 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x10372 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10373 = x10372 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10374 = x10362 + x10373;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10375 = args[2][152 * steps + ((cycle - 0) & mask)];
assert(x10375 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10376 = x10375 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10377 = x10365 + x10376;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10378 = args[2][160 * steps + ((cycle - 0) & mask)];
assert(x10378 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10379 = x10378 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10380 = x10368 + x10379;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10381 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x10381 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10382 = x10381 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10383 = x10371 + x10382;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10384 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x10384 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10385 = x10384 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10386 = x10374 + x10385;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10387 = args[2][153 * steps + ((cycle - 0) & mask)];
assert(x10387 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10388 = x10387 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10389 = x10377 + x10388;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10390 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x10390 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10391 = x10390 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10392 = x10380 + x10391;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10393 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x10393 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10394 = x10393 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10395 = x10383 + x10394;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10396 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x10396 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10397 = x10396 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10398 = x10386 + x10397;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10399 = args[2][154 * steps + ((cycle - 0) & mask)];
assert(x10399 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10400 = x10399 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10401 = x10389 + x10400;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10402 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x10402 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10403 = x10402 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10404 = x10392 + x10403;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10405 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x10405 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10406 = x10405 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10407 = x10395 + x10406;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10408 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x10408 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10409 = x10408 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10410 = x10398 + x10409;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10411 = args[2][155 * steps + ((cycle - 0) & mask)];
assert(x10411 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10412 = x10411 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10413 = x10401 + x10412;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10414 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x10414 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10415 = x10414 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10416 = x10404 + x10415;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10417 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x10417 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10418 = x10417 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10419 = x10407 + x10418;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10420 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x10420 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10421 = x10420 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10422 = x10410 + x10421;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10423 = args[2][156 * steps + ((cycle - 0) & mask)];
assert(x10423 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10424 = x10423 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10425 = x10413 + x10424;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10426 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x10426 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10427 = x10426 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10428 = x10416 + x10427;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10429 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x10429 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10430 = x10429 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10431 = x10419 + x10430;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10432 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x10432 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10433 = x10432 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10434 = x10422 + x10433;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10435 = args[2][157 * steps + ((cycle - 0) & mask)];
assert(x10435 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10436 = x10435 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10437 = x10425 + x10436;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10438 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x10438 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10439 = x10438 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10440 = x10428 + x10439;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10441 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x10441 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10442 = x10441 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10443 = x10431 + x10442;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10444 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x10444 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10445 = x10444 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10446 = x10434 + x10445;
host_args.at(0) = x10358;
host_args.at(1) = x10343;
host_args.at(2) = x10344;
host_args.at(3) = x10345;
host_args.at(4) = x10346;
host_args.at(5) = x10446;
host_args.at(6) = x10443;
host_args.at(7) = x10440;
host_args.at(8) = x10437;
host(ctx, "log", " io0: [0x%x] %w, a: %w", host_args.data(), 9, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/Reg"("cirgen/components/ram.cpp":137:10))
auto x10447 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x10447 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":406:39)
auto x10448 = x10447 * x85;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10449 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x10449 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10450 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x10450 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10451 = args[2][198 * steps + ((cycle - 0) & mask)];
assert(x10451 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10452 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x10452 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10453 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x10453 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10454 = x10453 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10455 = x10449 + x10454;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10456 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x10456 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10457 = x10456 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10458 = x10450 + x10457;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10459 = args[2][199 * steps + ((cycle - 0) & mask)];
assert(x10459 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10460 = x10459 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10461 = x10451 + x10460;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10462 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x10462 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10463 = x10462 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10464 = x10452 + x10463;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10465 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x10465 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10466 = x10465 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10467 = x10455 + x10466;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10468 = args[2][192 * steps + ((cycle - 0) & mask)];
assert(x10468 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10469 = x10468 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10470 = x10458 + x10469;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10471 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x10471 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10472 = x10471 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10473 = x10461 + x10472;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10474 = args[2][208 * steps + ((cycle - 0) & mask)];
assert(x10474 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10475 = x10474 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10476 = x10464 + x10475;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10477 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x10477 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10478 = x10477 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10479 = x10467 + x10478;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10480 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x10480 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10481 = x10480 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10482 = x10470 + x10481;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10483 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x10483 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10484 = x10483 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10485 = x10473 + x10484;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10486 = args[2][209 * steps + ((cycle - 0) & mask)];
assert(x10486 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10487 = x10486 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10488 = x10476 + x10487;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10489 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x10489 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10490 = x10489 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10491 = x10479 + x10490;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10492 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x10492 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10493 = x10492 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10494 = x10482 + x10493;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10495 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x10495 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10496 = x10495 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10497 = x10485 + x10496;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10498 = args[2][210 * steps + ((cycle - 0) & mask)];
assert(x10498 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10499 = x10498 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10500 = x10488 + x10499;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10501 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x10501 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10502 = x10501 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10503 = x10491 + x10502;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10504 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x10504 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10505 = x10504 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10506 = x10494 + x10505;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10507 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x10507 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10508 = x10507 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10509 = x10497 + x10508;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10510 = args[2][211 * steps + ((cycle - 0) & mask)];
assert(x10510 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10511 = x10510 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10512 = x10500 + x10511;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10513 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x10513 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10514 = x10513 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10515 = x10503 + x10514;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10516 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x10516 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10517 = x10516 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10518 = x10506 + x10517;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10519 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x10519 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10520 = x10519 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10521 = x10509 + x10520;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10522 = args[2][212 * steps + ((cycle - 0) & mask)];
assert(x10522 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10523 = x10522 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10524 = x10512 + x10523;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10525 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x10525 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10526 = x10525 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10527 = x10515 + x10526;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10528 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x10528 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10529 = x10528 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10530 = x10518 + x10529;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10531 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x10531 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10532 = x10531 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10533 = x10521 + x10532;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10534 = args[2][213 * steps + ((cycle - 0) & mask)];
assert(x10534 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10535 = x10534 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10536 = x10524 + x10535;
host_args.at(0) = x10448;
host_args.at(1) = x10353;
host_args.at(2) = x10354;
host_args.at(3) = x10355;
host_args.at(4) = x10356;
host_args.at(5) = x10536;
host_args.at(6) = x10533;
host_args.at(7) = x10530;
host_args.at(8) = x10527;
host(ctx, "log", " io1: [0x%x] %w, e: %w", host_args.data(), 9, host_outs.data(), 0);
// loc("./cirgen/components/u32.h":25:12)
auto x10537 = x10344 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x10538 = x10343 + x10537;
// loc("./cirgen/components/u32.h":26:12)
auto x10539 = x10345 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x10540 = x10538 + x10539;
// loc("./cirgen/components/u32.h":27:12)
auto x10541 = x10346 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x10542 = x10540 + x10541;
// loc("./cirgen/components/u32.h":25:12)
auto x10543 = x10443 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x10544 = x10446 + x10543;
// loc("./cirgen/components/u32.h":26:12)
auto x10545 = x10440 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x10546 = x10544 + x10545;
// loc("./cirgen/components/u32.h":27:12)
auto x10547 = x10437 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x10548 = x10546 + x10547;
// loc("cirgen/circuit/rv32im/sha.cpp":407:10)
auto x10549 = x10542 - x10548;
// loc("cirgen/circuit/rv32im/sha.cpp":407:10)
if (x10549 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:407");
// loc("./cirgen/components/u32.h":25:12)
auto x10550 = x10354 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x10551 = x10353 + x10550;
// loc("./cirgen/components/u32.h":26:12)
auto x10552 = x10355 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x10553 = x10551 + x10552;
// loc("./cirgen/components/u32.h":27:12)
auto x10554 = x10356 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x10555 = x10553 + x10554;
// loc("./cirgen/components/u32.h":25:12)
auto x10556 = x10533 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x10557 = x10536 + x10556;
// loc("./cirgen/components/u32.h":26:12)
auto x10558 = x10530 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x10559 = x10557 + x10558;
// loc("./cirgen/components/u32.h":27:12)
auto x10560 = x10527 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x10561 = x10559 + x10560;
// loc("cirgen/circuit/rv32im/sha.cpp":408:10)
auto x10562 = x10555 - x10561;
// loc("cirgen/circuit/rv32im/sha.cpp":408:10)
if (x10562 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:408");
}
if (x10336 != 0) {
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x10563 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x10563 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":411:27)
auto x10564 = x10563 + x8495;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10565 = args[2][150 * steps + ((cycle - 0) & mask)];
assert(x10565 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10566 = args[2][158 * steps + ((cycle - 0) & mask)];
assert(x10566 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10567 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x10567 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10568 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x10568 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10569 = args[2][151 * steps + ((cycle - 0) & mask)];
assert(x10569 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10570 = x10569 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10571 = x10565 + x10570;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10572 = args[2][159 * steps + ((cycle - 0) & mask)];
assert(x10572 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10573 = x10572 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10574 = x10566 + x10573;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10575 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x10575 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10576 = x10575 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10577 = x10567 + x10576;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10578 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x10578 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10579 = x10578 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10580 = x10568 + x10579;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10581 = args[2][152 * steps + ((cycle - 0) & mask)];
assert(x10581 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10582 = x10581 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10583 = x10571 + x10582;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10584 = args[2][160 * steps + ((cycle - 0) & mask)];
assert(x10584 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10585 = x10584 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10586 = x10574 + x10585;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10587 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x10587 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10588 = x10587 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10589 = x10577 + x10588;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10590 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x10590 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10591 = x10590 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10592 = x10580 + x10591;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10593 = args[2][153 * steps + ((cycle - 0) & mask)];
assert(x10593 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10594 = x10593 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10595 = x10583 + x10594;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10596 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x10596 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10597 = x10596 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10598 = x10586 + x10597;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10599 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x10599 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10600 = x10599 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10601 = x10589 + x10600;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10602 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x10602 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10603 = x10602 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10604 = x10592 + x10603;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10605 = args[2][154 * steps + ((cycle - 0) & mask)];
assert(x10605 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10606 = x10605 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10607 = x10595 + x10606;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10608 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x10608 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10609 = x10608 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10610 = x10598 + x10609;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10611 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x10611 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10612 = x10611 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10613 = x10601 + x10612;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10614 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x10614 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10615 = x10614 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10616 = x10604 + x10615;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10617 = args[2][155 * steps + ((cycle - 0) & mask)];
assert(x10617 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10618 = x10617 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10619 = x10607 + x10618;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10620 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x10620 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10621 = x10620 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10622 = x10610 + x10621;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10623 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x10623 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10624 = x10623 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10625 = x10613 + x10624;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10626 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x10626 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10627 = x10626 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10628 = x10616 + x10627;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10629 = args[2][156 * steps + ((cycle - 0) & mask)];
assert(x10629 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10630 = x10629 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10631 = x10619 + x10630;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10632 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x10632 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10633 = x10632 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10634 = x10622 + x10633;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10635 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x10635 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10636 = x10635 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10637 = x10625 + x10636;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10638 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x10638 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10639 = x10638 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10640 = x10628 + x10639;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10641 = args[2][157 * steps + ((cycle - 0) & mask)];
assert(x10641 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10642 = x10641 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10643 = x10631 + x10642;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10644 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x10644 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10645 = x10644 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10646 = x10634 + x10645;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10647 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x10647 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10648 = x10647 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10649 = x10637 + x10648;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10650 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x10650 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10651 = x10650 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10652 = x10640 + x10651;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10652);
reg = x10652;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10649);
reg = x10649;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10646);
reg = x10646;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10643);
reg = x10643;
}
{
host_args.at(0) = x10564;
host_args.at(1) = x10652;
host_args.at(2) = x10649;
host_args.at(3) = x10646;
host_args.at(4) = x10643;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10653 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x10653 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x10654 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x10654 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x10655 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x10655 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x10656 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x10656 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10564);
reg = x10564;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8483);
reg = x8483;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10653);
reg = x10653;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10654);
reg = x10654;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10655);
reg = x10655;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10656);
reg = x10656;
}
// loc("cirgen/circuit/rv32im/sha.cpp":412:27)
auto x10657 = x10563 + x85;
// loc("cirgen/circuit/rv32im/sha.cpp":412:27)
auto x10658 = x10657 + x8495;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10659 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x10659 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10660 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x10660 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10661 = args[2][198 * steps + ((cycle - 0) & mask)];
assert(x10661 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10662 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x10662 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10663 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x10663 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10664 = x10663 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10665 = x10659 + x10664;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10666 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x10666 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10667 = x10666 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10668 = x10660 + x10667;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10669 = args[2][199 * steps + ((cycle - 0) & mask)];
assert(x10669 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10670 = x10669 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10671 = x10661 + x10670;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10672 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x10672 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10673 = x10672 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10674 = x10662 + x10673;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10675 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x10675 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10676 = x10675 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10677 = x10665 + x10676;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10678 = args[2][192 * steps + ((cycle - 0) & mask)];
assert(x10678 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10679 = x10678 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10680 = x10668 + x10679;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10681 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x10681 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10682 = x10681 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10683 = x10671 + x10682;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10684 = args[2][208 * steps + ((cycle - 0) & mask)];
assert(x10684 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10685 = x10684 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10686 = x10674 + x10685;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10687 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x10687 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10688 = x10687 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10689 = x10677 + x10688;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10690 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x10690 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10691 = x10690 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10692 = x10680 + x10691;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10693 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x10693 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10694 = x10693 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10695 = x10683 + x10694;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10696 = args[2][209 * steps + ((cycle - 0) & mask)];
assert(x10696 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10697 = x10696 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10698 = x10686 + x10697;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10699 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x10699 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10700 = x10699 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10701 = x10689 + x10700;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10702 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x10702 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10703 = x10702 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10704 = x10692 + x10703;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10705 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x10705 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10706 = x10705 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10707 = x10695 + x10706;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10708 = args[2][210 * steps + ((cycle - 0) & mask)];
assert(x10708 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10709 = x10708 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10710 = x10698 + x10709;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10711 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x10711 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10712 = x10711 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10713 = x10701 + x10712;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10714 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x10714 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10715 = x10714 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10716 = x10704 + x10715;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10717 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x10717 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10718 = x10717 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10719 = x10707 + x10718;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10720 = args[2][211 * steps + ((cycle - 0) & mask)];
assert(x10720 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10721 = x10720 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10722 = x10710 + x10721;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10723 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x10723 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10724 = x10723 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10725 = x10713 + x10724;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10726 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x10726 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10727 = x10726 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10728 = x10716 + x10727;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10729 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x10729 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10730 = x10729 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10731 = x10719 + x10730;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10732 = args[2][212 * steps + ((cycle - 0) & mask)];
assert(x10732 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10733 = x10732 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10734 = x10722 + x10733;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10735 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x10735 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10736 = x10735 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10737 = x10725 + x10736;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10738 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x10738 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10739 = x10738 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10740 = x10728 + x10739;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10741 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x10741 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10742 = x10741 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10743 = x10731 + x10742;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10744 = args[2][213 * steps + ((cycle - 0) & mask)];
assert(x10744 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":147:53)
auto x10745 = x10744 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":147:30)
auto x10746 = x10734 + x10745;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10746);
reg = x10746;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10743);
reg = x10743;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10740);
reg = x10740;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10737);
reg = x10737;
}
{
host_args.at(0) = x10658;
host_args.at(1) = x10746;
host_args.at(2) = x10743;
host_args.at(3) = x10740;
host_args.at(4) = x10737;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10747 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x10747 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x10748 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x10748 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x10749 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x10749 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x10750 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x10750 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10658);
reg = x10658;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x8483);
reg = x8483;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10747);
reg = x10747;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10748);
reg = x10748;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10749);
reg = x10749;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x10750);
reg = x10750;
}
}
}
if (x8512 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
if (x8503 != 0) {
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10751 = args[2][150 * steps + ((cycle - 1) & mask)];
assert(x10751 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10752 = args[2][151 * steps + ((cycle - 1) & mask)];
assert(x10752 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10753 = args[2][152 * steps + ((cycle - 1) & mask)];
assert(x10753 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10754 = args[2][153 * steps + ((cycle - 1) & mask)];
assert(x10754 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10755 = args[2][154 * steps + ((cycle - 1) & mask)];
assert(x10755 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10756 = args[2][155 * steps + ((cycle - 1) & mask)];
assert(x10756 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10757 = args[2][156 * steps + ((cycle - 1) & mask)];
assert(x10757 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10758 = args[2][157 * steps + ((cycle - 1) & mask)];
assert(x10758 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10759 = args[2][158 * steps + ((cycle - 1) & mask)];
assert(x10759 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10760 = args[2][159 * steps + ((cycle - 1) & mask)];
assert(x10760 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10761 = args[2][160 * steps + ((cycle - 1) & mask)];
assert(x10761 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10762 = args[2][161 * steps + ((cycle - 1) & mask)];
assert(x10762 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10763 = args[2][162 * steps + ((cycle - 1) & mask)];
assert(x10763 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10764 = args[2][163 * steps + ((cycle - 1) & mask)];
assert(x10764 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10765 = args[2][164 * steps + ((cycle - 1) & mask)];
assert(x10765 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10766 = args[2][165 * steps + ((cycle - 1) & mask)];
assert(x10766 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10767 = args[2][166 * steps + ((cycle - 1) & mask)];
assert(x10767 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10768 = args[2][167 * steps + ((cycle - 1) & mask)];
assert(x10768 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10769 = args[2][168 * steps + ((cycle - 1) & mask)];
assert(x10769 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10770 = args[2][169 * steps + ((cycle - 1) & mask)];
assert(x10770 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10771 = args[2][170 * steps + ((cycle - 1) & mask)];
assert(x10771 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10772 = args[2][171 * steps + ((cycle - 1) & mask)];
assert(x10772 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10773 = args[2][172 * steps + ((cycle - 1) & mask)];
assert(x10773 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10774 = args[2][173 * steps + ((cycle - 1) & mask)];
assert(x10774 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10775 = args[2][174 * steps + ((cycle - 1) & mask)];
assert(x10775 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10776 = args[2][175 * steps + ((cycle - 1) & mask)];
assert(x10776 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10777 = args[2][176 * steps + ((cycle - 1) & mask)];
assert(x10777 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10778 = args[2][177 * steps + ((cycle - 1) & mask)];
assert(x10778 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10779 = args[2][178 * steps + ((cycle - 1) & mask)];
assert(x10779 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10780 = args[2][179 * steps + ((cycle - 1) & mask)];
assert(x10780 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10781 = args[2][180 * steps + ((cycle - 1) & mask)];
assert(x10781 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10782 = args[2][181 * steps + ((cycle - 1) & mask)];
assert(x10782 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10783 = args[2][150 * steps + ((cycle - 2) & mask)];
assert(x10783 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10784 = args[2][151 * steps + ((cycle - 2) & mask)];
assert(x10784 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10785 = args[2][152 * steps + ((cycle - 2) & mask)];
assert(x10785 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10786 = args[2][153 * steps + ((cycle - 2) & mask)];
assert(x10786 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10787 = args[2][154 * steps + ((cycle - 2) & mask)];
assert(x10787 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10788 = args[2][155 * steps + ((cycle - 2) & mask)];
assert(x10788 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10789 = args[2][156 * steps + ((cycle - 2) & mask)];
assert(x10789 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10790 = args[2][157 * steps + ((cycle - 2) & mask)];
assert(x10790 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10791 = args[2][158 * steps + ((cycle - 2) & mask)];
assert(x10791 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10792 = args[2][159 * steps + ((cycle - 2) & mask)];
assert(x10792 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10793 = args[2][160 * steps + ((cycle - 2) & mask)];
assert(x10793 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10794 = args[2][161 * steps + ((cycle - 2) & mask)];
assert(x10794 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10795 = args[2][162 * steps + ((cycle - 2) & mask)];
assert(x10795 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10796 = args[2][163 * steps + ((cycle - 2) & mask)];
assert(x10796 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10797 = args[2][164 * steps + ((cycle - 2) & mask)];
assert(x10797 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10798 = args[2][165 * steps + ((cycle - 2) & mask)];
assert(x10798 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10799 = args[2][166 * steps + ((cycle - 2) & mask)];
assert(x10799 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10800 = args[2][167 * steps + ((cycle - 2) & mask)];
assert(x10800 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10801 = args[2][168 * steps + ((cycle - 2) & mask)];
assert(x10801 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10802 = args[2][169 * steps + ((cycle - 2) & mask)];
assert(x10802 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10803 = args[2][170 * steps + ((cycle - 2) & mask)];
assert(x10803 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10804 = args[2][171 * steps + ((cycle - 2) & mask)];
assert(x10804 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10805 = args[2][172 * steps + ((cycle - 2) & mask)];
assert(x10805 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10806 = args[2][173 * steps + ((cycle - 2) & mask)];
assert(x10806 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10807 = args[2][174 * steps + ((cycle - 2) & mask)];
assert(x10807 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10808 = args[2][175 * steps + ((cycle - 2) & mask)];
assert(x10808 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10809 = args[2][176 * steps + ((cycle - 2) & mask)];
assert(x10809 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10810 = args[2][177 * steps + ((cycle - 2) & mask)];
assert(x10810 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10811 = args[2][178 * steps + ((cycle - 2) & mask)];
assert(x10811 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10812 = args[2][179 * steps + ((cycle - 2) & mask)];
assert(x10812 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10813 = args[2][180 * steps + ((cycle - 2) & mask)];
assert(x10813 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10814 = args[2][181 * steps + ((cycle - 2) & mask)];
assert(x10814 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10815 = args[2][150 * steps + ((cycle - 3) & mask)];
assert(x10815 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10816 = args[2][151 * steps + ((cycle - 3) & mask)];
assert(x10816 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10817 = args[2][152 * steps + ((cycle - 3) & mask)];
assert(x10817 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10818 = args[2][153 * steps + ((cycle - 3) & mask)];
assert(x10818 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10819 = args[2][154 * steps + ((cycle - 3) & mask)];
assert(x10819 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10820 = args[2][155 * steps + ((cycle - 3) & mask)];
assert(x10820 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10821 = args[2][156 * steps + ((cycle - 3) & mask)];
assert(x10821 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10822 = args[2][157 * steps + ((cycle - 3) & mask)];
assert(x10822 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10823 = args[2][158 * steps + ((cycle - 3) & mask)];
assert(x10823 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10824 = args[2][159 * steps + ((cycle - 3) & mask)];
assert(x10824 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10825 = args[2][160 * steps + ((cycle - 3) & mask)];
assert(x10825 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10826 = args[2][161 * steps + ((cycle - 3) & mask)];
assert(x10826 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10827 = args[2][162 * steps + ((cycle - 3) & mask)];
assert(x10827 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10828 = args[2][163 * steps + ((cycle - 3) & mask)];
assert(x10828 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10829 = args[2][164 * steps + ((cycle - 3) & mask)];
assert(x10829 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10830 = args[2][165 * steps + ((cycle - 3) & mask)];
assert(x10830 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10831 = args[2][166 * steps + ((cycle - 3) & mask)];
assert(x10831 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10832 = args[2][167 * steps + ((cycle - 3) & mask)];
assert(x10832 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10833 = args[2][168 * steps + ((cycle - 3) & mask)];
assert(x10833 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10834 = args[2][169 * steps + ((cycle - 3) & mask)];
assert(x10834 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10835 = args[2][170 * steps + ((cycle - 3) & mask)];
assert(x10835 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10836 = args[2][171 * steps + ((cycle - 3) & mask)];
assert(x10836 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10837 = args[2][172 * steps + ((cycle - 3) & mask)];
assert(x10837 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10838 = args[2][173 * steps + ((cycle - 3) & mask)];
assert(x10838 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10839 = args[2][174 * steps + ((cycle - 3) & mask)];
assert(x10839 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10840 = args[2][175 * steps + ((cycle - 3) & mask)];
assert(x10840 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10841 = args[2][176 * steps + ((cycle - 3) & mask)];
assert(x10841 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10842 = args[2][177 * steps + ((cycle - 3) & mask)];
assert(x10842 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10843 = args[2][178 * steps + ((cycle - 3) & mask)];
assert(x10843 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10844 = args[2][179 * steps + ((cycle - 3) & mask)];
assert(x10844 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10845 = args[2][180 * steps + ((cycle - 3) & mask)];
assert(x10845 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10846 = args[2][181 * steps + ((cycle - 3) & mask)];
assert(x10846 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10847 = args[2][150 * steps + ((cycle - 4) & mask)];
assert(x10847 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10848 = args[2][151 * steps + ((cycle - 4) & mask)];
assert(x10848 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10849 = args[2][152 * steps + ((cycle - 4) & mask)];
assert(x10849 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10850 = args[2][153 * steps + ((cycle - 4) & mask)];
assert(x10850 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10851 = args[2][154 * steps + ((cycle - 4) & mask)];
assert(x10851 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10852 = args[2][155 * steps + ((cycle - 4) & mask)];
assert(x10852 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10853 = args[2][156 * steps + ((cycle - 4) & mask)];
assert(x10853 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10854 = args[2][157 * steps + ((cycle - 4) & mask)];
assert(x10854 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10855 = args[2][158 * steps + ((cycle - 4) & mask)];
assert(x10855 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10856 = args[2][159 * steps + ((cycle - 4) & mask)];
assert(x10856 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10857 = args[2][160 * steps + ((cycle - 4) & mask)];
assert(x10857 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10858 = args[2][161 * steps + ((cycle - 4) & mask)];
assert(x10858 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10859 = args[2][162 * steps + ((cycle - 4) & mask)];
assert(x10859 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10860 = args[2][163 * steps + ((cycle - 4) & mask)];
assert(x10860 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10861 = args[2][164 * steps + ((cycle - 4) & mask)];
assert(x10861 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10862 = args[2][165 * steps + ((cycle - 4) & mask)];
assert(x10862 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10863 = args[2][166 * steps + ((cycle - 4) & mask)];
assert(x10863 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10864 = args[2][167 * steps + ((cycle - 4) & mask)];
assert(x10864 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10865 = args[2][168 * steps + ((cycle - 4) & mask)];
assert(x10865 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10866 = args[2][169 * steps + ((cycle - 4) & mask)];
assert(x10866 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10867 = args[2][170 * steps + ((cycle - 4) & mask)];
assert(x10867 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10868 = args[2][171 * steps + ((cycle - 4) & mask)];
assert(x10868 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10869 = args[2][172 * steps + ((cycle - 4) & mask)];
assert(x10869 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10870 = args[2][173 * steps + ((cycle - 4) & mask)];
assert(x10870 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10871 = args[2][174 * steps + ((cycle - 4) & mask)];
assert(x10871 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10872 = args[2][175 * steps + ((cycle - 4) & mask)];
assert(x10872 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10873 = args[2][176 * steps + ((cycle - 4) & mask)];
assert(x10873 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10874 = args[2][177 * steps + ((cycle - 4) & mask)];
assert(x10874 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10875 = args[2][178 * steps + ((cycle - 4) & mask)];
assert(x10875 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10876 = args[2][179 * steps + ((cycle - 4) & mask)];
assert(x10876 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10877 = args[2][180 * steps + ((cycle - 4) & mask)];
assert(x10877 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10878 = args[2][181 * steps + ((cycle - 4) & mask)];
assert(x10878 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10879 = args[2][182 * steps + ((cycle - 1) & mask)];
assert(x10879 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10880 = args[2][183 * steps + ((cycle - 1) & mask)];
assert(x10880 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10881 = args[2][184 * steps + ((cycle - 1) & mask)];
assert(x10881 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10882 = args[2][185 * steps + ((cycle - 1) & mask)];
assert(x10882 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10883 = args[2][186 * steps + ((cycle - 1) & mask)];
assert(x10883 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10884 = args[2][187 * steps + ((cycle - 1) & mask)];
assert(x10884 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10885 = args[2][188 * steps + ((cycle - 1) & mask)];
assert(x10885 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10886 = args[2][189 * steps + ((cycle - 1) & mask)];
assert(x10886 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10887 = args[2][190 * steps + ((cycle - 1) & mask)];
assert(x10887 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10888 = args[2][191 * steps + ((cycle - 1) & mask)];
assert(x10888 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10889 = args[2][192 * steps + ((cycle - 1) & mask)];
assert(x10889 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10890 = args[2][193 * steps + ((cycle - 1) & mask)];
assert(x10890 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10891 = args[2][194 * steps + ((cycle - 1) & mask)];
assert(x10891 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10892 = args[2][195 * steps + ((cycle - 1) & mask)];
assert(x10892 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10893 = args[2][196 * steps + ((cycle - 1) & mask)];
assert(x10893 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10894 = args[2][197 * steps + ((cycle - 1) & mask)];
assert(x10894 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10895 = args[2][198 * steps + ((cycle - 1) & mask)];
assert(x10895 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10896 = args[2][199 * steps + ((cycle - 1) & mask)];
assert(x10896 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10897 = args[2][200 * steps + ((cycle - 1) & mask)];
assert(x10897 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10898 = args[2][201 * steps + ((cycle - 1) & mask)];
assert(x10898 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10899 = args[2][202 * steps + ((cycle - 1) & mask)];
assert(x10899 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10900 = args[2][203 * steps + ((cycle - 1) & mask)];
assert(x10900 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10901 = args[2][204 * steps + ((cycle - 1) & mask)];
assert(x10901 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10902 = args[2][205 * steps + ((cycle - 1) & mask)];
assert(x10902 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10903 = args[2][206 * steps + ((cycle - 1) & mask)];
assert(x10903 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10904 = args[2][207 * steps + ((cycle - 1) & mask)];
assert(x10904 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10905 = args[2][208 * steps + ((cycle - 1) & mask)];
assert(x10905 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10906 = args[2][209 * steps + ((cycle - 1) & mask)];
assert(x10906 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10907 = args[2][210 * steps + ((cycle - 1) & mask)];
assert(x10907 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10908 = args[2][211 * steps + ((cycle - 1) & mask)];
assert(x10908 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10909 = args[2][212 * steps + ((cycle - 1) & mask)];
assert(x10909 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10910 = args[2][213 * steps + ((cycle - 1) & mask)];
assert(x10910 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10911 = args[2][182 * steps + ((cycle - 2) & mask)];
assert(x10911 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10912 = args[2][183 * steps + ((cycle - 2) & mask)];
assert(x10912 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10913 = args[2][184 * steps + ((cycle - 2) & mask)];
assert(x10913 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10914 = args[2][185 * steps + ((cycle - 2) & mask)];
assert(x10914 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10915 = args[2][186 * steps + ((cycle - 2) & mask)];
assert(x10915 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10916 = args[2][187 * steps + ((cycle - 2) & mask)];
assert(x10916 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10917 = args[2][188 * steps + ((cycle - 2) & mask)];
assert(x10917 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10918 = args[2][189 * steps + ((cycle - 2) & mask)];
assert(x10918 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10919 = args[2][190 * steps + ((cycle - 2) & mask)];
assert(x10919 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10920 = args[2][191 * steps + ((cycle - 2) & mask)];
assert(x10920 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10921 = args[2][192 * steps + ((cycle - 2) & mask)];
assert(x10921 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10922 = args[2][193 * steps + ((cycle - 2) & mask)];
assert(x10922 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10923 = args[2][194 * steps + ((cycle - 2) & mask)];
assert(x10923 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10924 = args[2][195 * steps + ((cycle - 2) & mask)];
assert(x10924 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10925 = args[2][196 * steps + ((cycle - 2) & mask)];
assert(x10925 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10926 = args[2][197 * steps + ((cycle - 2) & mask)];
assert(x10926 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10927 = args[2][198 * steps + ((cycle - 2) & mask)];
assert(x10927 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10928 = args[2][199 * steps + ((cycle - 2) & mask)];
assert(x10928 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10929 = args[2][200 * steps + ((cycle - 2) & mask)];
assert(x10929 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10930 = args[2][201 * steps + ((cycle - 2) & mask)];
assert(x10930 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10931 = args[2][202 * steps + ((cycle - 2) & mask)];
assert(x10931 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10932 = args[2][203 * steps + ((cycle - 2) & mask)];
assert(x10932 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10933 = args[2][204 * steps + ((cycle - 2) & mask)];
assert(x10933 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10934 = args[2][205 * steps + ((cycle - 2) & mask)];
assert(x10934 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10935 = args[2][206 * steps + ((cycle - 2) & mask)];
assert(x10935 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10936 = args[2][207 * steps + ((cycle - 2) & mask)];
assert(x10936 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10937 = args[2][208 * steps + ((cycle - 2) & mask)];
assert(x10937 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10938 = args[2][209 * steps + ((cycle - 2) & mask)];
assert(x10938 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10939 = args[2][210 * steps + ((cycle - 2) & mask)];
assert(x10939 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10940 = args[2][211 * steps + ((cycle - 2) & mask)];
assert(x10940 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10941 = args[2][212 * steps + ((cycle - 2) & mask)];
assert(x10941 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10942 = args[2][213 * steps + ((cycle - 2) & mask)];
assert(x10942 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10943 = args[2][182 * steps + ((cycle - 3) & mask)];
assert(x10943 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10944 = args[2][183 * steps + ((cycle - 3) & mask)];
assert(x10944 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10945 = args[2][184 * steps + ((cycle - 3) & mask)];
assert(x10945 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10946 = args[2][185 * steps + ((cycle - 3) & mask)];
assert(x10946 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10947 = args[2][186 * steps + ((cycle - 3) & mask)];
assert(x10947 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10948 = args[2][187 * steps + ((cycle - 3) & mask)];
assert(x10948 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10949 = args[2][188 * steps + ((cycle - 3) & mask)];
assert(x10949 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10950 = args[2][189 * steps + ((cycle - 3) & mask)];
assert(x10950 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10951 = args[2][190 * steps + ((cycle - 3) & mask)];
assert(x10951 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10952 = args[2][191 * steps + ((cycle - 3) & mask)];
assert(x10952 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10953 = args[2][192 * steps + ((cycle - 3) & mask)];
assert(x10953 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10954 = args[2][193 * steps + ((cycle - 3) & mask)];
assert(x10954 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10955 = args[2][194 * steps + ((cycle - 3) & mask)];
assert(x10955 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10956 = args[2][195 * steps + ((cycle - 3) & mask)];
assert(x10956 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10957 = args[2][196 * steps + ((cycle - 3) & mask)];
assert(x10957 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10958 = args[2][197 * steps + ((cycle - 3) & mask)];
assert(x10958 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10959 = args[2][198 * steps + ((cycle - 3) & mask)];
assert(x10959 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10960 = args[2][199 * steps + ((cycle - 3) & mask)];
assert(x10960 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10961 = args[2][200 * steps + ((cycle - 3) & mask)];
assert(x10961 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10962 = args[2][201 * steps + ((cycle - 3) & mask)];
assert(x10962 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10963 = args[2][202 * steps + ((cycle - 3) & mask)];
assert(x10963 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10964 = args[2][203 * steps + ((cycle - 3) & mask)];
assert(x10964 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10965 = args[2][204 * steps + ((cycle - 3) & mask)];
assert(x10965 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10966 = args[2][205 * steps + ((cycle - 3) & mask)];
assert(x10966 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10967 = args[2][206 * steps + ((cycle - 3) & mask)];
assert(x10967 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10968 = args[2][207 * steps + ((cycle - 3) & mask)];
assert(x10968 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10969 = args[2][208 * steps + ((cycle - 3) & mask)];
assert(x10969 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10970 = args[2][209 * steps + ((cycle - 3) & mask)];
assert(x10970 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10971 = args[2][210 * steps + ((cycle - 3) & mask)];
assert(x10971 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10972 = args[2][211 * steps + ((cycle - 3) & mask)];
assert(x10972 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10973 = args[2][212 * steps + ((cycle - 3) & mask)];
assert(x10973 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10974 = args[2][213 * steps + ((cycle - 3) & mask)];
assert(x10974 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10975 = args[2][182 * steps + ((cycle - 4) & mask)];
assert(x10975 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10976 = args[2][183 * steps + ((cycle - 4) & mask)];
assert(x10976 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10977 = args[2][184 * steps + ((cycle - 4) & mask)];
assert(x10977 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10978 = args[2][185 * steps + ((cycle - 4) & mask)];
assert(x10978 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10979 = args[2][186 * steps + ((cycle - 4) & mask)];
assert(x10979 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10980 = args[2][187 * steps + ((cycle - 4) & mask)];
assert(x10980 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10981 = args[2][188 * steps + ((cycle - 4) & mask)];
assert(x10981 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10982 = args[2][189 * steps + ((cycle - 4) & mask)];
assert(x10982 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10983 = args[2][190 * steps + ((cycle - 4) & mask)];
assert(x10983 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10984 = args[2][191 * steps + ((cycle - 4) & mask)];
assert(x10984 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10985 = args[2][192 * steps + ((cycle - 4) & mask)];
assert(x10985 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10986 = args[2][193 * steps + ((cycle - 4) & mask)];
assert(x10986 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10987 = args[2][194 * steps + ((cycle - 4) & mask)];
assert(x10987 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10988 = args[2][195 * steps + ((cycle - 4) & mask)];
assert(x10988 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10989 = args[2][196 * steps + ((cycle - 4) & mask)];
assert(x10989 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10990 = args[2][197 * steps + ((cycle - 4) & mask)];
assert(x10990 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10991 = args[2][198 * steps + ((cycle - 4) & mask)];
assert(x10991 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10992 = args[2][199 * steps + ((cycle - 4) & mask)];
assert(x10992 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10993 = args[2][200 * steps + ((cycle - 4) & mask)];
assert(x10993 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10994 = args[2][201 * steps + ((cycle - 4) & mask)];
assert(x10994 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10995 = args[2][202 * steps + ((cycle - 4) & mask)];
assert(x10995 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10996 = args[2][203 * steps + ((cycle - 4) & mask)];
assert(x10996 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10997 = args[2][204 * steps + ((cycle - 4) & mask)];
assert(x10997 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10998 = args[2][205 * steps + ((cycle - 4) & mask)];
assert(x10998 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x10999 = args[2][206 * steps + ((cycle - 4) & mask)];
assert(x10999 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11000 = args[2][207 * steps + ((cycle - 4) & mask)];
assert(x11000 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11001 = args[2][208 * steps + ((cycle - 4) & mask)];
assert(x11001 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11002 = args[2][209 * steps + ((cycle - 4) & mask)];
assert(x11002 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11003 = args[2][210 * steps + ((cycle - 4) & mask)];
assert(x11003 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11004 = args[2][211 * steps + ((cycle - 4) & mask)];
assert(x11004 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11005 = args[2][212 * steps + ((cycle - 4) & mask)];
assert(x11005 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11006 = args[2][213 * steps + ((cycle - 4) & mask)];
assert(x11006 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11007 = args[2][82 * steps + ((cycle - 0) & mask)];
assert(x11007 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11008 = args[2][83 * steps + ((cycle - 0) & mask)];
assert(x11008 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11009 = args[2][84 * steps + ((cycle - 0) & mask)];
assert(x11009 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11010 = args[2][85 * steps + ((cycle - 0) & mask)];
assert(x11010 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11011 = args[2][86 * steps + ((cycle - 0) & mask)];
assert(x11011 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11012 = args[2][87 * steps + ((cycle - 0) & mask)];
assert(x11012 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11013 = args[2][88 * steps + ((cycle - 0) & mask)];
assert(x11013 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11014 = args[2][89 * steps + ((cycle - 0) & mask)];
assert(x11014 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11015 = args[2][90 * steps + ((cycle - 0) & mask)];
assert(x11015 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11016 = args[2][91 * steps + ((cycle - 0) & mask)];
assert(x11016 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11017 = args[2][19 * steps + ((cycle - 0) & mask)];
assert(x11017 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11018 = args[2][20 * steps + ((cycle - 0) & mask)];
assert(x11018 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement5/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11019 = args[2][21 * steps + ((cycle - 0) & mask)];
assert(x11019 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11020 = args[2][22 * steps + ((cycle - 0) & mask)];
assert(x11020 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement6/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11021 = args[2][23 * steps + ((cycle - 0) & mask)];
assert(x11021 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11022 = args[2][24 * steps + ((cycle - 0) & mask)];
assert(x11022 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11023 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x11023 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11024 = args[2][26 * steps + ((cycle - 0) & mask)];
assert(x11024 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement8/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11025 = args[2][27 * steps + ((cycle - 0) & mask)];
assert(x11025 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11026 = args[2][28 * steps + ((cycle - 0) & mask)];
assert(x11026 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement9/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11027 = args[2][29 * steps + ((cycle - 0) & mask)];
assert(x11027 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11028 = args[2][30 * steps + ((cycle - 0) & mask)];
assert(x11028 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement10/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11029 = args[2][31 * steps + ((cycle - 0) & mask)];
assert(x11029 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11030 = args[2][32 * steps + ((cycle - 0) & mask)];
assert(x11030 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement11/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11031 = args[2][33 * steps + ((cycle - 0) & mask)];
assert(x11031 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11032 = args[2][34 * steps + ((cycle - 0) & mask)];
assert(x11032 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement12/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11033 = args[2][35 * steps + ((cycle - 0) & mask)];
assert(x11033 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11034 = args[2][36 * steps + ((cycle - 0) & mask)];
assert(x11034 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement13/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11035 = args[2][37 * steps + ((cycle - 0) & mask)];
assert(x11035 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11036 = args[2][38 * steps + ((cycle - 0) & mask)];
assert(x11036 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement14/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11037 = args[2][39 * steps + ((cycle - 0) & mask)];
assert(x11037 != Fp::invalid());
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11038 = args[2][40 * steps + ((cycle - 0) & mask)];
assert(x11038 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x11039 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x11039 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x11040 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x11040 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x11041 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x11041 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x11042 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x11042 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":132:26)
auto x11043 = x11040 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":132:11)
auto x11044 = x11039 + x11043;
// loc("cirgen/circuit/rv32im/sha.cpp":132:61)
auto x11045 = x11042 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":132:46)
auto x11046 = x11041 + x11045;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11047 = x10764 + x10773;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11048 = x10764 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11049 = x11048 * x10773;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11050 = x11047 - x11049;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11051 = x10765 + x10774;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11052 = x10765 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11053 = x11052 * x10774;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11054 = x11051 - x11053;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11055 = x10766 + x10775;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11056 = x10766 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11057 = x11056 * x10775;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11058 = x11055 - x11057;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11059 = x10767 + x10776;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11060 = x10767 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11061 = x11060 * x10776;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11062 = x11059 - x11061;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11063 = x10768 + x10777;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11064 = x10768 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11065 = x11064 * x10777;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11066 = x11063 - x11065;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11067 = x10769 + x10778;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11068 = x10769 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11069 = x11068 * x10778;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11070 = x11067 - x11069;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11071 = x10770 + x10779;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11072 = x10770 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11073 = x11072 * x10779;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11074 = x11071 - x11073;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11075 = x10771 + x10780;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11076 = x10771 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11077 = x11076 * x10780;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11078 = x11075 - x11077;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11079 = x10772 + x10781;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11080 = x10772 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11081 = x11080 * x10781;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11082 = x11079 - x11081;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11083 = x10773 + x10782;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11084 = x10773 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11085 = x11084 * x10782;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11086 = x11083 - x11085;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11087 = x10774 + x10751;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11088 = x10774 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11089 = x11088 * x10751;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11090 = x11087 - x11089;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11091 = x10775 + x10752;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11092 = x10775 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11093 = x11092 * x10752;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11094 = x11091 - x11093;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11095 = x10776 + x10753;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11096 = x10776 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11097 = x11096 * x10753;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11098 = x11095 - x11097;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11099 = x10777 + x10754;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11100 = x10777 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11101 = x11100 * x10754;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11102 = x11099 - x11101;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11103 = x10778 + x10755;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11104 = x10778 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11105 = x11104 * x10755;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11106 = x11103 - x11105;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11107 = x10779 + x10756;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11108 = x10779 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11109 = x11108 * x10756;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11110 = x11107 - x11109;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11111 = x10780 + x10757;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11112 = x10780 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11113 = x11112 * x10757;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11114 = x11111 - x11113;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11115 = x10781 + x10758;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11116 = x10781 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11117 = x11116 * x10758;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11118 = x11115 - x11117;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11119 = x10782 + x10759;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11120 = x10782 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11121 = x11120 * x10759;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11122 = x11119 - x11121;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11123 = x10751 + x10760;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11124 = x10751 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11125 = x11124 * x10760;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11126 = x11123 - x11125;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11127 = x10752 + x10761;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11128 = x10752 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11129 = x11128 * x10761;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11130 = x11127 - x11129;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11131 = x10753 + x10762;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11132 = x10753 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11133 = x11132 * x10762;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11134 = x11131 - x11133;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11135 = x10754 + x10763;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11136 = x10754 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11137 = x11136 * x10763;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11138 = x11135 - x11137;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11139 = x10755 + x10764;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11140 = x10755 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11141 = x11140 * x10764;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11142 = x11139 - x11141;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11143 = x10756 + x10765;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11144 = x10756 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11145 = x11144 * x10765;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11146 = x11143 - x11145;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11147 = x10757 + x10766;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11148 = x10757 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11149 = x11148 * x10766;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11150 = x11147 - x11149;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11151 = x10758 + x10767;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11152 = x10758 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11153 = x11152 * x10767;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11154 = x11151 - x11153;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11155 = x10759 + x10768;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11156 = x10759 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11157 = x11156 * x10768;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11158 = x11155 - x11157;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11159 = x10760 + x10769;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11160 = x10760 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11161 = x11160 * x10769;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11162 = x11159 - x11161;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11163 = x10761 + x10770;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11164 = x10761 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11165 = x11164 * x10770;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11166 = x11163 - x11165;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11167 = x10762 + x10771;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11168 = x10762 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11169 = x11168 * x10771;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11170 = x11167 - x11169;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11171 = x10763 + x10772;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11172 = x10763 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11173 = x11172 * x10772;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11174 = x11171 - x11173;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11175 = x10753 + x11050;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11176 = x11132 * x11050;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11177 = x11175 - x11176;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11178 = x10754 + x11054;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11179 = x11136 * x11054;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11180 = x11178 - x11179;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11181 = x10755 + x11058;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11182 = x11140 * x11058;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11183 = x11181 - x11182;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11184 = x10756 + x11062;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11185 = x11144 * x11062;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11186 = x11184 - x11185;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11187 = x10757 + x11066;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11188 = x11148 * x11066;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11189 = x11187 - x11188;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11190 = x10758 + x11070;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11191 = x11152 * x11070;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11192 = x11190 - x11191;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11193 = x10759 + x11074;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11194 = x11156 * x11074;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11195 = x11193 - x11194;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11196 = x10760 + x11078;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11197 = x11160 * x11078;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11198 = x11196 - x11197;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11199 = x10761 + x11082;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11200 = x11164 * x11082;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11201 = x11199 - x11200;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11202 = x10762 + x11086;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11203 = x11168 * x11086;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11204 = x11202 - x11203;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11205 = x10763 + x11090;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11206 = x11172 * x11090;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11207 = x11205 - x11206;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11208 = x10764 + x11094;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11209 = x11048 * x11094;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11210 = x11208 - x11209;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11211 = x10765 + x11098;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11212 = x11052 * x11098;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11213 = x11211 - x11212;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11214 = x10766 + x11102;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11215 = x11056 * x11102;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11216 = x11214 - x11215;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11217 = x10767 + x11106;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11218 = x11060 * x11106;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11219 = x11217 - x11218;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11220 = x10768 + x11110;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11221 = x11064 * x11110;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11222 = x11220 - x11221;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11223 = x10769 + x11114;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11224 = x11068 * x11114;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11225 = x11223 - x11224;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11226 = x10770 + x11118;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11227 = x11072 * x11118;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11228 = x11226 - x11227;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11229 = x10771 + x11122;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11230 = x11076 * x11122;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11231 = x11229 - x11230;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11232 = x10772 + x11126;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11233 = x11080 * x11126;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11234 = x11232 - x11233;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11235 = x10773 + x11130;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11236 = x11084 * x11130;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11237 = x11235 - x11236;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11238 = x10774 + x11134;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11239 = x11088 * x11134;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11240 = x11238 - x11239;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11241 = x10775 + x11138;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11242 = x11092 * x11138;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11243 = x11241 - x11242;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11244 = x10776 + x11142;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11245 = x11096 * x11142;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11246 = x11244 - x11245;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11247 = x10777 + x11146;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11248 = x11100 * x11146;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11249 = x11247 - x11248;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11250 = x10778 + x11150;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11251 = x11104 * x11150;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11252 = x11250 - x11251;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11253 = x10779 + x11154;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11254 = x11108 * x11154;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11255 = x11253 - x11254;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11256 = x10780 + x11158;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11257 = x11112 * x11158;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11258 = x11256 - x11257;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11259 = x10781 + x11162;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11260 = x11116 * x11162;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11261 = x11259 - x11260;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11262 = x10782 + x11166;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11263 = x11120 * x11166;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11264 = x11262 - x11263;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11265 = x10751 + x11170;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11266 = x11124 * x11170;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11267 = x11265 - x11266;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11268 = x10752 + x11174;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11269 = x11128 * x11174;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11270 = x11268 - x11269;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11271 = x10890 + x10904;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11272 = x10890 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11273 = x11272 * x10904;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11274 = x11271 - x11273;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11275 = x10891 + x10905;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11276 = x10891 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11277 = x11276 * x10905;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11278 = x11275 - x11277;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11279 = x10892 + x10906;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11280 = x10892 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11281 = x11280 * x10906;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11282 = x11279 - x11281;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11283 = x10893 + x10907;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11284 = x10893 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11285 = x11284 * x10907;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11286 = x11283 - x11285;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11287 = x10894 + x10908;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11288 = x10894 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11289 = x11288 * x10908;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11290 = x11287 - x11289;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11291 = x10895 + x10909;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11292 = x10895 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11293 = x11292 * x10909;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11294 = x11291 - x11293;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11295 = x10896 + x10910;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11296 = x10896 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11297 = x11296 * x10910;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11298 = x11295 - x11297;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11299 = x10897 + x10879;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11300 = x10897 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11301 = x11300 * x10879;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11302 = x11299 - x11301;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11303 = x10898 + x10880;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11304 = x10898 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11305 = x11304 * x10880;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11306 = x11303 - x11305;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11307 = x10899 + x10881;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11308 = x10899 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11309 = x11308 * x10881;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11310 = x11307 - x11309;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11311 = x10900 + x10882;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11312 = x10900 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11313 = x11312 * x10882;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11314 = x11311 - x11313;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11315 = x10901 + x10883;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11316 = x10901 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11317 = x11316 * x10883;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11318 = x11315 - x11317;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11319 = x10902 + x10884;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11320 = x10902 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11321 = x11320 * x10884;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11322 = x11319 - x11321;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11323 = x10903 + x10885;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11324 = x10903 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11325 = x11324 * x10885;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11326 = x11323 - x11325;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11327 = x10904 + x10886;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11328 = x10904 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11329 = x11328 * x10886;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11330 = x11327 - x11329;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11331 = x10905 + x10887;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11332 = x10905 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11333 = x11332 * x10887;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11334 = x11331 - x11333;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11335 = x10906 + x10888;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11336 = x10906 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11337 = x11336 * x10888;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11338 = x11335 - x11337;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11339 = x10907 + x10889;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11340 = x10907 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11341 = x11340 * x10889;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11342 = x11339 - x11341;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11343 = x10908 + x10890;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11344 = x10908 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11345 = x11344 * x10890;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11346 = x11343 - x11345;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11347 = x10909 + x10891;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11348 = x10909 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11349 = x11348 * x10891;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11350 = x11347 - x11349;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11351 = x10910 + x10892;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11352 = x10910 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11353 = x11352 * x10892;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11354 = x11351 - x11353;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11355 = x10879 + x10893;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11356 = x10879 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11357 = x11356 * x10893;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11358 = x11355 - x11357;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11359 = x10880 + x10894;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11360 = x10880 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11361 = x11360 * x10894;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11362 = x11359 - x11361;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11363 = x10881 + x10895;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11364 = x10881 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11365 = x11364 * x10895;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11366 = x11363 - x11365;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11367 = x10882 + x10896;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11368 = x10882 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11369 = x11368 * x10896;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11370 = x11367 - x11369;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11371 = x10883 + x10897;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11372 = x10883 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11373 = x11372 * x10897;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11374 = x11371 - x11373;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11375 = x10884 + x10898;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11376 = x10884 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11377 = x11376 * x10898;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11378 = x11375 - x11377;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11379 = x10885 + x10899;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11380 = x10885 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11381 = x11380 * x10899;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11382 = x11379 - x11381;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11383 = x10886 + x10900;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11384 = x10886 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11385 = x11384 * x10900;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11386 = x11383 - x11385;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11387 = x10887 + x10901;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11388 = x10887 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11389 = x11388 * x10901;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11390 = x11387 - x11389;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11391 = x10888 + x10902;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11392 = x10888 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11393 = x11392 * x10902;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11394 = x11391 - x11393;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11395 = x10889 + x10903;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11396 = x10889 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11397 = x11396 * x10903;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11398 = x11395 - x11397;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11399 = x10885 + x11274;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11400 = x11380 * x11274;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11401 = x11399 - x11400;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11402 = x10886 + x11278;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11403 = x11384 * x11278;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11404 = x11402 - x11403;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11405 = x10887 + x11282;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11406 = x11388 * x11282;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11407 = x11405 - x11406;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11408 = x10888 + x11286;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11409 = x11392 * x11286;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11410 = x11408 - x11409;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11411 = x10889 + x11290;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11412 = x11396 * x11290;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11413 = x11411 - x11412;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11414 = x10890 + x11294;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11415 = x11272 * x11294;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11416 = x11414 - x11415;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11417 = x10891 + x11298;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11418 = x11276 * x11298;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11419 = x11417 - x11418;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11420 = x10892 + x11302;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11421 = x11280 * x11302;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11422 = x11420 - x11421;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11423 = x10893 + x11306;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11424 = x11284 * x11306;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11425 = x11423 - x11424;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11426 = x10894 + x11310;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11427 = x11288 * x11310;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11428 = x11426 - x11427;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11429 = x10895 + x11314;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11430 = x11292 * x11314;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11431 = x11429 - x11430;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11432 = x10896 + x11318;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11433 = x11296 * x11318;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11434 = x11432 - x11433;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11435 = x10897 + x11322;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11436 = x11300 * x11322;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11437 = x11435 - x11436;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11438 = x10898 + x11326;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11439 = x11304 * x11326;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11440 = x11438 - x11439;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11441 = x10899 + x11330;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11442 = x11308 * x11330;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11443 = x11441 - x11442;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11444 = x10900 + x11334;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11445 = x11312 * x11334;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11446 = x11444 - x11445;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11447 = x10901 + x11338;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11448 = x11316 * x11338;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11449 = x11447 - x11448;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11450 = x10902 + x11342;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11451 = x11320 * x11342;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11452 = x11450 - x11451;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11453 = x10903 + x11346;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11454 = x11324 * x11346;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11455 = x11453 - x11454;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11456 = x10904 + x11350;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11457 = x11328 * x11350;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11458 = x11456 - x11457;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11459 = x10905 + x11354;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11460 = x11332 * x11354;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11461 = x11459 - x11460;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11462 = x10906 + x11358;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11463 = x11336 * x11358;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11464 = x11462 - x11463;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11465 = x10907 + x11362;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11466 = x11340 * x11362;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11467 = x11465 - x11466;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11468 = x10908 + x11366;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11469 = x11344 * x11366;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11470 = x11468 - x11469;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11471 = x10909 + x11370;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11472 = x11348 * x11370;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11473 = x11471 - x11472;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11474 = x10910 + x11374;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11475 = x11352 * x11374;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11476 = x11474 - x11475;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11477 = x10879 + x11378;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11478 = x11356 * x11378;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11479 = x11477 - x11478;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11480 = x10880 + x11382;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11481 = x11360 * x11382;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11482 = x11480 - x11481;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11483 = x10881 + x11386;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11484 = x11364 * x11386;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11485 = x11483 - x11484;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11486 = x10882 + x11390;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11487 = x11368 * x11390;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11488 = x11486 - x11487;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11489 = x10883 + x11394;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11490 = x11372 * x11394;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11491 = x11489 - x11490;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11492 = x10884 + x11398;
// loc("cirgen/circuit/rv32im/sha.cpp":47:28)
auto x11493 = x11376 * x11398;
// loc("cirgen/circuit/rv32im/sha.cpp":47:14)
auto x11494 = x11492 - x11493;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11495 = x11008 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11496 = x11007 + x11495;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11497 = x11009 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11498 = x11496 + x11497;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11499 = x11010 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11500 = x11498 + x11499;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11501 = x11011 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11502 = x11500 + x11501;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11503 = x11012 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11504 = x11502 + x11503;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11505 = x11013 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11506 = x11504 + x11505;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11507 = x11014 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11508 = x11506 + x11507;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11509 = x11015 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11510 = x11508 + x11509;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11511 = x11016 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11512 = x11510 + x11511;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11513 = x11017 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11514 = x11512 + x11513;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11515 = x11018 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11516 = x11514 + x11515;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11517 = x11019 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11518 = x11516 + x11517;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11519 = x11020 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11520 = x11518 + x11519;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11521 = x11021 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11522 = x11520 + x11521;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11523 = x11022 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11524 = x11522 + x11523;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11525 = x11024 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11526 = x11023 + x11525;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11527 = x11025 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11528 = x11526 + x11527;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11529 = x11026 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11530 = x11528 + x11529;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11531 = x11027 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11532 = x11530 + x11531;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11533 = x11028 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11534 = x11532 + x11533;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11535 = x11029 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11536 = x11534 + x11535;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11537 = x11030 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11538 = x11536 + x11537;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11539 = x11031 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11540 = x11538 + x11539;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11541 = x11032 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11542 = x11540 + x11541;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11543 = x11033 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11544 = x11542 + x11543;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11545 = x11034 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11546 = x11544 + x11545;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11547 = x11035 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11548 = x11546 + x11547;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11549 = x11036 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11550 = x11548 + x11549;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11551 = x11037 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11552 = x11550 + x11551;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11553 = x11038 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11554 = x11552 + x11553;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11555 = x10976 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11556 = x10975 + x11555;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11557 = x10977 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11558 = x11556 + x11557;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11559 = x10978 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11560 = x11558 + x11559;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11561 = x10979 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11562 = x11560 + x11561;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11563 = x10980 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11564 = x11562 + x11563;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11565 = x10981 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11566 = x11564 + x11565;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11567 = x10982 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11568 = x11566 + x11567;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11569 = x10983 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11570 = x11568 + x11569;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11571 = x10984 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11572 = x11570 + x11571;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11573 = x10985 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11574 = x11572 + x11573;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11575 = x10986 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11576 = x11574 + x11575;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11577 = x10987 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11578 = x11576 + x11577;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11579 = x10988 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11580 = x11578 + x11579;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11581 = x10989 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11582 = x11580 + x11581;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11583 = x10990 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11584 = x11582 + x11583;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11585 = x10992 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11586 = x10991 + x11585;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11587 = x10993 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11588 = x11586 + x11587;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11589 = x10994 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11590 = x11588 + x11589;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11591 = x10995 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11592 = x11590 + x11591;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11593 = x10996 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11594 = x11592 + x11593;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11595 = x10997 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11596 = x11594 + x11595;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11597 = x10998 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11598 = x11596 + x11597;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11599 = x10999 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11600 = x11598 + x11599;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11601 = x11000 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11602 = x11600 + x11601;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11603 = x11001 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11604 = x11602 + x11603;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11605 = x11002 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11606 = x11604 + x11605;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11607 = x11003 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11608 = x11606 + x11607;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11609 = x11004 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11610 = x11608 + x11609;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11611 = x11005 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11612 = x11610 + x11611;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11613 = x11006 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11614 = x11612 + x11613;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11615 = x10879 * x10911;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11616 = x102 - x10879;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11617 = x11616 * x10943;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11618 = x11615 + x11617;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11619 = x10880 * x10912;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11620 = x102 - x10880;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11621 = x11620 * x10944;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11622 = x11619 + x11621;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11623 = x10881 * x10913;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11624 = x102 - x10881;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11625 = x11624 * x10945;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11626 = x11623 + x11625;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11627 = x10882 * x10914;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11628 = x102 - x10882;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11629 = x11628 * x10946;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11630 = x11627 + x11629;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11631 = x10883 * x10915;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11632 = x102 - x10883;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11633 = x11632 * x10947;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11634 = x11631 + x11633;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11635 = x10884 * x10916;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11636 = x102 - x10884;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11637 = x11636 * x10948;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11638 = x11635 + x11637;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11639 = x10885 * x10917;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11640 = x102 - x10885;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11641 = x11640 * x10949;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11642 = x11639 + x11641;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11643 = x10886 * x10918;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11644 = x102 - x10886;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11645 = x11644 * x10950;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11646 = x11643 + x11645;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11647 = x10887 * x10919;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11648 = x102 - x10887;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11649 = x11648 * x10951;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11650 = x11647 + x11649;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11651 = x10888 * x10920;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11652 = x102 - x10888;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11653 = x11652 * x10952;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11654 = x11651 + x11653;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11655 = x10889 * x10921;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11656 = x102 - x10889;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11657 = x11656 * x10953;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11658 = x11655 + x11657;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11659 = x10890 * x10922;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11660 = x102 - x10890;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11661 = x11660 * x10954;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11662 = x11659 + x11661;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11663 = x10891 * x10923;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11664 = x102 - x10891;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11665 = x11664 * x10955;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11666 = x11663 + x11665;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11667 = x10892 * x10924;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11668 = x102 - x10892;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11669 = x11668 * x10956;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11670 = x11667 + x11669;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11671 = x10893 * x10925;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11672 = x102 - x10893;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11673 = x11672 * x10957;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11674 = x11671 + x11673;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11675 = x10894 * x10926;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11676 = x102 - x10894;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11677 = x11676 * x10958;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11678 = x11675 + x11677;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11679 = x10895 * x10927;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11680 = x102 - x10895;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11681 = x11680 * x10959;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11682 = x11679 + x11681;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11683 = x10896 * x10928;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11684 = x102 - x10896;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11685 = x11684 * x10960;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11686 = x11683 + x11685;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11687 = x10897 * x10929;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11688 = x102 - x10897;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11689 = x11688 * x10961;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11690 = x11687 + x11689;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11691 = x10898 * x10930;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11692 = x102 - x10898;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11693 = x11692 * x10962;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11694 = x11691 + x11693;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11695 = x10899 * x10931;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11696 = x102 - x10899;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11697 = x11696 * x10963;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11698 = x11695 + x11697;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11699 = x10900 * x10932;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11700 = x102 - x10900;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11701 = x11700 * x10964;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11702 = x11699 + x11701;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11703 = x10901 * x10933;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11704 = x102 - x10901;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11705 = x11704 * x10965;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11706 = x11703 + x11705;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11707 = x10902 * x10934;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11708 = x102 - x10902;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11709 = x11708 * x10966;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11710 = x11707 + x11709;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11711 = x10903 * x10935;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11712 = x102 - x10903;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11713 = x11712 * x10967;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11714 = x11711 + x11713;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11715 = x10904 * x10936;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11716 = x102 - x10904;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11717 = x11716 * x10968;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11718 = x11715 + x11717;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11719 = x10905 * x10937;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11720 = x102 - x10905;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11721 = x11720 * x10969;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11722 = x11719 + x11721;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11723 = x10906 * x10938;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11724 = x102 - x10906;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11725 = x11724 * x10970;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11726 = x11723 + x11725;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11727 = x10907 * x10939;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11728 = x102 - x10907;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11729 = x11728 * x10971;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11730 = x11727 + x11729;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11731 = x10908 * x10940;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11732 = x102 - x10908;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11733 = x11732 * x10972;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11734 = x11731 + x11733;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11735 = x10909 * x10941;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11736 = x102 - x10909;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11737 = x11736 * x10973;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11738 = x11735 + x11737;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11739 = x10910 * x10942;
// loc("cirgen/circuit/rv32im/sha.cpp":64:29)
auto x11740 = x102 - x10910;
// loc("cirgen/circuit/rv32im/sha.cpp":64:28)
auto x11741 = x11740 * x10974;
// loc("cirgen/circuit/rv32im/sha.cpp":64:14)
auto x11742 = x11739 + x11741;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11743 = x11622 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11744 = x11618 + x11743;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11745 = x11626 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11746 = x11744 + x11745;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11747 = x11630 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11748 = x11746 + x11747;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11749 = x11634 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11750 = x11748 + x11749;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11751 = x11638 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11752 = x11750 + x11751;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11753 = x11642 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11754 = x11752 + x11753;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11755 = x11646 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11756 = x11754 + x11755;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11757 = x11650 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11758 = x11756 + x11757;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11759 = x11654 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11760 = x11758 + x11759;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11761 = x11658 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11762 = x11760 + x11761;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11763 = x11662 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11764 = x11762 + x11763;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11765 = x11666 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11766 = x11764 + x11765;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11767 = x11670 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11768 = x11766 + x11767;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11769 = x11674 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11770 = x11768 + x11769;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11771 = x11678 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11772 = x11770 + x11771;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11773 = x11686 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11774 = x11682 + x11773;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11775 = x11690 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11776 = x11774 + x11775;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11777 = x11694 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11778 = x11776 + x11777;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11779 = x11698 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11780 = x11778 + x11779;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11781 = x11702 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11782 = x11780 + x11781;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11783 = x11706 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11784 = x11782 + x11783;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11785 = x11710 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11786 = x11784 + x11785;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11787 = x11714 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11788 = x11786 + x11787;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11789 = x11718 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11790 = x11788 + x11789;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11791 = x11722 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11792 = x11790 + x11791;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11793 = x11726 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11794 = x11792 + x11793;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11795 = x11730 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11796 = x11794 + x11795;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11797 = x11734 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11798 = x11796 + x11797;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11799 = x11738 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11800 = x11798 + x11799;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11801 = x11742 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11802 = x11800 + x11801;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11803 = x11404 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11804 = x11401 + x11803;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11805 = x11407 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11806 = x11804 + x11805;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11807 = x11410 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11808 = x11806 + x11807;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11809 = x11413 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11810 = x11808 + x11809;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11811 = x11416 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11812 = x11810 + x11811;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11813 = x11419 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11814 = x11812 + x11813;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11815 = x11422 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11816 = x11814 + x11815;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11817 = x11425 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11818 = x11816 + x11817;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11819 = x11428 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11820 = x11818 + x11819;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11821 = x11431 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11822 = x11820 + x11821;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11823 = x11434 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11824 = x11822 + x11823;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11825 = x11437 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11826 = x11824 + x11825;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11827 = x11440 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11828 = x11826 + x11827;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11829 = x11443 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11830 = x11828 + x11829;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11831 = x11446 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11832 = x11830 + x11831;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11833 = x11452 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11834 = x11449 + x11833;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11835 = x11455 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11836 = x11834 + x11835;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11837 = x11458 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11838 = x11836 + x11837;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11839 = x11461 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11840 = x11838 + x11839;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11841 = x11464 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11842 = x11840 + x11841;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11843 = x11467 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11844 = x11842 + x11843;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11845 = x11470 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11846 = x11844 + x11845;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11847 = x11473 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11848 = x11846 + x11847;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11849 = x11476 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11850 = x11848 + x11849;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11851 = x11479 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11852 = x11850 + x11851;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11853 = x11482 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11854 = x11852 + x11853;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11855 = x11485 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11856 = x11854 + x11855;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11857 = x11488 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11858 = x11856 + x11857;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11859 = x11491 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11860 = x11858 + x11859;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x11861 = x11494 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x11862 = x11860 + x11861;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x11863 = x11772 + x11832;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x11864 = x11802 + x11862;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x11865 = x11584 + x11863;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x11866 = x11614 + x11864;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x11867 = x11044 + x11865;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x11868 = x11046 + x11866;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x11869 = x11524 + x11867;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x11870 = x11554 + x11868;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11871 = x10751 * x10783;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x11872 = x102 - x10815;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11873 = x11871 * x11872;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x11874 = x102 - x10783;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11875 = x10751 * x11874;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11876 = x11875 * x10815;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11877 = x11873 + x11876;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x11878 = x102 - x10751;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11879 = x11878 * x10783;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11880 = x11879 * x10815;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11881 = x11877 + x11880;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x11882 = x11871 * x10815;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11883 = x11881 + x11882;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11884 = x10752 * x10784;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x11885 = x102 - x10816;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11886 = x11884 * x11885;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x11887 = x102 - x10784;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11888 = x10752 * x11887;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11889 = x11888 * x10816;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11890 = x11886 + x11889;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x11891 = x102 - x10752;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11892 = x11891 * x10784;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11893 = x11892 * x10816;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11894 = x11890 + x11893;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x11895 = x11884 * x10816;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11896 = x11894 + x11895;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11897 = x10753 * x10785;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x11898 = x102 - x10817;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11899 = x11897 * x11898;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x11900 = x102 - x10785;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11901 = x10753 * x11900;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11902 = x11901 * x10817;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11903 = x11899 + x11902;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x11904 = x102 - x10753;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11905 = x11904 * x10785;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11906 = x11905 * x10817;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11907 = x11903 + x11906;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x11908 = x11897 * x10817;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11909 = x11907 + x11908;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11910 = x10754 * x10786;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x11911 = x102 - x10818;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11912 = x11910 * x11911;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x11913 = x102 - x10786;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11914 = x10754 * x11913;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11915 = x11914 * x10818;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11916 = x11912 + x11915;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x11917 = x102 - x10754;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11918 = x11917 * x10786;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11919 = x11918 * x10818;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11920 = x11916 + x11919;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x11921 = x11910 * x10818;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11922 = x11920 + x11921;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11923 = x10755 * x10787;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x11924 = x102 - x10819;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11925 = x11923 * x11924;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x11926 = x102 - x10787;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11927 = x10755 * x11926;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11928 = x11927 * x10819;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11929 = x11925 + x11928;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x11930 = x102 - x10755;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11931 = x11930 * x10787;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11932 = x11931 * x10819;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11933 = x11929 + x11932;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x11934 = x11923 * x10819;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11935 = x11933 + x11934;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11936 = x10756 * x10788;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x11937 = x102 - x10820;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11938 = x11936 * x11937;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x11939 = x102 - x10788;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11940 = x10756 * x11939;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11941 = x11940 * x10820;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11942 = x11938 + x11941;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x11943 = x102 - x10756;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11944 = x11943 * x10788;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11945 = x11944 * x10820;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11946 = x11942 + x11945;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x11947 = x11936 * x10820;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11948 = x11946 + x11947;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11949 = x10757 * x10789;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x11950 = x102 - x10821;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11951 = x11949 * x11950;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x11952 = x102 - x10789;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11953 = x10757 * x11952;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11954 = x11953 * x10821;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11955 = x11951 + x11954;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x11956 = x102 - x10757;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11957 = x11956 * x10789;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11958 = x11957 * x10821;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11959 = x11955 + x11958;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x11960 = x11949 * x10821;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11961 = x11959 + x11960;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11962 = x10758 * x10790;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x11963 = x102 - x10822;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11964 = x11962 * x11963;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x11965 = x102 - x10790;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11966 = x10758 * x11965;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11967 = x11966 * x10822;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11968 = x11964 + x11967;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x11969 = x102 - x10758;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11970 = x11969 * x10790;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11971 = x11970 * x10822;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11972 = x11968 + x11971;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x11973 = x11962 * x10822;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11974 = x11972 + x11973;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11975 = x10759 * x10791;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x11976 = x102 - x10823;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11977 = x11975 * x11976;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x11978 = x102 - x10791;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11979 = x10759 * x11978;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11980 = x11979 * x10823;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11981 = x11977 + x11980;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x11982 = x102 - x10759;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11983 = x11982 * x10791;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11984 = x11983 * x10823;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11985 = x11981 + x11984;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x11986 = x11975 * x10823;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11987 = x11985 + x11986;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11988 = x10760 * x10792;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x11989 = x102 - x10824;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11990 = x11988 * x11989;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x11991 = x102 - x10792;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11992 = x10760 * x11991;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x11993 = x11992 * x10824;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11994 = x11990 + x11993;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x11995 = x102 - x10760;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11996 = x11995 * x10792;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x11997 = x11996 * x10824;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x11998 = x11994 + x11997;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x11999 = x11988 * x10824;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12000 = x11998 + x11999;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12001 = x10761 * x10793;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12002 = x102 - x10825;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12003 = x12001 * x12002;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12004 = x102 - x10793;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12005 = x10761 * x12004;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12006 = x12005 * x10825;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12007 = x12003 + x12006;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12008 = x102 - x10761;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12009 = x12008 * x10793;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12010 = x12009 * x10825;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12011 = x12007 + x12010;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12012 = x12001 * x10825;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12013 = x12011 + x12012;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12014 = x10762 * x10794;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12015 = x102 - x10826;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12016 = x12014 * x12015;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12017 = x102 - x10794;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12018 = x10762 * x12017;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12019 = x12018 * x10826;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12020 = x12016 + x12019;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12021 = x102 - x10762;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12022 = x12021 * x10794;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12023 = x12022 * x10826;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12024 = x12020 + x12023;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12025 = x12014 * x10826;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12026 = x12024 + x12025;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12027 = x10763 * x10795;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12028 = x102 - x10827;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12029 = x12027 * x12028;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12030 = x102 - x10795;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12031 = x10763 * x12030;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12032 = x12031 * x10827;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12033 = x12029 + x12032;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12034 = x102 - x10763;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12035 = x12034 * x10795;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12036 = x12035 * x10827;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12037 = x12033 + x12036;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12038 = x12027 * x10827;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12039 = x12037 + x12038;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12040 = x10764 * x10796;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12041 = x102 - x10828;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12042 = x12040 * x12041;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12043 = x102 - x10796;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12044 = x10764 * x12043;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12045 = x12044 * x10828;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12046 = x12042 + x12045;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12047 = x102 - x10764;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12048 = x12047 * x10796;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12049 = x12048 * x10828;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12050 = x12046 + x12049;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12051 = x12040 * x10828;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12052 = x12050 + x12051;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12053 = x10765 * x10797;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12054 = x102 - x10829;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12055 = x12053 * x12054;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12056 = x102 - x10797;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12057 = x10765 * x12056;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12058 = x12057 * x10829;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12059 = x12055 + x12058;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12060 = x102 - x10765;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12061 = x12060 * x10797;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12062 = x12061 * x10829;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12063 = x12059 + x12062;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12064 = x12053 * x10829;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12065 = x12063 + x12064;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12066 = x10766 * x10798;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12067 = x102 - x10830;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12068 = x12066 * x12067;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12069 = x102 - x10798;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12070 = x10766 * x12069;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12071 = x12070 * x10830;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12072 = x12068 + x12071;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12073 = x102 - x10766;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12074 = x12073 * x10798;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12075 = x12074 * x10830;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12076 = x12072 + x12075;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12077 = x12066 * x10830;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12078 = x12076 + x12077;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12079 = x10767 * x10799;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12080 = x102 - x10831;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12081 = x12079 * x12080;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12082 = x102 - x10799;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12083 = x10767 * x12082;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12084 = x12083 * x10831;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12085 = x12081 + x12084;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12086 = x102 - x10767;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12087 = x12086 * x10799;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12088 = x12087 * x10831;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12089 = x12085 + x12088;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12090 = x12079 * x10831;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12091 = x12089 + x12090;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12092 = x10768 * x10800;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12093 = x102 - x10832;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12094 = x12092 * x12093;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12095 = x102 - x10800;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12096 = x10768 * x12095;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12097 = x12096 * x10832;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12098 = x12094 + x12097;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12099 = x102 - x10768;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12100 = x12099 * x10800;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12101 = x12100 * x10832;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12102 = x12098 + x12101;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12103 = x12092 * x10832;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12104 = x12102 + x12103;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12105 = x10769 * x10801;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12106 = x102 - x10833;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12107 = x12105 * x12106;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12108 = x102 - x10801;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12109 = x10769 * x12108;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12110 = x12109 * x10833;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12111 = x12107 + x12110;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12112 = x102 - x10769;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12113 = x12112 * x10801;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12114 = x12113 * x10833;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12115 = x12111 + x12114;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12116 = x12105 * x10833;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12117 = x12115 + x12116;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12118 = x10770 * x10802;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12119 = x102 - x10834;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12120 = x12118 * x12119;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12121 = x102 - x10802;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12122 = x10770 * x12121;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12123 = x12122 * x10834;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12124 = x12120 + x12123;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12125 = x102 - x10770;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12126 = x12125 * x10802;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12127 = x12126 * x10834;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12128 = x12124 + x12127;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12129 = x12118 * x10834;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12130 = x12128 + x12129;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12131 = x10771 * x10803;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12132 = x102 - x10835;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12133 = x12131 * x12132;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12134 = x102 - x10803;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12135 = x10771 * x12134;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12136 = x12135 * x10835;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12137 = x12133 + x12136;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12138 = x102 - x10771;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12139 = x12138 * x10803;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12140 = x12139 * x10835;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12141 = x12137 + x12140;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12142 = x12131 * x10835;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12143 = x12141 + x12142;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12144 = x10772 * x10804;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12145 = x102 - x10836;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12146 = x12144 * x12145;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12147 = x102 - x10804;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12148 = x10772 * x12147;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12149 = x12148 * x10836;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12150 = x12146 + x12149;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12151 = x102 - x10772;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12152 = x12151 * x10804;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12153 = x12152 * x10836;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12154 = x12150 + x12153;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12155 = x12144 * x10836;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12156 = x12154 + x12155;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12157 = x10773 * x10805;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12158 = x102 - x10837;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12159 = x12157 * x12158;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12160 = x102 - x10805;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12161 = x10773 * x12160;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12162 = x12161 * x10837;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12163 = x12159 + x12162;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12164 = x102 - x10773;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12165 = x12164 * x10805;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12166 = x12165 * x10837;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12167 = x12163 + x12166;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12168 = x12157 * x10837;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12169 = x12167 + x12168;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12170 = x10774 * x10806;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12171 = x102 - x10838;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12172 = x12170 * x12171;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12173 = x102 - x10806;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12174 = x10774 * x12173;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12175 = x12174 * x10838;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12176 = x12172 + x12175;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12177 = x102 - x10774;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12178 = x12177 * x10806;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12179 = x12178 * x10838;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12180 = x12176 + x12179;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12181 = x12170 * x10838;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12182 = x12180 + x12181;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12183 = x10775 * x10807;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12184 = x102 - x10839;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12185 = x12183 * x12184;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12186 = x102 - x10807;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12187 = x10775 * x12186;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12188 = x12187 * x10839;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12189 = x12185 + x12188;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12190 = x102 - x10775;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12191 = x12190 * x10807;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12192 = x12191 * x10839;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12193 = x12189 + x12192;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12194 = x12183 * x10839;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12195 = x12193 + x12194;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12196 = x10776 * x10808;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12197 = x102 - x10840;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12198 = x12196 * x12197;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12199 = x102 - x10808;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12200 = x10776 * x12199;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12201 = x12200 * x10840;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12202 = x12198 + x12201;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12203 = x102 - x10776;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12204 = x12203 * x10808;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12205 = x12204 * x10840;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12206 = x12202 + x12205;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12207 = x12196 * x10840;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12208 = x12206 + x12207;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12209 = x10777 * x10809;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12210 = x102 - x10841;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12211 = x12209 * x12210;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12212 = x102 - x10809;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12213 = x10777 * x12212;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12214 = x12213 * x10841;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12215 = x12211 + x12214;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12216 = x102 - x10777;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12217 = x12216 * x10809;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12218 = x12217 * x10841;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12219 = x12215 + x12218;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12220 = x12209 * x10841;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12221 = x12219 + x12220;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12222 = x10778 * x10810;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12223 = x102 - x10842;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12224 = x12222 * x12223;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12225 = x102 - x10810;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12226 = x10778 * x12225;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12227 = x12226 * x10842;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12228 = x12224 + x12227;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12229 = x102 - x10778;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12230 = x12229 * x10810;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12231 = x12230 * x10842;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12232 = x12228 + x12231;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12233 = x12222 * x10842;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12234 = x12232 + x12233;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12235 = x10779 * x10811;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12236 = x102 - x10843;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12237 = x12235 * x12236;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12238 = x102 - x10811;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12239 = x10779 * x12238;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12240 = x12239 * x10843;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12241 = x12237 + x12240;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12242 = x102 - x10779;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12243 = x12242 * x10811;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12244 = x12243 * x10843;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12245 = x12241 + x12244;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12246 = x12235 * x10843;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12247 = x12245 + x12246;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12248 = x10780 * x10812;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12249 = x102 - x10844;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12250 = x12248 * x12249;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12251 = x102 - x10812;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12252 = x10780 * x12251;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12253 = x12252 * x10844;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12254 = x12250 + x12253;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12255 = x102 - x10780;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12256 = x12255 * x10812;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12257 = x12256 * x10844;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12258 = x12254 + x12257;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12259 = x12248 * x10844;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12260 = x12258 + x12259;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12261 = x10781 * x10813;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12262 = x102 - x10845;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12263 = x12261 * x12262;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12264 = x102 - x10813;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12265 = x10781 * x12264;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12266 = x12265 * x10845;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12267 = x12263 + x12266;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12268 = x102 - x10781;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12269 = x12268 * x10813;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12270 = x12269 * x10845;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12271 = x12267 + x12270;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12272 = x12261 * x10845;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12273 = x12271 + x12272;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12274 = x10782 * x10814;
// loc("cirgen/circuit/rv32im/sha.cpp":55:29)
auto x12275 = x102 - x10846;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12276 = x12274 * x12275;
// loc("cirgen/circuit/rv32im/sha.cpp":55:49)
auto x12277 = x102 - x10814;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12278 = x10782 * x12277;
// loc("cirgen/circuit/rv32im/sha.cpp":55:41)
auto x12279 = x12278 * x10846;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12280 = x12276 + x12279;
// loc("cirgen/circuit/rv32im/sha.cpp":55:69)
auto x12281 = x102 - x10782;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12282 = x12281 * x10814;
// loc("cirgen/circuit/rv32im/sha.cpp":55:68)
auto x12283 = x12282 * x10846;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12284 = x12280 + x12283;
// loc("cirgen/circuit/rv32im/sha.cpp":56:14)
auto x12285 = x12274 * x10846;
// loc("cirgen/circuit/rv32im/sha.cpp":55:14)
auto x12286 = x12284 + x12285;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12287 = x11896 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12288 = x11883 + x12287;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12289 = x11909 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12290 = x12288 + x12289;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12291 = x11922 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12292 = x12290 + x12291;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12293 = x11935 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12294 = x12292 + x12293;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12295 = x11948 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12296 = x12294 + x12295;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12297 = x11961 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12298 = x12296 + x12297;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12299 = x11974 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12300 = x12298 + x12299;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12301 = x11987 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12302 = x12300 + x12301;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12303 = x12000 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12304 = x12302 + x12303;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12305 = x12013 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12306 = x12304 + x12305;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12307 = x12026 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12308 = x12306 + x12307;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12309 = x12039 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12310 = x12308 + x12309;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12311 = x12052 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12312 = x12310 + x12311;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12313 = x12065 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12314 = x12312 + x12313;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12315 = x12078 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12316 = x12314 + x12315;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12317 = x12104 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12318 = x12091 + x12317;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12319 = x12117 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12320 = x12318 + x12319;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12321 = x12130 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12322 = x12320 + x12321;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12323 = x12143 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12324 = x12322 + x12323;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12325 = x12156 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12326 = x12324 + x12325;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12327 = x12169 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12328 = x12326 + x12327;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12329 = x12182 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12330 = x12328 + x12329;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12331 = x12195 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12332 = x12330 + x12331;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12333 = x12208 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12334 = x12332 + x12333;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12335 = x12221 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12336 = x12334 + x12335;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12337 = x12234 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12338 = x12336 + x12337;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12339 = x12247 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12340 = x12338 + x12339;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12341 = x12260 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12342 = x12340 + x12341;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12343 = x12273 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12344 = x12342 + x12343;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12345 = x12286 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12346 = x12344 + x12345;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12347 = x11180 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12348 = x11177 + x12347;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12349 = x11183 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12350 = x12348 + x12349;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12351 = x11186 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12352 = x12350 + x12351;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12353 = x11189 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12354 = x12352 + x12353;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12355 = x11192 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12356 = x12354 + x12355;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12357 = x11195 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12358 = x12356 + x12357;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12359 = x11198 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12360 = x12358 + x12359;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12361 = x11201 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12362 = x12360 + x12361;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12363 = x11204 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12364 = x12362 + x12363;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12365 = x11207 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12366 = x12364 + x12365;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12367 = x11210 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12368 = x12366 + x12367;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12369 = x11213 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12370 = x12368 + x12369;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12371 = x11216 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12372 = x12370 + x12371;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12373 = x11219 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12374 = x12372 + x12373;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12375 = x11222 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12376 = x12374 + x12375;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12377 = x11228 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12378 = x11225 + x12377;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12379 = x11231 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12380 = x12378 + x12379;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12381 = x11234 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12382 = x12380 + x12381;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12383 = x11237 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12384 = x12382 + x12383;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12385 = x11240 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12386 = x12384 + x12385;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12387 = x11243 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12388 = x12386 + x12387;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12389 = x11246 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12390 = x12388 + x12389;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12391 = x11249 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12392 = x12390 + x12391;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12393 = x11252 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12394 = x12392 + x12393;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12395 = x11255 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12396 = x12394 + x12395;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12397 = x11258 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12398 = x12396 + x12397;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12399 = x11261 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12400 = x12398 + x12399;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12401 = x11264 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12402 = x12400 + x12401;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12403 = x11267 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12404 = x12402 + x12403;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12405 = x11270 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12406 = x12404 + x12405;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x12407 = x12316 + x12376;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x12408 = x12346 + x12406;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x12409 = x11869 + x12407;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x12410 = x11870 + x12408;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12411 = x10848 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12412 = x10847 + x12411;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12413 = x10849 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12414 = x12412 + x12413;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12415 = x10850 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12416 = x12414 + x12415;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12417 = x10851 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12418 = x12416 + x12417;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12419 = x10852 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12420 = x12418 + x12419;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12421 = x10853 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12422 = x12420 + x12421;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12423 = x10854 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12424 = x12422 + x12423;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12425 = x10855 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12426 = x12424 + x12425;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12427 = x10856 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12428 = x12426 + x12427;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12429 = x10857 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12430 = x12428 + x12429;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12431 = x10858 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12432 = x12430 + x12431;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12433 = x10859 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12434 = x12432 + x12433;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12435 = x10860 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12436 = x12434 + x12435;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12437 = x10861 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12438 = x12436 + x12437;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12439 = x10862 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12440 = x12438 + x12439;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12441 = x10864 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12442 = x10863 + x12441;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12443 = x10865 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12444 = x12442 + x12443;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12445 = x10866 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12446 = x12444 + x12445;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12447 = x10867 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12448 = x12446 + x12447;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12449 = x10868 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12450 = x12448 + x12449;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12451 = x10869 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12452 = x12450 + x12451;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12453 = x10870 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12454 = x12452 + x12453;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12455 = x10871 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12456 = x12454 + x12455;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12457 = x10872 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12458 = x12456 + x12457;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12459 = x10873 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12460 = x12458 + x12459;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12461 = x10874 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12462 = x12460 + x12461;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12463 = x10875 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12464 = x12462 + x12463;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12465 = x10876 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12466 = x12464 + x12465;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12467 = x10877 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12468 = x12466 + x12467;
// loc("cirgen/circuit/rv32im/sha.cpp":74:25)
auto x12469 = x10878 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":74:16)
auto x12470 = x12468 + x12469;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x12471 = x11869 + x12440;
// loc("cirgen/circuit/rv32im/sha.cpp":83:14)
auto x12472 = x11870 + x12470;
// loc("cirgen/circuit/rv32im/sha.cpp":488:5)
{
auto& reg = args[2][144 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12409);
reg = x12409;
}
// loc("cirgen/circuit/rv32im/sha.cpp":489:5)
{
auto& reg = args[2][146 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12471);
reg = x12471;
}
// loc("cirgen/circuit/rv32im/sha.cpp":488:5)
{
auto& reg = args[2][145 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12410);
reg = x12410;
}
// loc("cirgen/circuit/rv32im/sha.cpp":489:5)
{
auto& reg = args[2][147 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12472);
reg = x12472;
}
if (x8504 != 0) {
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg6"("cirgen/circuit/rv32im/sha.cpp":140:11))
auto x12473 = args[2][144 * steps + ((cycle - 0) & mask)];
assert(x12473 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg7"("cirgen/circuit/rv32im/sha.cpp":140:26))
auto x12474 = args[2][145 * steps + ((cycle - 0) & mask)];
assert(x12474 != Fp::invalid());
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12475 = Fp(x12473.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][150 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12475);
reg = x12475;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12476 = Fp(x12473.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12477 = x12476 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][151 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12477);
reg = x12477;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12478 = Fp(x12473.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12479 = x12478 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][152 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12479);
reg = x12479;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12480 = Fp(x12473.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12481 = x12480 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][153 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12481);
reg = x12481;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12482 = Fp(x12473.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12483 = x12482 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][154 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12483);
reg = x12483;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12484 = Fp(x12473.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12485 = x12484 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][155 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12485);
reg = x12485;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12486 = Fp(x12473.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12487 = x12486 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][156 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12487);
reg = x12487;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12488 = Fp(x12473.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12489 = x12488 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][157 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12489);
reg = x12489;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12490 = Fp(x12473.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12491 = x12490 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][158 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12491);
reg = x12491;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12492 = Fp(x12473.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12493 = x12492 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][159 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12493);
reg = x12493;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12494 = Fp(x12473.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12495 = x12494 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][160 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12495);
reg = x12495;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12496 = Fp(x12473.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12497 = x12496 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12497);
reg = x12497;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12498 = Fp(x12473.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12499 = x12498 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12499);
reg = x12499;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12500 = Fp(x12473.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12501 = x12500 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12501);
reg = x12501;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12502 = Fp(x12473.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12503 = x12502 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12503);
reg = x12503;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12504 = Fp(x12473.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12505 = x12504 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12505);
reg = x12505;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12506 = args[2][150 * steps + ((cycle - 0) & mask)];
assert(x12506 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12507 = args[2][151 * steps + ((cycle - 0) & mask)];
assert(x12507 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12508 = x12507 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12509 = x12506 + x12508;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12510 = args[2][152 * steps + ((cycle - 0) & mask)];
assert(x12510 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12511 = x12510 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12512 = x12509 + x12511;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12513 = args[2][153 * steps + ((cycle - 0) & mask)];
assert(x12513 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12514 = x12513 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12515 = x12512 + x12514;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12516 = args[2][154 * steps + ((cycle - 0) & mask)];
assert(x12516 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12517 = x12516 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12518 = x12515 + x12517;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit8/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12519 = args[2][155 * steps + ((cycle - 0) & mask)];
assert(x12519 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12520 = x12519 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12521 = x12518 + x12520;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit9/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12522 = args[2][156 * steps + ((cycle - 0) & mask)];
assert(x12522 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12523 = x12522 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12524 = x12521 + x12523;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit10/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12525 = args[2][157 * steps + ((cycle - 0) & mask)];
assert(x12525 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12526 = x12525 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12527 = x12524 + x12526;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit11/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12528 = args[2][158 * steps + ((cycle - 0) & mask)];
assert(x12528 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12529 = x12528 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12530 = x12527 + x12529;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12531 = args[2][159 * steps + ((cycle - 0) & mask)];
assert(x12531 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12532 = x12531 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12533 = x12530 + x12532;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12534 = args[2][160 * steps + ((cycle - 0) & mask)];
assert(x12534 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12535 = x12534 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12536 = x12533 + x12535;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit14/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12537 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x12537 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12538 = x12537 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12539 = x12536 + x12538;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit15/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12540 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x12540 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12541 = x12540 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12542 = x12539 + x12541;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit16/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12543 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x12543 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12544 = x12543 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12545 = x12542 + x12544;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit17/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12546 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x12546 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12547 = x12546 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12548 = x12545 + x12547;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit18/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12549 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x12549 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12550 = x12549 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12551 = x12548 + x12550;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x12552 = x12473 - x12551;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x12553 = x12552 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":122:26)
auto x12554 = Fp(x12553.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][76 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12554);
reg = x12554;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12555 = args[2][76 * steps + ((cycle - 0) & mask)];
assert(x12555 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":123:20)
auto x12556 = x12553 - x12555;
// loc("cirgen/circuit/rv32im/sha.cpp":123:19)
auto x12557 = x12556 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":124:20)
auto x12558 = x102 - x12557;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
auto x12559 = x12557 * x12558;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
if (x12559 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:124");
// loc("cirgen/circuit/rv32im/sha.cpp":125:32)
auto x12560 = x12474 + x12553;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12561 = Fp(x12560.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12561);
reg = x12561;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12562 = Fp(x12560.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12563 = x12562 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12563);
reg = x12563;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12564 = Fp(x12560.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12565 = x12564 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12565);
reg = x12565;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12566 = Fp(x12560.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12567 = x12566 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][169 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12567);
reg = x12567;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12568 = Fp(x12560.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12569 = x12568 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][170 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12569);
reg = x12569;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12570 = Fp(x12560.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12571 = x12570 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][171 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12571);
reg = x12571;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12572 = Fp(x12560.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12573 = x12572 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][172 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12573);
reg = x12573;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12574 = Fp(x12560.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12575 = x12574 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12575);
reg = x12575;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12576 = Fp(x12560.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12577 = x12576 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][174 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12577);
reg = x12577;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12578 = Fp(x12560.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12579 = x12578 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][175 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12579);
reg = x12579;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12580 = Fp(x12560.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12581 = x12580 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12581);
reg = x12581;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12582 = Fp(x12560.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12583 = x12582 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12583);
reg = x12583;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12584 = Fp(x12560.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12585 = x12584 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12585);
reg = x12585;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12586 = Fp(x12560.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12587 = x12586 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12587);
reg = x12587;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12588 = Fp(x12560.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12589 = x12588 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12589);
reg = x12589;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12590 = Fp(x12560.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12591 = x12590 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12591);
reg = x12591;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit19/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12592 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x12592 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit20/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12593 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x12593 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12594 = x12593 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12595 = x12592 + x12594;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit21/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12596 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x12596 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12597 = x12596 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12598 = x12595 + x12597;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit22/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12599 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x12599 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12600 = x12599 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12601 = x12598 + x12600;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit23/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12602 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x12602 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12603 = x12602 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12604 = x12601 + x12603;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit24/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12605 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x12605 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12606 = x12605 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12607 = x12604 + x12606;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit25/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12608 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x12608 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12609 = x12608 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12610 = x12607 + x12609;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit26/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12611 = args[2][173 * steps + ((cycle - 0) & mask)];
assert(x12611 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12612 = x12611 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12613 = x12610 + x12612;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit27/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12614 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x12614 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12615 = x12614 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12616 = x12613 + x12615;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit28/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12617 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x12617 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12618 = x12617 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12619 = x12616 + x12618;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit29/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12620 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x12620 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12621 = x12620 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12622 = x12619 + x12621;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit30/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12623 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x12623 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12624 = x12623 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12625 = x12622 + x12624;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit31/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12626 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x12626 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12627 = x12626 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12628 = x12625 + x12627;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit32/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12629 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x12629 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12630 = x12629 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12631 = x12628 + x12630;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit33/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12632 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x12632 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12633 = x12632 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12634 = x12631 + x12633;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit34/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12635 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x12635 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12636 = x12635 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12637 = x12634 + x12636;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x12638 = x12560 - x12637;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x12639 = x12638 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":126:27)
auto x12640 = Fp(x12639.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][77 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12640);
reg = x12640;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12641 = args[2][77 * steps + ((cycle - 0) & mask)];
assert(x12641 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":127:21)
auto x12642 = x12639 - x12641;
// loc("cirgen/circuit/rv32im/sha.cpp":127:20)
auto x12643 = x12642 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":128:21)
auto x12644 = x102 - x12643;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
auto x12645 = x12643 * x12644;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
if (x12645 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:128");
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg8"("cirgen/circuit/rv32im/sha.cpp":140:11))
auto x12646 = args[2][146 * steps + ((cycle - 0) & mask)];
assert(x12646 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg9"("cirgen/circuit/rv32im/sha.cpp":140:26))
auto x12647 = args[2][147 * steps + ((cycle - 0) & mask)];
assert(x12647 != Fp::invalid());
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12648 = Fp(x12646.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12648);
reg = x12648;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12649 = Fp(x12646.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12650 = x12649 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12650);
reg = x12650;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12651 = Fp(x12646.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12652 = x12651 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12652);
reg = x12652;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12653 = Fp(x12646.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12654 = x12653 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12654);
reg = x12654;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12655 = Fp(x12646.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12656 = x12655 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12656);
reg = x12656;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12657 = Fp(x12646.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12658 = x12657 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][187 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12658);
reg = x12658;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12659 = Fp(x12646.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12660 = x12659 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][188 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12660);
reg = x12660;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12661 = Fp(x12646.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12662 = x12661 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][189 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12662);
reg = x12662;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12663 = Fp(x12646.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12664 = x12663 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][190 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12664);
reg = x12664;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12665 = Fp(x12646.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12666 = x12665 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][191 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12666);
reg = x12666;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12667 = Fp(x12646.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12668 = x12667 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][192 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12668);
reg = x12668;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12669 = Fp(x12646.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12670 = x12669 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][193 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12670);
reg = x12670;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12671 = Fp(x12646.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12672 = x12671 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][194 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12672);
reg = x12672;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12673 = Fp(x12646.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12674 = x12673 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][195 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12674);
reg = x12674;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12675 = Fp(x12646.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12676 = x12675 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][196 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12676);
reg = x12676;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12677 = Fp(x12646.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12678 = x12677 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][197 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12678);
reg = x12678;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit35/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12679 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x12679 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit36/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12680 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x12680 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12681 = x12680 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12682 = x12679 + x12681;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit37/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12683 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x12683 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12684 = x12683 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12685 = x12682 + x12684;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit38/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12686 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x12686 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12687 = x12686 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12688 = x12685 + x12687;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit39/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12689 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x12689 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12690 = x12689 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12691 = x12688 + x12690;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit40/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12692 = args[2][187 * steps + ((cycle - 0) & mask)];
assert(x12692 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12693 = x12692 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12694 = x12691 + x12693;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit41/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12695 = args[2][188 * steps + ((cycle - 0) & mask)];
assert(x12695 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12696 = x12695 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12697 = x12694 + x12696;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit42/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12698 = args[2][189 * steps + ((cycle - 0) & mask)];
assert(x12698 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12699 = x12698 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12700 = x12697 + x12699;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit43/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12701 = args[2][190 * steps + ((cycle - 0) & mask)];
assert(x12701 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12702 = x12701 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12703 = x12700 + x12702;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit44/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12704 = args[2][191 * steps + ((cycle - 0) & mask)];
assert(x12704 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12705 = x12704 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12706 = x12703 + x12705;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit45/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12707 = args[2][192 * steps + ((cycle - 0) & mask)];
assert(x12707 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12708 = x12707 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12709 = x12706 + x12708;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit46/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12710 = args[2][193 * steps + ((cycle - 0) & mask)];
assert(x12710 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12711 = x12710 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12712 = x12709 + x12711;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit47/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12713 = args[2][194 * steps + ((cycle - 0) & mask)];
assert(x12713 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12714 = x12713 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12715 = x12712 + x12714;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit48/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12716 = args[2][195 * steps + ((cycle - 0) & mask)];
assert(x12716 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12717 = x12716 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12718 = x12715 + x12717;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit49/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12719 = args[2][196 * steps + ((cycle - 0) & mask)];
assert(x12719 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12720 = x12719 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12721 = x12718 + x12720;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit50/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12722 = args[2][197 * steps + ((cycle - 0) & mask)];
assert(x12722 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12723 = x12722 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12724 = x12721 + x12723;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x12725 = x12646 - x12724;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x12726 = x12725 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":122:26)
auto x12727 = Fp(x12726.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][78 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12727);
reg = x12727;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12728 = args[2][78 * steps + ((cycle - 0) & mask)];
assert(x12728 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":123:20)
auto x12729 = x12726 - x12728;
// loc("cirgen/circuit/rv32im/sha.cpp":123:19)
auto x12730 = x12729 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":124:20)
auto x12731 = x102 - x12730;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
auto x12732 = x12730 * x12731;
// loc("cirgen/circuit/rv32im/sha.cpp":124:7)
if (x12732 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:124");
// loc("cirgen/circuit/rv32im/sha.cpp":125:32)
auto x12733 = x12647 + x12726;
{
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12734 = Fp(x12733.asUInt32() & x102.asUInt32());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][198 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12734);
reg = x12734;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12735 = Fp(x12733.asUInt32() & x99.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12736 = x12735 * x63;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][199 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12736);
reg = x12736;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12737 = Fp(x12733.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12738 = x12737 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][200 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12738);
reg = x12738;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12739 = Fp(x12733.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12740 = x12739 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][201 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12740);
reg = x12740;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12741 = Fp(x12733.asUInt32() & x66.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12742 = x12741 * x65;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][202 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12742);
reg = x12742;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12743 = Fp(x12733.asUInt32() & x68.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12744 = x12743 * x67;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][203 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12744);
reg = x12744;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12745 = Fp(x12733.asUInt32() & x62.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12746 = x12745 * x61;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][204 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12746);
reg = x12746;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12747 = Fp(x12733.asUInt32() & x71.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12748 = x12747 * x70;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][205 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12748);
reg = x12748;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12749 = Fp(x12733.asUInt32() & x97.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12750 = x12749 * x96;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][206 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12750);
reg = x12750;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12751 = Fp(x12733.asUInt32() & x28.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12752 = x12751 * x27;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][207 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12752);
reg = x12752;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12753 = Fp(x12733.asUInt32() & x29.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12754 = x12753 * x26;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][208 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12754);
reg = x12754;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12755 = Fp(x12733.asUInt32() & x25.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12756 = x12755 * x24;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][209 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12756);
reg = x12756;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12757 = Fp(x12733.asUInt32() & x23.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12758 = x12757 * x22;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][210 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12758);
reg = x12758;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12759 = Fp(x12733.asUInt32() & x21.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12760 = x12759 * x20;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][211 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12760);
reg = x12760;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12761 = Fp(x12733.asUInt32() & x43.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12762 = x12761 * x19;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][212 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12762);
reg = x12762;
}
// loc("cirgen/circuit/rv32im/sha.cpp":104:29)
auto x12763 = Fp(x12733.asUInt32() & x18.asUInt32());
// loc("cirgen/circuit/rv32im/sha.cpp":104:28)
auto x12764 = x12763 * x17;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][213 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12764);
reg = x12764;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit51/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12765 = args[2][198 * steps + ((cycle - 0) & mask)];
assert(x12765 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit52/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12766 = args[2][199 * steps + ((cycle - 0) & mask)];
assert(x12766 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12767 = x12766 * x99;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12768 = x12765 + x12767;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit53/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12769 = args[2][200 * steps + ((cycle - 0) & mask)];
assert(x12769 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12770 = x12769 * x85;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12771 = x12768 + x12770;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit54/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12772 = args[2][201 * steps + ((cycle - 0) & mask)];
assert(x12772 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12773 = x12772 * x77;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12774 = x12771 + x12773;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit55/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12775 = args[2][202 * steps + ((cycle - 0) & mask)];
assert(x12775 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12776 = x12775 * x66;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12777 = x12774 + x12776;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit56/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12778 = args[2][203 * steps + ((cycle - 0) & mask)];
assert(x12778 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12779 = x12778 * x68;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12780 = x12777 + x12779;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit57/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12781 = args[2][204 * steps + ((cycle - 0) & mask)];
assert(x12781 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12782 = x12781 * x62;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12783 = x12780 + x12782;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit58/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12784 = args[2][205 * steps + ((cycle - 0) & mask)];
assert(x12784 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12785 = x12784 * x71;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12786 = x12783 + x12785;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit59/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12787 = args[2][206 * steps + ((cycle - 0) & mask)];
assert(x12787 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12788 = x12787 * x97;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12789 = x12786 + x12788;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit60/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12790 = args[2][207 * steps + ((cycle - 0) & mask)];
assert(x12790 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12791 = x12790 * x28;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12792 = x12789 + x12791;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit61/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12793 = args[2][208 * steps + ((cycle - 0) & mask)];
assert(x12793 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12794 = x12793 * x29;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12795 = x12792 + x12794;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit62/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12796 = args[2][209 * steps + ((cycle - 0) & mask)];
assert(x12796 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12797 = x12796 * x25;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12798 = x12795 + x12797;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit63/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12799 = args[2][210 * steps + ((cycle - 0) & mask)];
assert(x12799 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12800 = x12799 * x23;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12801 = x12798 + x12800;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit64/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12802 = args[2][211 * steps + ((cycle - 0) & mask)];
assert(x12802 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12803 = x12802 * x21;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12804 = x12801 + x12803;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit65/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12805 = args[2][212 * steps + ((cycle - 0) & mask)];
assert(x12805 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12806 = x12805 * x43;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12807 = x12804 + x12806;
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit66/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12808 = args[2][213 * steps + ((cycle - 0) & mask)];
assert(x12808 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":109:21)
auto x12809 = x12808 * x18;
// loc("cirgen/circuit/rv32im/sha.cpp":109:13)
auto x12810 = x12807 + x12809;
// loc("cirgen/circuit/rv32im/sha.cpp":111:16)
auto x12811 = x12733 - x12810;
// loc("cirgen/circuit/rv32im/sha.cpp":111:15)
auto x12812 = x12811 * x16;
{
// loc("cirgen/circuit/rv32im/sha.cpp":126:27)
auto x12813 = Fp(x12812.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12813);
reg = x12813;
}
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Twit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12814 = args[2][79 * steps + ((cycle - 0) & mask)];
assert(x12814 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":127:21)
auto x12815 = x12812 - x12814;
// loc("cirgen/circuit/rv32im/sha.cpp":127:20)
auto x12816 = x12815 * x83;
// loc("cirgen/circuit/rv32im/sha.cpp":128:21)
auto x12817 = x102 - x12816;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
auto x12818 = x12816 * x12817;
// loc("cirgen/circuit/rv32im/sha.cpp":128:7)
if (x12818 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/sha.cpp:128");
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12819 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x12819 != Fp::invalid());
if (x12819 != 0) {
if (x8511 != 0) {
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg2"("cirgen/circuit/rv32im/sha.cpp":430:38))
auto x12820 = args[2][133 * steps + ((cycle - 1) & mask)];
assert(x12820 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":430:7)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12820);
reg = x12820;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg3"("cirgen/circuit/rv32im/sha.cpp":431:38))
auto x12821 = args[2][134 * steps + ((cycle - 1) & mask)];
assert(x12821 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":431:7)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12821);
reg = x12821;
}
// loc("cirgen/circuit/rv32im/sha.cpp":432:7)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
if (x8512 != 0) {
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg2"("cirgen/circuit/rv32im/sha.cpp":436:51))
auto x12822 = args[2][133 * steps + ((cycle - 1) & mask)];
assert(x12822 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":436:51)
auto x12823 = x12822 + x66;
// loc("cirgen/circuit/rv32im/sha.cpp":436:7)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12823);
reg = x12823;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg3"("cirgen/circuit/rv32im/sha.cpp":437:51))
auto x12824 = args[2][134 * steps + ((cycle - 1) & mask)];
assert(x12824 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":437:51)
auto x12825 = x12824 + x66;
// loc("cirgen/circuit/rv32im/sha.cpp":437:7)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12825);
reg = x12825;
}
// loc("cirgen/circuit/rv32im/sha.cpp":438:7)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x75);
reg = x75;
}
}
}
// loc("cirgen/circuit/rv32im/sha.cpp":441:27)
auto x12826 = x102 - x12819;
if (x12826 != 0) {
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg2"("cirgen/circuit/rv32im/sha.cpp":442:36))
auto x12827 = args[2][133 * steps + ((cycle - 1) & mask)];
assert(x12827 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":442:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12827);
reg = x12827;
}
// loc("Top/Mux/4/Mux/11/ShaCycle/Reg3"("cirgen/circuit/rv32im/sha.cpp":443:36))
auto x12828 = args[2][134 * steps + ((cycle - 1) & mask)];
assert(x12828 != Fp::invalid());
// loc("cirgen/circuit/rv32im/sha.cpp":443:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12828);
reg = x12828;
}
// loc("cirgen/circuit/rv32im/sha.cpp":444:5)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x74);
reg = x74;
}
}
}
// loc("Top/Mux/4/OneHot/Reg12"("./cirgen/components/mux.h":37:25))
auto x12829 = args[2][106 * steps + ((cycle - 0) & mask)];
assert(x12829 != Fp::invalid());
if (x12829 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12830 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x12830 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":257:41)
auto x12831 = x603 * x83;
{
host_args.at(0) = x12831;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x12832 = host_outs.at(0);
auto x12833 = host_outs.at(1);
auto x12834 = host_outs.at(2);
auto x12835 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12832);
reg = x12832;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12833);
reg = x12833;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12834);
reg = x12834;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12835);
reg = x12835;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12836 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x12836 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x12837 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x12837 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x12838 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x12838 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x12839 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x12839 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12831);
reg = x12831;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12836);
reg = x12836;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12837);
reg = x12837;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12838);
reg = x12838;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12839);
reg = x12839;
}
// loc("Top/Mux/4/OneHot/Reg8"("cirgen/circuit/rv32im/ffpu.cpp":259:70))
auto x12840 = args[2][102 * steps + ((cycle - 1) & mask)];
assert(x12840 != Fp::invalid());
if (x12840 != 0) {
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12841 = args[2][132 * steps + ((cycle - 1) & mask)];
assert(x12841 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x12842 = args[2][133 * steps + ((cycle - 1) & mask)];
assert(x12842 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x12843 = args[2][134 * steps + ((cycle - 1) & mask)];
assert(x12843 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x12844 = args[2][135 * steps + ((cycle - 1) & mask)];
assert(x12844 != Fp::invalid());
// loc("./cirgen/components/u32.h":25:12)
auto x12845 = x12842 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x12846 = x12841 + x12845;
// loc("./cirgen/components/u32.h":26:12)
auto x12847 = x12843 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x12848 = x12846 + x12847;
// loc("./cirgen/components/u32.h":27:12)
auto x12849 = x12844 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x12850 = x12848 + x12849;
// loc("cirgen/circuit/rv32im/ffpu.cpp":265:27)
auto x12851 = x12850 * x83;
// loc("cirgen/circuit/rv32im/ffpu.cpp":265:5)
{
auto& reg = args[2][175 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12851);
reg = x12851;
}
{
host_args.at(0) = x31;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x12852 = host_outs.at(0);
auto x12853 = host_outs.at(1);
auto x12854 = host_outs.at(2);
auto x12855 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12852);
reg = x12852;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12853);
reg = x12853;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12854);
reg = x12854;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12855);
reg = x12855;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12856 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x12856 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x12857 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x12857 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x12858 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x12858 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x12859 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x12859 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x31);
reg = x31;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12856);
reg = x12856;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12857);
reg = x12857;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12858);
reg = x12858;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12859);
reg = x12859;
}
// loc("./cirgen/components/u32.h":25:12)
auto x12860 = x12857 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x12861 = x12856 + x12860;
// loc("./cirgen/components/u32.h":26:12)
auto x12862 = x12858 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x12863 = x12861 + x12862;
// loc("./cirgen/components/u32.h":27:12)
auto x12864 = x12859 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x12865 = x12863 + x12864;
// loc("cirgen/circuit/rv32im/ffpu.cpp":268:5)
{
auto& reg = args[2][169 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12865);
reg = x12865;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("Top/Mux/4/Mux/8/Mux/4/Reg"("cirgen/circuit/rv32im/ffpu.cpp":272:50))
auto x12866 = args[2][181 * steps + ((cycle - 1) & mask)];
assert(x12866 != Fp::invalid());
host_args.at(0) = x12866;
host(ctx, "log", "origPc: %u", host_args.data(), 1, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ffpu.cpp":274:24)
auto x12867 = x12866 + x85;
// loc("cirgen/circuit/rv32im/ffpu.cpp":274:5)
{
auto& reg = args[2][174 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12867);
reg = x12867;
}
// loc("Top/Mux/4/Mux/12/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12868 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x12868 != Fp::invalid());
host_args.at(0) = x12850;
host_args.at(1) = x12868;
host_args.at(2) = x12866;
host(ctx, "log", "FFPU INIT, baseAddr = %u, haltPos = %u, origPc = %u", host_args.data(), 3, host_outs.data(), 0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":283:5)
{
auto& reg = args[2][172 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":284:5)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
{
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12869 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x12869 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12870 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x12870 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12871 = x12870 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x12872 = x12869 + x12871;
// loc("Top/Mux/4/Mux/12/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12873 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x12873 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12874 = x12873 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x12875 = x12872 + x12874;
// loc("Top/Mux/4/Mux/12/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12876 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x12876 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12877 = x12876 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x12878 = x12875 + x12877;
// loc("Top/Mux/4/Mux/12/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12879 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x12879 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12880 = x12879 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x12881 = x12878 + x12880;
// loc("Top/Mux/4/Mux/12/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12882 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x12882 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12883 = x12882 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x12884 = x12881 + x12883;
// loc("Top/Mux/4/Mux/12/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12885 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x12885 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12886 = x12885 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x12887 = x12884 + x12886;
// loc("./cirgen/components/onehot.h":38:8)
if (x12887 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":289:22)
auto x12888 = x102 - x12840;
if (x12888 != 0) {
// loc("Top/Mux/4/Mux/12/Reg4"("cirgen/circuit/rv32im/ffpu.cpp":291:58))
auto x12889 = args[2][175 * steps + ((cycle - 1) & mask)];
assert(x12889 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":291:5)
{
auto& reg = args[2][175 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12889);
reg = x12889;
}
// loc("Top/Mux/4/Mux/12/Reg"("cirgen/circuit/rv32im/ffpu.cpp":292:40))
auto x12890 = args[2][169 * steps + ((cycle - 1) & mask)];
assert(x12890 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":292:5)
{
auto& reg = args[2][169 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12890);
reg = x12890;
}
// loc("Top/Mux/4/Mux/12/Reg3"("cirgen/circuit/rv32im/ffpu.cpp":293:52))
auto x12891 = args[2][174 * steps + ((cycle - 1) & mask)];
assert(x12891 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":293:5)
{
auto& reg = args[2][174 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12891);
reg = x12891;
}
// loc("Top/Mux/4/Mux/12/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12892 = args[2][179 * steps + ((cycle - 1) & mask)];
assert(x12892 != Fp::invalid());
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][178 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12892);
reg = x12892;
}
// loc("Top/Mux/4/Mux/12/Reg2"("cirgen/circuit/rv32im/ffpu.cpp":296:60))
auto x12893 = args[2][173 * steps + ((cycle - 1) & mask)];
assert(x12893 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":296:5)
{
auto& reg = args[2][172 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12893);
reg = x12893;
}
}
{
// loc("cirgen/circuit/rv32im/ffpu.cpp":311:20)
auto x12894 = Fp(x12836.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][78 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12894);
reg = x12894;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":312:23)
auto x12895 = Fp(x12836.asUInt32() & x85.asUInt32());
// loc("cirgen/circuit/rv32im/ffpu.cpp":312:22)
auto x12896 = x12895 * x83;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][177 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12896);
reg = x12896;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":313:25)
auto x12897 = Fp(x12836.asUInt32() & x77.asUInt32());
// loc("cirgen/circuit/rv32im/ffpu.cpp":313:24)
auto x12898 = x12897 * x64;
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][176 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12898);
reg = x12898;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":314:21)
auto x12899 = Fp(x12836.asUInt32() & x50.asUInt32());
// loc("cirgen/circuit/rv32im/ffpu.cpp":314:20)
auto x12900 = x12899 * x65;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x12901 = Fp(x12900.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12901);
reg = x12901;
}
}
}
// loc("Top/Mux/4/Mux/12/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12902 = args[2][78 * steps + ((cycle - 0) & mask)];
assert(x12902 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/Bit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12903 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x12903 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":316:18)
auto x12904 = x12903 * x85;
// loc("cirgen/circuit/rv32im/ffpu.cpp":316:6)
auto x12905 = x12902 + x12904;
// loc("Top/Mux/4/Mux/12/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x12906 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x12906 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":316:43)
auto x12907 = x12906 * x77;
// loc("cirgen/circuit/rv32im/ffpu.cpp":316:6)
auto x12908 = x12905 + x12907;
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement7/Reg1"("cirgen/components/bytes.cpp":78:10))
auto x12909 = args[2][25 * steps + ((cycle - 0) & mask)];
assert(x12909 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":316:70)
auto x12910 = x12909 * x66;
// loc("cirgen/circuit/rv32im/ffpu.cpp":316:6)
auto x12911 = x12908 + x12910;
// loc("cirgen/circuit/rv32im/ffpu.cpp":316:6)
auto x12912 = x12911 - x12836;
// loc("cirgen/circuit/rv32im/ffpu.cpp":316:6)
if (x12912 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:316");
// loc("cirgen/circuit/rv32im/ffpu.cpp":330:17)
auto x12913 = x12839 * x97;
// loc("cirgen/circuit/rv32im/ffpu.cpp":330:17)
auto x12914 = x12913 + x12838;
// loc("cirgen/circuit/rv32im/ffpu.cpp":332:7)
auto x12915 = x12837 * x62;
// loc("cirgen/circuit/rv32im/ffpu.cpp":332:34)
auto x12916 = x12909 * x85;
// loc("cirgen/circuit/rv32im/ffpu.cpp":332:7)
auto x12917 = x12915 + x12916;
// loc("cirgen/circuit/rv32im/ffpu.cpp":332:57)
auto x12918 = x12906 * x99;
// loc("cirgen/circuit/rv32im/ffpu.cpp":332:7)
auto x12919 = x12917 + x12918;
// loc("cirgen/circuit/rv32im/ffpu.cpp":332:7)
auto x12920 = x12919 + x12903;
{
if (x12888 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":350:31)
auto x12921 = x12902 - x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":350:31)
auto x12922 = (x12921 == 0) ? Fp(1) : Fp(0);
if (x12922 != 0) {
{
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12923 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x12923 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12924 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x12924 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12925 = x12924 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x12926 = x12923 + x12925;
// loc("Top/Mux/4/Mux/12/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12927 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x12927 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12928 = x12927 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x12929 = x12926 + x12928;
// loc("Top/Mux/4/Mux/12/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12930 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x12930 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12931 = x12930 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x12932 = x12929 + x12931;
// loc("Top/Mux/4/Mux/12/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12933 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x12933 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12934 = x12933 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x12935 = x12932 + x12934;
// loc("Top/Mux/4/Mux/12/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12936 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x12936 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12937 = x12936 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x12938 = x12935 + x12937;
// loc("Top/Mux/4/Mux/12/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12939 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x12939 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12940 = x12939 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x12941 = x12938 + x12940;
// loc("./cirgen/components/onehot.h":38:8)
auto x12942 = x12941 - x102;
// loc("./cirgen/components/onehot.h":38:8)
if (x12942 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":351:31)
auto x12943 = x12902 - x99;
// loc("cirgen/circuit/rv32im/ffpu.cpp":351:31)
auto x12944 = (x12943 == 0) ? Fp(1) : Fp(0);
if (x12944 != 0) {
{
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12945 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x12945 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12946 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x12946 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12947 = x12946 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x12948 = x12945 + x12947;
// loc("Top/Mux/4/Mux/12/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12949 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x12949 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12950 = x12949 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x12951 = x12948 + x12950;
// loc("Top/Mux/4/Mux/12/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12952 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x12952 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12953 = x12952 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x12954 = x12951 + x12953;
// loc("Top/Mux/4/Mux/12/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12955 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x12955 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12956 = x12955 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x12957 = x12954 + x12956;
// loc("Top/Mux/4/Mux/12/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12958 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x12958 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12959 = x12958 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x12960 = x12957 + x12959;
// loc("Top/Mux/4/Mux/12/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12961 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x12961 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12962 = x12961 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x12963 = x12960 + x12962;
// loc("./cirgen/components/onehot.h":38:8)
auto x12964 = x12963 - x99;
// loc("./cirgen/components/onehot.h":38:8)
if (x12964 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":352:31)
auto x12965 = x12902 - x84;
// loc("cirgen/circuit/rv32im/ffpu.cpp":352:31)
auto x12966 = (x12965 == 0) ? Fp(1) : Fp(0);
if (x12966 != 0) {
{
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12967 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x12967 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12968 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x12968 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12969 = x12968 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x12970 = x12967 + x12969;
// loc("Top/Mux/4/Mux/12/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12971 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x12971 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12972 = x12971 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x12973 = x12970 + x12972;
// loc("Top/Mux/4/Mux/12/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12974 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x12974 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12975 = x12974 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x12976 = x12973 + x12975;
// loc("Top/Mux/4/Mux/12/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12977 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x12977 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12978 = x12977 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x12979 = x12976 + x12978;
// loc("Top/Mux/4/Mux/12/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12980 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x12980 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12981 = x12980 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x12982 = x12979 + x12981;
// loc("Top/Mux/4/Mux/12/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12983 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x12983 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12984 = x12983 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x12985 = x12982 + x12984;
// loc("./cirgen/components/onehot.h":38:8)
auto x12986 = x12985 - x84;
// loc("./cirgen/components/onehot.h":38:8)
if (x12986 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":353:24)
auto x12987 = (x12902 == 0) ? Fp(1) : Fp(0);
if (x12987 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":354:29)
auto x12988 = x102 - x12906;
if (x12988 != 0) {
if (x12903 != 0) {
{
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12989 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x12989 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12990 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x12990 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12991 = x12990 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x12992 = x12989 + x12991;
// loc("Top/Mux/4/Mux/12/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12993 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x12993 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12994 = x12993 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x12995 = x12992 + x12994;
// loc("Top/Mux/4/Mux/12/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12996 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x12996 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x12997 = x12996 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x12998 = x12995 + x12997;
// loc("Top/Mux/4/Mux/12/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x12999 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x12999 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13000 = x12999 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x13001 = x12998 + x13000;
// loc("Top/Mux/4/Mux/12/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13002 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x13002 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13003 = x13002 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x13004 = x13001 + x13003;
// loc("Top/Mux/4/Mux/12/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13005 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x13005 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13006 = x13005 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x13007 = x13004 + x13006;
// loc("./cirgen/components/onehot.h":38:8)
auto x13008 = x13007 - x85;
// loc("./cirgen/components/onehot.h":38:8)
if (x13008 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":356:29)
auto x13009 = x102 - x12903;
if (x13009 != 0) {
{
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13010 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x13010 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13011 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x13011 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13012 = x13011 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x13013 = x13010 + x13012;
// loc("Top/Mux/4/Mux/12/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13014 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x13014 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13015 = x13014 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x13016 = x13013 + x13015;
// loc("Top/Mux/4/Mux/12/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13017 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x13017 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13018 = x13017 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x13019 = x13016 + x13018;
// loc("Top/Mux/4/Mux/12/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13020 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x13020 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13021 = x13020 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x13022 = x13019 + x13021;
// loc("Top/Mux/4/Mux/12/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13023 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x13023 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13024 = x13023 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x13025 = x13022 + x13024;
// loc("Top/Mux/4/Mux/12/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13026 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x13026 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13027 = x13026 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x13028 = x13025 + x13027;
// loc("./cirgen/components/onehot.h":38:8)
auto x13029 = x13028 - x80;
// loc("./cirgen/components/onehot.h":38:8)
if (x13029 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
}
if (x12906 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":359:30)
auto x13030 = (x12837 == 0) ? Fp(1) : Fp(0);
if (x13030 != 0) {
{
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13031 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x13031 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13032 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x13032 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13033 = x13032 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x13034 = x13031 + x13033;
// loc("Top/Mux/4/Mux/12/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13035 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x13035 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13036 = x13035 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x13037 = x13034 + x13036;
// loc("Top/Mux/4/Mux/12/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13038 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x13038 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13039 = x13038 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x13040 = x13037 + x13039;
// loc("Top/Mux/4/Mux/12/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13041 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x13041 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13042 = x13041 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x13043 = x13040 + x13042;
// loc("Top/Mux/4/Mux/12/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13044 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x13044 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13045 = x13044 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x13046 = x13043 + x13045;
// loc("Top/Mux/4/Mux/12/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13047 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x13047 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13048 = x13047 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x13049 = x13046 + x13048;
// loc("./cirgen/components/onehot.h":38:8)
auto x13050 = x13049 - x79;
// loc("./cirgen/components/onehot.h":38:8)
if (x13050 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":360:34)
auto x13051 = x12837 - x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":360:34)
auto x13052 = (x13051 == 0) ? Fp(1) : Fp(0);
if (x13052 != 0) {
{
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][161 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][162 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][163 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][164 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][165 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][166 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][167 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/onehot.h":35:9)
{
auto& reg = args[2][168 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13053 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x13053 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13054 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x13054 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13055 = x13054 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x13056 = x13053 + x13055;
// loc("Top/Mux/4/Mux/12/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13057 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x13057 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13058 = x13057 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x13059 = x13056 + x13058;
// loc("Top/Mux/4/Mux/12/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13060 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x13060 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13061 = x13060 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x13062 = x13059 + x13061;
// loc("Top/Mux/4/Mux/12/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13063 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x13063 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13064 = x13063 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x13065 = x13062 + x13064;
// loc("Top/Mux/4/Mux/12/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13066 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x13066 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13067 = x13066 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x13068 = x13065 + x13067;
// loc("Top/Mux/4/Mux/12/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13069 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x13069 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13070 = x13069 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x13071 = x13068 + x13070;
// loc("./cirgen/components/onehot.h":38:8)
auto x13072 = x13071 - x78;
// loc("./cirgen/components/onehot.h":38:8)
if (x13072 != 0) throw std::runtime_error("eqz failed at: ./cirgen/components/onehot.h:38");
}
}
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg"("cirgen/circuit/rv32im/ffpu.cpp":371:21))
auto x13073 = args[2][161 * steps + ((cycle - 0) & mask)];
assert(x13073 != Fp::invalid());
if (x13073 != 0) {
host_args.at(0) = x12836;
host_args.at(1) = x12837;
host_args.at(2) = x12838;
host_args.at(3) = x12839;
host_args.at(4) = x603;
host(ctx, "log", "FFPU Decoded INIT from %w, pc = %u", host_args.data(), 5, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg1"("cirgen/circuit/rv32im/ffpu.cpp":372:26))
auto x13074 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x13074 != Fp::invalid());
if (x13074 != 0) {
host_args.at(0) = x12836;
host_args.at(1) = x12837;
host_args.at(2) = x12838;
host_args.at(3) = x12839;
host_args.at(4) = x603;
host(ctx, "log", "FFPU Decoded BINOP_ADD from %w, pc = %u", host_args.data(), 5, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg2"("cirgen/circuit/rv32im/ffpu.cpp":373:26))
auto x13075 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x13075 != Fp::invalid());
if (x13075 != 0) {
host_args.at(0) = x12836;
host_args.at(1) = x12837;
host_args.at(2) = x12838;
host_args.at(3) = x12839;
host_args.at(4) = x603;
host(ctx, "log", "FFPU Decoded BINOP_SUB from %w, pc = %u", host_args.data(), 5, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg3"("cirgen/circuit/rv32im/ffpu.cpp":374:26))
auto x13076 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x13076 != Fp::invalid());
if (x13076 != 0) {
host_args.at(0) = x12836;
host_args.at(1) = x12837;
host_args.at(2) = x12838;
host_args.at(3) = x12839;
host_args.at(4) = x603;
host(ctx, "log", "FFPU Decoded BINOP_MUL from %w, pc = %u", host_args.data(), 5, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg4"("cirgen/circuit/rv32im/ffpu.cpp":375:20))
auto x13077 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x13077 != Fp::invalid());
if (x13077 != 0) {
host_args.at(0) = x12836;
host_args.at(1) = x12837;
host_args.at(2) = x12838;
host_args.at(3) = x12839;
host_args.at(4) = x603;
host(ctx, "log", "FFPU Decoded SET from %w, pc = %u", host_args.data(), 5, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg5"("cirgen/circuit/rv32im/ffpu.cpp":376:20))
auto x13078 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x13078 != Fp::invalid());
if (x13078 != 0) {
host_args.at(0) = x12836;
host_args.at(1) = x12837;
host_args.at(2) = x12838;
host_args.at(3) = x12839;
host_args.at(4) = x603;
host(ctx, "log", "FFPU Decoded GET from %w, pc = %u", host_args.data(), 5, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg6"("cirgen/circuit/rv32im/ffpu.cpp":377:30))
auto x13079 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x13079 != Fp::invalid());
if (x13079 != 0) {
host_args.at(0) = x12836;
host_args.at(1) = x12837;
host_args.at(2) = x12838;
host_args.at(3) = x12839;
host_args.at(4) = x603;
host(ctx, "log", "FFPU Decoded UNOP_IDENTITY from %w, pc = %u", host_args.data(), 5, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg7"("cirgen/circuit/rv32im/ffpu.cpp":378:25))
auto x13080 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x13080 != Fp::invalid());
if (x13080 != 0) {
host_args.at(0) = x12836;
host_args.at(1) = x12837;
host_args.at(2) = x12838;
host_args.at(3) = x12839;
host_args.at(4) = x603;
host(ctx, "log", "FFPU Decoded UNOP_INV from %w, pc = %u", host_args.data(), 5, host_outs.data(), 0);
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg1"("cirgen/circuit/rv32im/ffpu.cpp":383:32))
auto x13081 = args[2][162 * steps + ((cycle - 0) & mask)];
assert(x13081 != Fp::invalid());
if (x13081 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":384:8)
auto x13082 = x12902 - x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":384:8)
if (x13082 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:384");
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13083 = x12914 + x11;
{
host_args.at(0) = x13083;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13084 = host_outs.at(0);
auto x13085 = host_outs.at(1);
auto x13086 = host_outs.at(2);
auto x13087 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13084);
reg = x13084;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13085);
reg = x13085;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13086);
reg = x13086;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13087);
reg = x13087;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13088 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13088 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13089 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13089 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13090 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x13090 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13091 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x13091 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13083);
reg = x13083;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13088);
reg = x13088;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13089);
reg = x13089;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13090);
reg = x13090;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13091);
reg = x13091;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13092 = x12920 + x11;
{
host_args.at(0) = x13092;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13093 = host_outs.at(0);
auto x13094 = host_outs.at(1);
auto x13095 = host_outs.at(2);
auto x13096 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13093);
reg = x13093;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13094);
reg = x13094;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13095);
reg = x13095;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13096);
reg = x13096;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13097 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x13097 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13098 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x13098 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13099 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x13099 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13100 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x13100 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13092);
reg = x13092;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13097);
reg = x13097;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13098);
reg = x13098;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13099);
reg = x13099;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13100);
reg = x13100;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":66:85)
auto x13101 = x13088 + x13097;
// loc("cirgen/circuit/rv32im/ffpu.cpp":66:85)
auto x13102 = x13089 + x13098;
// loc("cirgen/circuit/rv32im/ffpu.cpp":66:85)
auto x13103 = x13090 + x13099;
// loc("cirgen/circuit/rv32im/ffpu.cpp":66:85)
auto x13104 = x13091 + x13100;
host_args.at(0) = x12914;
host_args.at(1) = x13088;
host_args.at(2) = x13089;
host_args.at(3) = x13090;
host_args.at(4) = x13091;
host_args.at(5) = x12920;
host_args.at(6) = x13097;
host_args.at(7) = x13098;
host_args.at(8) = x13099;
host_args.at(9) = x13100;
host_args.at(10) = x13101;
host_args.at(11) = x13102;
host_args.at(12) = x13103;
host_args.at(13) = x13104;
host(ctx, "log", "FFPU: Add %%%u (%w) + %%%u (%w) -> %w", host_args.data(), 14, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/Reg1"("cirgen/circuit/rv32im/ffpu.cpp":17:20))
auto x13105 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x13105 != Fp::invalid());
host_args.at(0) = x13105;
host_args.at(1) = x13101;
host_args.at(2) = x13102;
host_args.at(3) = x13103;
host_args.at(4) = x13104;
host(ctx, "log", "FFPU: %%%u = FpExt(%u, %u, %u, %u)", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13106 = x13105 + x11;
{
host_args.at(0) = x13106;
host(ctx, "isResident", "", host_args.data(), 1, host_outs.data(), 1);
auto x13107 = host_outs.at(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13107);
reg = x13107;
}
}
// loc("Top/Mux/4/Mux/12/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13108 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x13108 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":30:13)
auto x13109 = x13108 * x99;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13101);
reg = x13101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13102);
reg = x13102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13103);
reg = x13103;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13104);
reg = x13104;
}
{
host_args.at(0) = x13106;
host_args.at(1) = x13101;
host_args.at(2) = x13102;
host_args.at(3) = x13103;
host_args.at(4) = x13104;
host_args.at(5) = x13109;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13110 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x13110 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13111 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x13111 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13112 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x13112 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13113 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x13113 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13106);
reg = x13106;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13109);
reg = x13109;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13110);
reg = x13110;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13111);
reg = x13111;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13112);
reg = x13112;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13113);
reg = x13113;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:28)
auto x13114 = x13105 + x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:3)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13114);
reg = x13114;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg2"("cirgen/circuit/rv32im/ffpu.cpp":387:32))
auto x13115 = args[2][163 * steps + ((cycle - 0) & mask)];
assert(x13115 != Fp::invalid());
if (x13115 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":388:8)
auto x13116 = x12902 - x99;
// loc("cirgen/circuit/rv32im/ffpu.cpp":388:8)
if (x13116 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:388");
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13117 = x12914 + x11;
{
host_args.at(0) = x13117;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13118 = host_outs.at(0);
auto x13119 = host_outs.at(1);
auto x13120 = host_outs.at(2);
auto x13121 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13118);
reg = x13118;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13119);
reg = x13119;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13120);
reg = x13120;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13121);
reg = x13121;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13122 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13122 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13123 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13123 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13124 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x13124 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13125 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x13125 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13117);
reg = x13117;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13122);
reg = x13122;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13123);
reg = x13123;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13124);
reg = x13124;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13125);
reg = x13125;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13126 = x12920 + x11;
{
host_args.at(0) = x13126;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13127 = host_outs.at(0);
auto x13128 = host_outs.at(1);
auto x13129 = host_outs.at(2);
auto x13130 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13127);
reg = x13127;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13128);
reg = x13128;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13129);
reg = x13129;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13130);
reg = x13130;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13131 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x13131 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13132 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x13132 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13133 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x13133 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13134 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x13134 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13126);
reg = x13126;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13131);
reg = x13131;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13132);
reg = x13132;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13133);
reg = x13133;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13134);
reg = x13134;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":71:85)
auto x13135 = x13122 - x13131;
// loc("cirgen/circuit/rv32im/ffpu.cpp":71:85)
auto x13136 = x13123 - x13132;
// loc("cirgen/circuit/rv32im/ffpu.cpp":71:85)
auto x13137 = x13124 - x13133;
// loc("cirgen/circuit/rv32im/ffpu.cpp":71:85)
auto x13138 = x13125 - x13134;
host_args.at(0) = x12914;
host_args.at(1) = x13122;
host_args.at(2) = x13123;
host_args.at(3) = x13124;
host_args.at(4) = x13125;
host_args.at(5) = x12920;
host_args.at(6) = x13131;
host_args.at(7) = x13132;
host_args.at(8) = x13133;
host_args.at(9) = x13134;
host_args.at(10) = x13135;
host_args.at(11) = x13136;
host_args.at(12) = x13137;
host_args.at(13) = x13138;
host(ctx, "log", "FFPU: Sub %%%u (%w) - %%%u (%w) -> %w", host_args.data(), 14, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/Reg1"("cirgen/circuit/rv32im/ffpu.cpp":17:20))
auto x13139 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x13139 != Fp::invalid());
host_args.at(0) = x13139;
host_args.at(1) = x13135;
host_args.at(2) = x13136;
host_args.at(3) = x13137;
host_args.at(4) = x13138;
host(ctx, "log", "FFPU: %%%u = FpExt(%u, %u, %u, %u)", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13140 = x13139 + x11;
{
host_args.at(0) = x13140;
host(ctx, "isResident", "", host_args.data(), 1, host_outs.data(), 1);
auto x13141 = host_outs.at(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13141);
reg = x13141;
}
}
// loc("Top/Mux/4/Mux/12/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13142 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x13142 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":30:13)
auto x13143 = x13142 * x99;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13135);
reg = x13135;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13136);
reg = x13136;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13137);
reg = x13137;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13138);
reg = x13138;
}
{
host_args.at(0) = x13140;
host_args.at(1) = x13135;
host_args.at(2) = x13136;
host_args.at(3) = x13137;
host_args.at(4) = x13138;
host_args.at(5) = x13143;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13144 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x13144 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13145 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x13145 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13146 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x13146 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13147 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x13147 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13140);
reg = x13140;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13143);
reg = x13143;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13144);
reg = x13144;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13145);
reg = x13145;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13146);
reg = x13146;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13147);
reg = x13147;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:28)
auto x13148 = x13139 + x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:3)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13148);
reg = x13148;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg3"("cirgen/circuit/rv32im/ffpu.cpp":391:32))
auto x13149 = args[2][164 * steps + ((cycle - 0) & mask)];
assert(x13149 != Fp::invalid());
if (x13149 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":392:8)
auto x13150 = x12902 - x84;
// loc("cirgen/circuit/rv32im/ffpu.cpp":392:8)
if (x13150 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:392");
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13151 = x12914 + x11;
{
host_args.at(0) = x13151;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13152 = host_outs.at(0);
auto x13153 = host_outs.at(1);
auto x13154 = host_outs.at(2);
auto x13155 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13152);
reg = x13152;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13153);
reg = x13153;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13154);
reg = x13154;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13155);
reg = x13155;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13156 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13156 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13157 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13157 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13158 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x13158 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13159 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x13159 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13151);
reg = x13151;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13156);
reg = x13156;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13157);
reg = x13157;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13158);
reg = x13158;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13159);
reg = x13159;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13160 = x12920 + x11;
{
host_args.at(0) = x13160;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13161 = host_outs.at(0);
auto x13162 = host_outs.at(1);
auto x13163 = host_outs.at(2);
auto x13164 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13161);
reg = x13161;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13162);
reg = x13162;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13163);
reg = x13163;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13164);
reg = x13164;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13165 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x13165 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13166 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x13166 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13167 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x13167 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13168 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x13168 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13160);
reg = x13160;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13165);
reg = x13165;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13166);
reg = x13166;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13167);
reg = x13167;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13168);
reg = x13168;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13169 = x13156 * x13165;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13170 = x13157 * x13168;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13171 = x13158 * x13167;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13172 = x13170 + x13171;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13173 = x13159 * x13166;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13174 = x13172 + x13173;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13175 = x13174 * x10;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13176 = x13169 + x13175;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13177 = x13156 * x13166;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13178 = x13157 * x13165;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13179 = x13177 + x13178;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13180 = x13158 * x13168;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13181 = x13159 * x13167;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13182 = x13180 + x13181;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13183 = x13182 * x10;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13184 = x13179 + x13183;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13185 = x13156 * x13167;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13186 = x13157 * x13166;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13187 = x13185 + x13186;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13188 = x13158 * x13165;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13189 = x13187 + x13188;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13190 = x13159 * x13168;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13191 = x13190 * x10;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13192 = x13189 + x13191;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13193 = x13156 * x13168;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13194 = x13157 * x13167;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13195 = x13193 + x13194;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13196 = x13158 * x13166;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13197 = x13195 + x13196;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13198 = x13159 * x13165;
// loc("cirgen/circuit/rv32im/ffpu.cpp":76:85)
auto x13199 = x13197 + x13198;
host_args.at(0) = x12914;
host_args.at(1) = x13156;
host_args.at(2) = x13157;
host_args.at(3) = x13158;
host_args.at(4) = x13159;
host_args.at(5) = x12920;
host_args.at(6) = x13165;
host_args.at(7) = x13166;
host_args.at(8) = x13167;
host_args.at(9) = x13168;
host_args.at(10) = x13176;
host_args.at(11) = x13184;
host_args.at(12) = x13192;
host_args.at(13) = x13199;
host(ctx, "log", "FFPU: Mul %%%u (%w) * %%%u (%w) -> %w", host_args.data(), 14, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/Reg1"("cirgen/circuit/rv32im/ffpu.cpp":17:20))
auto x13200 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x13200 != Fp::invalid());
host_args.at(0) = x13200;
host_args.at(1) = x13176;
host_args.at(2) = x13184;
host_args.at(3) = x13192;
host_args.at(4) = x13199;
host(ctx, "log", "FFPU: %%%u = FpExt(%u, %u, %u, %u)", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13201 = x13200 + x11;
{
host_args.at(0) = x13201;
host(ctx, "isResident", "", host_args.data(), 1, host_outs.data(), 1);
auto x13202 = host_outs.at(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13202);
reg = x13202;
}
}
// loc("Top/Mux/4/Mux/12/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13203 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x13203 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":30:13)
auto x13204 = x13203 * x99;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13176);
reg = x13176;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13184);
reg = x13184;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13192);
reg = x13192;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13199);
reg = x13199;
}
{
host_args.at(0) = x13201;
host_args.at(1) = x13176;
host_args.at(2) = x13184;
host_args.at(3) = x13192;
host_args.at(4) = x13199;
host_args.at(5) = x13204;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13205 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x13205 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13206 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x13206 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13207 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x13207 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13208 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x13208 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13201);
reg = x13201;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13204);
reg = x13204;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13205);
reg = x13205;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13206);
reg = x13206;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13207);
reg = x13207;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13208);
reg = x13208;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:28)
auto x13209 = x13200 + x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:3)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13209);
reg = x13209;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg4"("cirgen/circuit/rv32im/ffpu.cpp":395:26))
auto x13210 = args[2][165 * steps + ((cycle - 0) & mask)];
assert(x13210 != Fp::invalid());
if (x13210 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":396:8)
if (x12902 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:396");
// loc("cirgen/circuit/rv32im/ffpu.cpp":397:8)
auto x13211 = x12903 - x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":397:8)
if (x13211 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:397");
// loc("cirgen/circuit/rv32im/ffpu.cpp":398:8)
if (x12906 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:398");
// loc("Top/Mux/4/Mux/12/Reg4"("cirgen/circuit/rv32im/ffpu.cpp":171:46))
auto x13212 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x13212 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":171:46)
auto x13213 = x13212 + x12837;
{
host_args.at(0) = x13213;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13214 = host_outs.at(0);
auto x13215 = host_outs.at(1);
auto x13216 = host_outs.at(2);
auto x13217 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13214);
reg = x13214;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13215);
reg = x13215;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13216);
reg = x13216;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13217);
reg = x13217;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13218 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x13218 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13219 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x13219 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13220 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x13220 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13221 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x13221 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13213);
reg = x13213;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13218);
reg = x13218;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13219);
reg = x13219;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13220);
reg = x13220;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13221);
reg = x13221;
}
// loc("./cirgen/components/u32.h":25:12)
auto x13222 = x13219 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13223 = x13218 + x13222;
// loc("./cirgen/components/u32.h":26:12)
auto x13224 = x13220 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13225 = x13223 + x13224;
// loc("./cirgen/components/u32.h":27:12)
auto x13226 = x13221 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13227 = x13225 + x13226;
// loc("cirgen/circuit/rv32im/ffpu.cpp":171:18)
auto x13228 = x13227 * x83;
// loc("Top/Mux/4/Mux/12/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13229 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x13229 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":173:27)
auto x13230 = x102 - x13229;
if (x13230 != 0) {
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13231 = args[2][132 * steps + ((cycle - 1) & mask)];
assert(x13231 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13232 = args[2][133 * steps + ((cycle - 1) & mask)];
assert(x13232 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13233 = args[2][134 * steps + ((cycle - 1) & mask)];
assert(x13233 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13234 = args[2][135 * steps + ((cycle - 1) & mask)];
assert(x13234 != Fp::invalid());
{
// loc("cirgen/circuit/rv32im/ffpu.cpp":189:38)
auto x13235 = x12914 * x85;
// loc("cirgen/circuit/rv32im/ffpu.cpp":189:27)
auto x13236 = x13228 + x13235;
// loc("cirgen/circuit/rv32im/ffpu.cpp":47:10)
auto x13237 = x13231 * x1;
// loc("cirgen/components/u32.cpp":47:12)
auto x13238 = Fp(x13237.asUInt32() & x98.asUInt32());
// loc("cirgen/components/u32.cpp":48:12)
auto x13239 = Fp(x13237.asUInt32() & x9.asUInt32());
// loc("cirgen/components/u32.cpp":49:12)
auto x13240 = Fp(x13237.asUInt32() & x8.asUInt32());
// loc("cirgen/components/u32.cpp":50:12)
auto x13241 = x13237 - x13238;
// loc("cirgen/components/u32.cpp":50:12)
auto x13242 = x13241 - x13239;
// loc("cirgen/components/u32.cpp":50:12)
auto x13243 = x13242 - x13240;
// loc("cirgen/components/u32.cpp":54:21)
auto x13244 = x13239 * x96;
// loc("cirgen/components/u32.cpp":55:21)
auto x13245 = x13240 * x16;
// loc("cirgen/components/u32.cpp":56:21)
auto x13246 = x13243 * x7;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13238);
reg = x13238;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13244);
reg = x13244;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13245);
reg = x13245;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13246);
reg = x13246;
}
{
host_args.at(0) = x13236;
host_args.at(1) = x13238;
host_args.at(2) = x13244;
host_args.at(3) = x13245;
host_args.at(4) = x13246;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13247 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13247 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13248 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13248 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13249 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x13249 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13250 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x13250 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13236);
reg = x13236;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13247);
reg = x13247;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13248);
reg = x13248;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13249);
reg = x13249;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13250);
reg = x13250;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":190:27)
auto x13251 = x13236 + x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":47:10)
auto x13252 = x13232 * x1;
// loc("cirgen/components/u32.cpp":47:12)
auto x13253 = Fp(x13252.asUInt32() & x98.asUInt32());
// loc("cirgen/components/u32.cpp":48:12)
auto x13254 = Fp(x13252.asUInt32() & x9.asUInt32());
// loc("cirgen/components/u32.cpp":49:12)
auto x13255 = Fp(x13252.asUInt32() & x8.asUInt32());
// loc("cirgen/components/u32.cpp":50:12)
auto x13256 = x13252 - x13253;
// loc("cirgen/components/u32.cpp":50:12)
auto x13257 = x13256 - x13254;
// loc("cirgen/components/u32.cpp":50:12)
auto x13258 = x13257 - x13255;
// loc("cirgen/components/u32.cpp":54:21)
auto x13259 = x13254 * x96;
// loc("cirgen/components/u32.cpp":55:21)
auto x13260 = x13255 * x16;
// loc("cirgen/components/u32.cpp":56:21)
auto x13261 = x13258 * x7;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13253);
reg = x13253;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13259);
reg = x13259;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13260);
reg = x13260;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13261);
reg = x13261;
}
{
host_args.at(0) = x13251;
host_args.at(1) = x13253;
host_args.at(2) = x13259;
host_args.at(3) = x13260;
host_args.at(4) = x13261;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13262 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x13262 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13263 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x13263 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13264 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x13264 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13265 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x13265 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13251);
reg = x13251;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13262);
reg = x13262;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13263);
reg = x13263;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13264);
reg = x13264;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13265);
reg = x13265;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/Reg1"("cirgen/components/ram.cpp":141:10))
auto x13266 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x13266 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":192:8)
auto x13267 = x13266 - x12830;
// loc("cirgen/circuit/rv32im/ffpu.cpp":192:8)
if (x13267 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:192");
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/Reg"("cirgen/components/ram.cpp":137:10))
auto x13268 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x13268 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":193:32)
auto x13269 = x12914 * x85;
// loc("cirgen/circuit/rv32im/ffpu.cpp":193:21)
auto x13270 = x13228 + x13269;
// loc("cirgen/circuit/rv32im/ffpu.cpp":193:8)
auto x13271 = x13268 - x13270;
// loc("cirgen/circuit/rv32im/ffpu.cpp":193:8)
if (x13271 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:193");
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13272 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13272 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13273 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13273 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13274 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x13274 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13275 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x13275 != Fp::invalid());
// loc("./cirgen/components/u32.h":25:12)
auto x13276 = x13273 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13277 = x13272 + x13276;
// loc("./cirgen/components/u32.h":26:12)
auto x13278 = x13274 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13279 = x13277 + x13278;
// loc("./cirgen/components/u32.h":27:12)
auto x13280 = x13275 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13281 = x13279 + x13280;
// loc("cirgen/circuit/rv32im/ffpu.cpp":47:10)
auto x13282 = x13231 * x1;
// loc("cirgen/circuit/rv32im/ffpu.cpp":194:8)
auto x13283 = x13281 - x13282;
// loc("cirgen/circuit/rv32im/ffpu.cpp":194:8)
if (x13283 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:194");
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/Reg1"("cirgen/components/ram.cpp":141:10))
auto x13284 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x13284 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":196:8)
auto x13285 = x13284 - x12830;
// loc("cirgen/circuit/rv32im/ffpu.cpp":196:8)
if (x13285 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:196");
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/Reg"("cirgen/components/ram.cpp":137:10))
auto x13286 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x13286 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":197:21)
auto x13287 = x13270 + x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":197:8)
auto x13288 = x13286 - x13287;
// loc("cirgen/circuit/rv32im/ffpu.cpp":197:8)
if (x13288 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:197");
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13289 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x13289 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13290 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x13290 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13291 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x13291 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13292 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x13292 != Fp::invalid());
// loc("./cirgen/components/u32.h":25:12)
auto x13293 = x13290 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13294 = x13289 + x13293;
// loc("./cirgen/components/u32.h":26:12)
auto x13295 = x13291 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13296 = x13294 + x13295;
// loc("./cirgen/components/u32.h":27:12)
auto x13297 = x13292 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13298 = x13296 + x13297;
// loc("cirgen/circuit/rv32im/ffpu.cpp":47:10)
auto x13299 = x13232 * x1;
// loc("cirgen/circuit/rv32im/ffpu.cpp":198:8)
auto x13300 = x13298 - x13299;
// loc("cirgen/circuit/rv32im/ffpu.cpp":198:8)
if (x13300 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:198");
// loc("cirgen/circuit/rv32im/ffpu.cpp":202:10)
auto x13301 = x13228 * x85;
host_args.at(0) = x12837;
host_args.at(1) = x13301;
host_args.at(2) = x12914;
host_args.at(3) = x13231;
host_args.at(4) = x13232;
host_args.at(5) = x13233;
host_args.at(6) = x13234;
host_args.at(7) = x13231;
host_args.at(8) = x13232;
host(ctx, "log", "FFPU: Set to arg[%u] (%x) [%u] <- %w (%u, %u, ...)", host_args.data(), 9, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/Reg1"("cirgen/circuit/rv32im/ffpu.cpp":37:28))
auto x13302 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x13302 != Fp::invalid());
host_args.at(0) = x13302;
host(ctx, "log", "FFPU: %%%u = ...", host_args.data(), 1, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ffpu.cpp":38:3)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13302);
reg = x13302;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
}
if (x13229 != 0) {
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13303 = args[2][132 * steps + ((cycle - 2) & mask)];
assert(x13303 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13304 = args[2][133 * steps + ((cycle - 2) & mask)];
assert(x13304 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13305 = args[2][134 * steps + ((cycle - 2) & mask)];
assert(x13305 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13306 = args[2][135 * steps + ((cycle - 2) & mask)];
assert(x13306 != Fp::invalid());
{
// loc("cirgen/circuit/rv32im/ffpu.cpp":227:38)
auto x13307 = x12914 * x85;
// loc("cirgen/circuit/rv32im/ffpu.cpp":227:27)
auto x13308 = x13228 + x13307;
// loc("cirgen/circuit/rv32im/ffpu.cpp":227:27)
auto x13309 = x13308 + x99;
// loc("cirgen/circuit/rv32im/ffpu.cpp":47:10)
auto x13310 = x13305 * x1;
// loc("cirgen/components/u32.cpp":47:12)
auto x13311 = Fp(x13310.asUInt32() & x98.asUInt32());
// loc("cirgen/components/u32.cpp":48:12)
auto x13312 = Fp(x13310.asUInt32() & x9.asUInt32());
// loc("cirgen/components/u32.cpp":49:12)
auto x13313 = Fp(x13310.asUInt32() & x8.asUInt32());
// loc("cirgen/components/u32.cpp":50:12)
auto x13314 = x13310 - x13311;
// loc("cirgen/components/u32.cpp":50:12)
auto x13315 = x13314 - x13312;
// loc("cirgen/components/u32.cpp":50:12)
auto x13316 = x13315 - x13313;
// loc("cirgen/components/u32.cpp":54:21)
auto x13317 = x13312 * x96;
// loc("cirgen/components/u32.cpp":55:21)
auto x13318 = x13313 * x16;
// loc("cirgen/components/u32.cpp":56:21)
auto x13319 = x13316 * x7;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13311);
reg = x13311;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13317);
reg = x13317;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13318);
reg = x13318;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13319);
reg = x13319;
}
{
host_args.at(0) = x13309;
host_args.at(1) = x13311;
host_args.at(2) = x13317;
host_args.at(3) = x13318;
host_args.at(4) = x13319;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13320 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13320 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13321 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13321 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13322 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x13322 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13323 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x13323 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13309);
reg = x13309;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13320);
reg = x13320;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13321);
reg = x13321;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13322);
reg = x13322;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13323);
reg = x13323;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":228:27)
auto x13324 = x13308 + x84;
// loc("cirgen/circuit/rv32im/ffpu.cpp":47:10)
auto x13325 = x13306 * x1;
// loc("cirgen/components/u32.cpp":47:12)
auto x13326 = Fp(x13325.asUInt32() & x98.asUInt32());
// loc("cirgen/components/u32.cpp":48:12)
auto x13327 = Fp(x13325.asUInt32() & x9.asUInt32());
// loc("cirgen/components/u32.cpp":49:12)
auto x13328 = Fp(x13325.asUInt32() & x8.asUInt32());
// loc("cirgen/components/u32.cpp":50:12)
auto x13329 = x13325 - x13326;
// loc("cirgen/components/u32.cpp":50:12)
auto x13330 = x13329 - x13327;
// loc("cirgen/components/u32.cpp":50:12)
auto x13331 = x13330 - x13328;
// loc("cirgen/components/u32.cpp":54:21)
auto x13332 = x13327 * x96;
// loc("cirgen/components/u32.cpp":55:21)
auto x13333 = x13328 * x16;
// loc("cirgen/components/u32.cpp":56:21)
auto x13334 = x13331 * x7;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13326);
reg = x13326;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13332);
reg = x13332;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13333);
reg = x13333;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13334);
reg = x13334;
}
{
host_args.at(0) = x13324;
host_args.at(1) = x13326;
host_args.at(2) = x13332;
host_args.at(3) = x13333;
host_args.at(4) = x13334;
host_args.at(5) = x99;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13335 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x13335 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13336 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x13336 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13337 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x13337 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13338 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x13338 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13324);
reg = x13324;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x99);
reg = x99;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13335);
reg = x13335;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13336);
reg = x13336;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13337);
reg = x13337;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13338);
reg = x13338;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/Reg1"("cirgen/components/ram.cpp":141:10))
auto x13339 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x13339 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":230:8)
auto x13340 = x13339 - x12830;
// loc("cirgen/circuit/rv32im/ffpu.cpp":230:8)
if (x13340 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:230");
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/Reg"("cirgen/components/ram.cpp":137:10))
auto x13341 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x13341 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":231:32)
auto x13342 = x12914 * x85;
// loc("cirgen/circuit/rv32im/ffpu.cpp":231:21)
auto x13343 = x13228 + x13342;
// loc("cirgen/circuit/rv32im/ffpu.cpp":231:21)
auto x13344 = x13343 + x99;
// loc("cirgen/circuit/rv32im/ffpu.cpp":231:8)
auto x13345 = x13341 - x13344;
// loc("cirgen/circuit/rv32im/ffpu.cpp":231:8)
if (x13345 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:231");
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13346 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13346 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13347 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13347 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13348 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x13348 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13349 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x13349 != Fp::invalid());
// loc("./cirgen/components/u32.h":25:12)
auto x13350 = x13347 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13351 = x13346 + x13350;
// loc("./cirgen/components/u32.h":26:12)
auto x13352 = x13348 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13353 = x13351 + x13352;
// loc("./cirgen/components/u32.h":27:12)
auto x13354 = x13349 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13355 = x13353 + x13354;
// loc("cirgen/circuit/rv32im/ffpu.cpp":47:10)
auto x13356 = x13305 * x1;
// loc("cirgen/circuit/rv32im/ffpu.cpp":232:8)
auto x13357 = x13355 - x13356;
// loc("cirgen/circuit/rv32im/ffpu.cpp":232:8)
if (x13357 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:232");
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/Reg1"("cirgen/components/ram.cpp":141:10))
auto x13358 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x13358 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":234:8)
auto x13359 = x13358 - x12830;
// loc("cirgen/circuit/rv32im/ffpu.cpp":234:8)
if (x13359 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:234");
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/Reg"("cirgen/components/ram.cpp":137:10))
auto x13360 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x13360 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":235:21)
auto x13361 = x13343 + x84;
// loc("cirgen/circuit/rv32im/ffpu.cpp":235:8)
auto x13362 = x13360 - x13361;
// loc("cirgen/circuit/rv32im/ffpu.cpp":235:8)
if (x13362 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:235");
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13363 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x13363 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13364 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x13364 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13365 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x13365 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13366 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x13366 != Fp::invalid());
// loc("./cirgen/components/u32.h":25:12)
auto x13367 = x13364 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13368 = x13363 + x13367;
// loc("./cirgen/components/u32.h":26:12)
auto x13369 = x13365 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13370 = x13368 + x13369;
// loc("./cirgen/components/u32.h":27:12)
auto x13371 = x13366 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13372 = x13370 + x13371;
// loc("cirgen/circuit/rv32im/ffpu.cpp":47:10)
auto x13373 = x13306 * x1;
// loc("cirgen/circuit/rv32im/ffpu.cpp":236:8)
auto x13374 = x13372 - x13373;
// loc("cirgen/circuit/rv32im/ffpu.cpp":236:8)
if (x13374 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:236");
// loc("cirgen/circuit/rv32im/ffpu.cpp":240:10)
auto x13375 = x13228 * x85;
host_args.at(0) = x12837;
host_args.at(1) = x13375;
host_args.at(2) = x12914;
host_args.at(3) = x13303;
host_args.at(4) = x13304;
host_args.at(5) = x13305;
host_args.at(6) = x13306;
host_args.at(7) = x13305;
host_args.at(8) = x13306;
host(ctx, "log", "FFPU: Set to arg[%u] (%x) [%u] <- %w (... %u, %u)", host_args.data(), 9, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/Reg1"("cirgen/circuit/rv32im/ffpu.cpp":37:28))
auto x13376 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x13376 != Fp::invalid());
host_args.at(0) = x13376;
host(ctx, "log", "FFPU: %%%u = ...", host_args.data(), 1, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ffpu.cpp":38:3)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13376);
reg = x13376;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg5"("cirgen/circuit/rv32im/ffpu.cpp":401:26))
auto x13377 = args[2][166 * steps + ((cycle - 0) & mask)];
assert(x13377 != Fp::invalid());
if (x13377 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":402:8)
if (x12902 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:402");
// loc("cirgen/circuit/rv32im/ffpu.cpp":403:8)
if (x12903 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:403");
// loc("cirgen/circuit/rv32im/ffpu.cpp":404:8)
if (x12906 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:404");
// loc("Top/Mux/4/Mux/12/Bit2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13378 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x13378 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":121:27)
auto x13379 = x102 - x13378;
if (x13379 != 0) {
// loc("Top/Mux/4/Mux/12/Reg4"("cirgen/circuit/rv32im/ffpu.cpp":124:48))
auto x13380 = args[2][175 * steps + ((cycle - 0) & mask)];
assert(x13380 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":124:48)
auto x13381 = x13380 + x12837;
{
host_args.at(0) = x13381;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13382 = host_outs.at(0);
auto x13383 = host_outs.at(1);
auto x13384 = host_outs.at(2);
auto x13385 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13382);
reg = x13382;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13383);
reg = x13383;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13384);
reg = x13384;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13385);
reg = x13385;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13386 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x13386 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13387 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x13387 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13388 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x13388 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13389 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x13389 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13381);
reg = x13381;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13386);
reg = x13386;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13387);
reg = x13387;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13388);
reg = x13388;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13389);
reg = x13389;
}
// loc("./cirgen/components/u32.h":25:12)
auto x13390 = x13387 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13391 = x13386 + x13390;
// loc("./cirgen/components/u32.h":26:12)
auto x13392 = x13388 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13393 = x13391 + x13392;
// loc("./cirgen/components/u32.h":27:12)
auto x13394 = x13389 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13395 = x13393 + x13394;
// loc("cirgen/circuit/rv32im/ffpu.cpp":124:20)
auto x13396 = x13395 * x83;
// loc("cirgen/circuit/rv32im/ffpu.cpp":126:64)
auto x13397 = x12914 * x85;
// loc("cirgen/circuit/rv32im/ffpu.cpp":126:53)
auto x13398 = x13396 + x13397;
{
host_args.at(0) = x13398;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13399 = host_outs.at(0);
auto x13400 = host_outs.at(1);
auto x13401 = host_outs.at(2);
auto x13402 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13399);
reg = x13399;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13400);
reg = x13400;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13401);
reg = x13401;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13402);
reg = x13402;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13403 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13403 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13404 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13404 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13405 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x13405 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13406 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x13406 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13398);
reg = x13398;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13403);
reg = x13403;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13404);
reg = x13404;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13405);
reg = x13405;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13406);
reg = x13406;
}
// loc("./cirgen/components/u32.h":25:12)
auto x13407 = x13404 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13408 = x13403 + x13407;
// loc("./cirgen/components/u32.h":26:12)
auto x13409 = x13405 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13410 = x13408 + x13409;
// loc("./cirgen/components/u32.h":27:12)
auto x13411 = x13406 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13412 = x13410 + x13411;
// loc("cirgen/circuit/rv32im/ffpu.cpp":51:10)
auto x13413 = x13412 * x0;
// loc("cirgen/circuit/rv32im/ffpu.cpp":127:53)
auto x13414 = x13398 + x102;
{
host_args.at(0) = x13414;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13415 = host_outs.at(0);
auto x13416 = host_outs.at(1);
auto x13417 = host_outs.at(2);
auto x13418 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13415);
reg = x13415;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13416);
reg = x13416;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13417);
reg = x13417;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13418);
reg = x13418;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13419 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x13419 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13420 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x13420 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13421 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x13421 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13422 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x13422 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13414);
reg = x13414;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13419);
reg = x13419;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13420);
reg = x13420;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13421);
reg = x13421;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13422);
reg = x13422;
}
// loc("./cirgen/components/u32.h":25:12)
auto x13423 = x13420 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13424 = x13419 + x13423;
// loc("./cirgen/components/u32.h":26:12)
auto x13425 = x13421 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13426 = x13424 + x13425;
// loc("./cirgen/components/u32.h":27:12)
auto x13427 = x13422 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13428 = x13426 + x13427;
// loc("cirgen/circuit/rv32im/ffpu.cpp":51:10)
auto x13429 = x13428 * x0;
// loc("cirgen/circuit/rv32im/ffpu.cpp":131:10)
auto x13430 = x13396 * x85;
host_args.at(0) = x12837;
host_args.at(1) = x13430;
host_args.at(2) = x12914;
host_args.at(3) = x13413;
host_args.at(4) = x13429;
host(ctx, "log", "FFPU: Get from arg[%u] (%x) [%u] -> %u, %u, ..", host_args.data(), 5, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/Reg1"("cirgen/circuit/rv32im/ffpu.cpp":37:28))
auto x13431 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x13431 != Fp::invalid());
host_args.at(0) = x13431;
host(ctx, "log", "FFPU: %%%u = ...", host_args.data(), 1, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ffpu.cpp":38:3)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13431);
reg = x13431;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
}
if (x13378 != 0) {
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13432 = args[2][132 * steps + ((cycle - 1) & mask)];
assert(x13432 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13433 = args[2][133 * steps + ((cycle - 1) & mask)];
assert(x13433 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13434 = args[2][134 * steps + ((cycle - 1) & mask)];
assert(x13434 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13435 = args[2][135 * steps + ((cycle - 1) & mask)];
assert(x13435 != Fp::invalid());
// loc("./cirgen/components/u32.h":25:12)
auto x13436 = x13433 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13437 = x13432 + x13436;
// loc("./cirgen/components/u32.h":26:12)
auto x13438 = x13434 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13439 = x13437 + x13438;
// loc("./cirgen/components/u32.h":27:12)
auto x13440 = x13435 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13441 = x13439 + x13440;
// loc("cirgen/circuit/rv32im/ffpu.cpp":144:59)
auto x13442 = x13441 * x83;
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13443 = args[2][118 * steps + ((cycle - 1) & mask)];
assert(x13443 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13444 = args[2][119 * steps + ((cycle - 1) & mask)];
assert(x13444 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13445 = args[2][120 * steps + ((cycle - 1) & mask)];
assert(x13445 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13446 = args[2][121 * steps + ((cycle - 1) & mask)];
assert(x13446 != Fp::invalid());
// loc("./cirgen/components/u32.h":25:12)
auto x13447 = x13444 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13448 = x13443 + x13447;
// loc("./cirgen/components/u32.h":26:12)
auto x13449 = x13445 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13450 = x13448 + x13449;
// loc("./cirgen/components/u32.h":27:12)
auto x13451 = x13446 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13452 = x13450 + x13451;
// loc("cirgen/circuit/rv32im/ffpu.cpp":51:10)
auto x13453 = x13452 * x0;
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13454 = args[2][125 * steps + ((cycle - 1) & mask)];
assert(x13454 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13455 = args[2][126 * steps + ((cycle - 1) & mask)];
assert(x13455 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13456 = args[2][127 * steps + ((cycle - 1) & mask)];
assert(x13456 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13457 = args[2][128 * steps + ((cycle - 1) & mask)];
assert(x13457 != Fp::invalid());
// loc("./cirgen/components/u32.h":25:12)
auto x13458 = x13455 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13459 = x13454 + x13458;
// loc("./cirgen/components/u32.h":26:12)
auto x13460 = x13456 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13461 = x13459 + x13460;
// loc("./cirgen/components/u32.h":27:12)
auto x13462 = x13457 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13463 = x13461 + x13462;
// loc("cirgen/circuit/rv32im/ffpu.cpp":51:10)
auto x13464 = x13463 * x0;
// loc("cirgen/circuit/rv32im/ffpu.cpp":148:64)
auto x13465 = x12914 * x85;
// loc("cirgen/circuit/rv32im/ffpu.cpp":148:53)
auto x13466 = x13442 + x13465;
// loc("cirgen/circuit/rv32im/ffpu.cpp":148:53)
auto x13467 = x13466 + x99;
{
host_args.at(0) = x13467;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13468 = host_outs.at(0);
auto x13469 = host_outs.at(1);
auto x13470 = host_outs.at(2);
auto x13471 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13468);
reg = x13468;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13469);
reg = x13469;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13470);
reg = x13470;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13471);
reg = x13471;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13472 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13472 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13473 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13473 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13474 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x13474 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13475 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x13475 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13467);
reg = x13467;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13472);
reg = x13472;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13473);
reg = x13473;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13474);
reg = x13474;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13475);
reg = x13475;
}
// loc("./cirgen/components/u32.h":25:12)
auto x13476 = x13473 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13477 = x13472 + x13476;
// loc("./cirgen/components/u32.h":26:12)
auto x13478 = x13474 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13479 = x13477 + x13478;
// loc("./cirgen/components/u32.h":27:12)
auto x13480 = x13475 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13481 = x13479 + x13480;
// loc("cirgen/circuit/rv32im/ffpu.cpp":51:10)
auto x13482 = x13481 * x0;
// loc("cirgen/circuit/rv32im/ffpu.cpp":149:53)
auto x13483 = x13466 + x84;
{
host_args.at(0) = x13483;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13484 = host_outs.at(0);
auto x13485 = host_outs.at(1);
auto x13486 = host_outs.at(2);
auto x13487 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13484);
reg = x13484;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13485);
reg = x13485;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13486);
reg = x13486;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13487);
reg = x13487;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13488 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x13488 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13489 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x13489 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13490 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x13490 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13491 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x13491 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13483);
reg = x13483;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13488);
reg = x13488;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13489);
reg = x13489;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13490);
reg = x13490;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13491);
reg = x13491;
}
// loc("./cirgen/components/u32.h":25:12)
auto x13492 = x13489 * x97;
// loc("./cirgen/components/u32.h":24:12)
auto x13493 = x13488 + x13492;
// loc("./cirgen/components/u32.h":26:12)
auto x13494 = x13490 * x87;
// loc("./cirgen/components/u32.h":24:12)
auto x13495 = x13493 + x13494;
// loc("./cirgen/components/u32.h":27:12)
auto x13496 = x13491 * x86;
// loc("./cirgen/components/u32.h":24:12)
auto x13497 = x13495 + x13496;
// loc("cirgen/circuit/rv32im/ffpu.cpp":51:10)
auto x13498 = x13497 * x0;
// loc("cirgen/circuit/rv32im/ffpu.cpp":154:10)
auto x13499 = x13442 * x85;
host_args.at(0) = x12837;
host_args.at(1) = x13499;
host_args.at(2) = x12914;
host_args.at(3) = x13453;
host_args.at(4) = x13464;
host_args.at(5) = x13482;
host_args.at(6) = x13498;
host(ctx, "log", "FFPU: Get from arg[%u] (%x) [%u] -> %u, %u, %u, %u", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/Reg1"("cirgen/circuit/rv32im/ffpu.cpp":17:20))
auto x13500 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x13500 != Fp::invalid());
host_args.at(0) = x13500;
host_args.at(1) = x13453;
host_args.at(2) = x13464;
host_args.at(3) = x13482;
host_args.at(4) = x13498;
host(ctx, "log", "FFPU: %%%u = FpExt(%u, %u, %u, %u)", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13501 = x13500 + x11;
{
host_args.at(0) = x13501;
host(ctx, "isResident", "", host_args.data(), 1, host_outs.data(), 1);
auto x13502 = host_outs.at(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13502);
reg = x13502;
}
}
// loc("Top/Mux/4/Mux/12/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13503 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x13503 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":30:13)
auto x13504 = x13503 * x99;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13453);
reg = x13453;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13464);
reg = x13464;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13482);
reg = x13482;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13498);
reg = x13498;
}
{
host_args.at(0) = x13501;
host_args.at(1) = x13453;
host_args.at(2) = x13464;
host_args.at(3) = x13482;
host_args.at(4) = x13498;
host_args.at(5) = x13504;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13505 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x13505 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13506 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x13506 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13507 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x13507 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13508 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x13508 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13501);
reg = x13501;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13504);
reg = x13504;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13505);
reg = x13505;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13506);
reg = x13506;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13507);
reg = x13507;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13508);
reg = x13508;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:28)
auto x13509 = x13500 + x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:3)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13509);
reg = x13509;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg6"("cirgen/circuit/rv32im/ffpu.cpp":407:36))
auto x13510 = args[2][167 * steps + ((cycle - 0) & mask)];
assert(x13510 != Fp::invalid());
if (x13510 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":408:8)
if (x12902 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:408");
// loc("cirgen/circuit/rv32im/ffpu.cpp":409:8)
if (x12903 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:409");
// loc("cirgen/circuit/rv32im/ffpu.cpp":410:8)
auto x13511 = x12906 - x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":410:8)
if (x13511 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:410");
// loc("cirgen/circuit/rv32im/ffpu.cpp":411:8)
if (x12837 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:411");
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13512 = x12914 + x11;
{
host_args.at(0) = x13512;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13513 = host_outs.at(0);
auto x13514 = host_outs.at(1);
auto x13515 = host_outs.at(2);
auto x13516 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13513);
reg = x13513;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13514);
reg = x13514;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13515);
reg = x13515;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13516);
reg = x13516;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13517 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13517 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13518 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13518 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13519 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x13519 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13520 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x13520 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13512);
reg = x13512;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13517);
reg = x13517;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13518);
reg = x13518;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13519);
reg = x13519;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13520);
reg = x13520;
}
host_args.at(0) = x12914;
host_args.at(1) = x13517;
host_args.at(2) = x13518;
host_args.at(3) = x13519;
host_args.at(4) = x13520;
host(ctx, "log", "FFPU: Identity %%%u (%w)", host_args.data(), 5, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/Reg1"("cirgen/circuit/rv32im/ffpu.cpp":17:20))
auto x13521 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x13521 != Fp::invalid());
host_args.at(0) = x13521;
host_args.at(1) = x13517;
host_args.at(2) = x13518;
host_args.at(3) = x13519;
host_args.at(4) = x13520;
host(ctx, "log", "FFPU: %%%u = FpExt(%u, %u, %u, %u)", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13522 = x13521 + x11;
{
host_args.at(0) = x13522;
host(ctx, "isResident", "", host_args.data(), 1, host_outs.data(), 1);
auto x13523 = host_outs.at(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13523);
reg = x13523;
}
}
// loc("Top/Mux/4/Mux/12/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13524 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x13524 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":30:13)
auto x13525 = x13524 * x99;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13517);
reg = x13517;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13518);
reg = x13518;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13519);
reg = x13519;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13520);
reg = x13520;
}
{
host_args.at(0) = x13522;
host_args.at(1) = x13517;
host_args.at(2) = x13518;
host_args.at(3) = x13519;
host_args.at(4) = x13520;
host_args.at(5) = x13525;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13526 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x13526 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13527 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x13527 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13528 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x13528 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13529 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x13529 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13522);
reg = x13522;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13525);
reg = x13525;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13526);
reg = x13526;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13527);
reg = x13527;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13528);
reg = x13528;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13529);
reg = x13529;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:28)
auto x13530 = x13521 + x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:3)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13530);
reg = x13530;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/OneHot/Reg7"("cirgen/circuit/rv32im/ffpu.cpp":414:31))
auto x13531 = args[2][168 * steps + ((cycle - 0) & mask)];
assert(x13531 != Fp::invalid());
if (x13531 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":415:8)
if (x12902 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:415");
// loc("cirgen/circuit/rv32im/ffpu.cpp":416:8)
if (x12903 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:416");
// loc("cirgen/circuit/rv32im/ffpu.cpp":417:8)
auto x13532 = x12906 - x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":417:8)
if (x13532 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:417");
// loc("cirgen/circuit/rv32im/ffpu.cpp":418:8)
auto x13533 = x12837 - x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":418:8)
if (x13533 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:418");
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13534 = x12914 + x11;
{
host_args.at(0) = x13534;
host_args.at(1) = x102;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13535 = host_outs.at(0);
auto x13536 = host_outs.at(1);
auto x13537 = host_outs.at(2);
auto x13538 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13535);
reg = x13535;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13536);
reg = x13536;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13537);
reg = x13537;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13538);
reg = x13538;
}
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13539 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13539 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13540 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13540 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13541 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x13541 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13542 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x13542 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13534);
reg = x13534;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13539);
reg = x13539;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13540);
reg = x13540;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13541);
reg = x13541;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13542);
reg = x13542;
}
{
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13543 = x13539 * x13539;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13544 = x13542 + x13542;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13545 = x13540 * x13544;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13546 = x13541 * x13541;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13547 = x13545 - x13546;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13548 = x13547 * x74;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13549 = x13543 + x13548;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13550 = x13541 + x13541;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13551 = x13539 * x13550;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13552 = x13540 * x13540;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13553 = x13551 - x13552;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13554 = x13542 * x13542;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13555 = x13554 * x74;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13556 = x13553 + x13555;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13557 = x13549 * x13549;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13558 = x13556 * x74;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13559 = x13558 * x13556;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13560 = x13557 + x13559;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13561 = inv(x13560);
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13562 = x13549 * x13561;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13563 = x13556 * x13561;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13564 = x13539 * x13562;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13565 = x13541 * x74;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13566 = x13565 * x13563;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13567 = x13564 + x13566;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13568 = -x13540;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13569 = x13568 * x13562;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13570 = x13542 * x74;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13571 = x13570 * x13563;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13572 = x13569 - x13571;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13573 = -x13539;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13574 = x13573 * x13563;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13575 = x13541 * x13562;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13576 = x13574 + x13575;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13577 = x13540 * x13563;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13578 = x13542 * x13562;
// loc("cirgen/circuit/rv32im/ffpu.cpp":92:24)
auto x13579 = x13577 - x13578;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][182 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13567);
reg = x13567;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][183 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13572);
reg = x13572;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][184 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13576);
reg = x13576;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][185 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13579);
reg = x13579;
}
}
// loc("Top/Mux/4/Mux/12/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13580 = args[2][182 * steps + ((cycle - 0) & mask)];
assert(x13580 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13581 = args[2][183 * steps + ((cycle - 0) & mask)];
assert(x13581 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13582 = args[2][184 * steps + ((cycle - 0) & mask)];
assert(x13582 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13583 = args[2][185 * steps + ((cycle - 0) & mask)];
assert(x13583 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13584 = x13580 * x13539;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13585 = x13581 * x13542;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13586 = x13582 * x13541;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13587 = x13585 + x13586;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13588 = x13583 * x13540;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13589 = x13587 + x13588;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13590 = x13589 * x10;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13591 = x13584 + x13590;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13592 = x13580 * x13540;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13593 = x13581 * x13539;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13594 = x13592 + x13593;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13595 = x13582 * x13542;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13596 = x13583 * x13541;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13597 = x13595 + x13596;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13598 = x13597 * x10;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13599 = x13594 + x13598;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13600 = x13580 * x13541;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13601 = x13581 * x13540;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13602 = x13600 + x13601;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13603 = x13582 * x13539;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13604 = x13602 + x13603;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13605 = x13583 * x13542;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13606 = x13605 * x10;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13607 = x13604 + x13606;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13608 = x13580 * x13542;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13609 = x13581 * x13541;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13610 = x13608 + x13609;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13611 = x13582 * x13540;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13612 = x13610 + x13611;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13613 = x13583 * x13539;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:21)
auto x13614 = x13612 + x13613;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:6)
auto x13615 = x102 - x13591;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:6)
if (x13615 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:96");
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:6)
auto x13616 = x101 - x13599;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:6)
if (x13616 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:96");
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:6)
auto x13617 = x101 - x13607;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:6)
if (x13617 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:96");
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:6)
auto x13618 = x101 - x13614;
// loc("cirgen/circuit/rv32im/ffpu.cpp":96:6)
if (x13618 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/ffpu.cpp:96");
host_args.at(0) = x12914;
host_args.at(1) = x13539;
host_args.at(2) = x13540;
host_args.at(3) = x13541;
host_args.at(4) = x13542;
host_args.at(5) = x13580;
host_args.at(6) = x13581;
host_args.at(7) = x13582;
host_args.at(8) = x13583;
host(ctx, "log", "FFPU: Inv %%%u (%w) -> %w", host_args.data(), 9, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/Reg1"("cirgen/circuit/rv32im/ffpu.cpp":17:20))
auto x13619 = args[2][172 * steps + ((cycle - 0) & mask)];
assert(x13619 != Fp::invalid());
host_args.at(0) = x13619;
host_args.at(1) = x13580;
host_args.at(2) = x13581;
host_args.at(3) = x13582;
host_args.at(4) = x13583;
host(ctx, "log", "FFPU: %%%u = FpExt(%u, %u, %u, %u)", host_args.data(), 5, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/ffpu.cpp":43:10)
auto x13620 = x13619 + x11;
{
host_args.at(0) = x13620;
host(ctx, "isResident", "", host_args.data(), 1, host_outs.data(), 1);
auto x13621 = host_outs.at(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][186 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13621);
reg = x13621;
}
}
// loc("Top/Mux/4/Mux/12/Bit6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13622 = args[2][186 * steps + ((cycle - 0) & mask)];
assert(x13622 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":30:13)
auto x13623 = x13622 * x99;
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13580);
reg = x13580;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13581);
reg = x13581;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13582);
reg = x13582;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13583);
reg = x13583;
}
{
host_args.at(0) = x13620;
host_args.at(1) = x13580;
host_args.at(2) = x13581;
host_args.at(3) = x13582;
host_args.at(4) = x13583;
host_args.at(5) = x13623;
host(ctx, "ramWrite", "", host_args.data(), 6, host_outs.data(), 0);
}
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13624 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x13624 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13625 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x13625 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13626 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x13626 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13627 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x13627 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13620);
reg = x13620;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x12830);
reg = x12830;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13623);
reg = x13623;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13624);
reg = x13624;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13625);
reg = x13625;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13626);
reg = x13626;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13627);
reg = x13627;
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:28)
auto x13628 = x13619 + x102;
// loc("cirgen/circuit/rv32im/ffpu.cpp":33:3)
{
auto& reg = args[2][173 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13628);
reg = x13628;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][179 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/12/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13629 = args[2][169 * steps + ((cycle - 0) & mask)];
assert(x13629 != Fp::invalid());
// loc("cirgen/circuit/rv32im/ffpu.cpp":423:57)
auto x13630 = x603 + x85;
// loc("cirgen/circuit/rv32im/ffpu.cpp":423:20)
auto x13631 = x13629 - x13630;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x13632 = (x13631 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][170 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13632);
reg = x13632;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x13633 = inv(x13631);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][171 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13633);
reg = x13633;
}
}
// loc("Top/Mux/4/Mux/12/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13634 = args[2][170 * steps + ((cycle - 0) & mask)];
assert(x13634 != Fp::invalid());
if (x13634 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x13631 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x13635 = x102 - x13634;
if (x13635 != 0) {
// loc("Top/Mux/4/Mux/12/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13636 = args[2][171 * steps + ((cycle - 0) & mask)];
assert(x13636 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x13637 = x13631 * x13636;
// loc("cirgen/components/iszero.cpp":15:26)
auto x13638 = x13637 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x13638 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
// loc("Top/Mux/4/Mux/12/Bit3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13639 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x13639 != Fp::invalid());
if (x13639 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":426:5)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x73);
reg = x73;
}
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13640 = Fp(x13630.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13640);
reg = x13640;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x13641 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x13641 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13642 = x13630 - x13641;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13643 = x13642 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13644 = Fp(x13643.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13644);
reg = x13644;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x13645 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x13645 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13646 = x13643 - x13645;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13647 = x13646 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13648 = Fp(x13647.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13648);
reg = x13648;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x13649 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x13649 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13650 = x13647 - x13649;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13651 = x13650 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x13652 = Fp(x13651.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13652);
reg = x13652;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13653 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x13653 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x13654 = x13651 - x13653;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x13655 = x13654 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13655);
reg = x13655;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13656 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x13656 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x13657 = x102 - x13656;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x13658 = x13656 * x13657;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13658);
reg = x13658;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13659 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x13659 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x13660 = x99 - x13656;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x13661 = x13659 * x13660;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x13661 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("cirgen/circuit/rv32im/ffpu.cpp":432:25)
auto x13662 = x102 - x13639;
if (x13662 != 0) {
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][181 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13635);
reg = x13635;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][180 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13634);
reg = x13634;
}
}
// loc("Top/Mux/4/Mux/12/Bit5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13663 = args[2][181 * steps + ((cycle - 0) & mask)];
assert(x13663 != Fp::invalid());
if (x13663 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":438:5)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x73);
reg = x73;
}
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x13664 = x13630 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13665 = Fp(x13664.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13665);
reg = x13665;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x13666 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x13666 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13667 = x13664 - x13666;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13668 = x13667 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13669 = Fp(x13668.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13669);
reg = x13669;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x13670 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x13670 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13671 = x13668 - x13670;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13672 = x13671 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13673 = Fp(x13672.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13673);
reg = x13673;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x13674 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x13674 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13675 = x13672 - x13674;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13676 = x13675 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x13677 = Fp(x13676.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13677);
reg = x13677;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13678 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x13678 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x13679 = x13676 - x13678;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x13680 = x13679 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13680);
reg = x13680;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13681 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x13681 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x13682 = x102 - x13681;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x13683 = x13681 * x13682;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13683);
reg = x13683;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13684 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x13684 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x13685 = x99 - x13681;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x13686 = x13684 * x13685;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x13686 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
}
// loc("Top/Mux/4/Mux/12/Bit4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13687 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x13687 != Fp::invalid());
if (x13687 != 0) {
// loc("cirgen/circuit/rv32im/ffpu.cpp":443:5)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
// loc("Top/Mux/4/Mux/12/Reg3"("cirgen/circuit/rv32im/ffpu.cpp":444:29))
auto x13688 = args[2][174 * steps + ((cycle - 0) & mask)];
assert(x13688 != Fp::invalid());
host_args.at(0) = x13688;
host(ctx, "log", "Returning to %x", host_args.data(), 1, host_outs.data(), 0);
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x13689 = x13688 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13690 = Fp(x13689.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13690);
reg = x13690;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x13691 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x13691 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13692 = x13689 - x13691;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13693 = x13692 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13694 = Fp(x13693.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13694);
reg = x13694;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x13695 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x13695 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13696 = x13693 - x13695;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13697 = x13696 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13698 = Fp(x13697.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13698);
reg = x13698;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x13699 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x13699 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13700 = x13697 - x13699;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13701 = x13700 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x13702 = Fp(x13701.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13702);
reg = x13702;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13703 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x13703 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x13704 = x13701 - x13703;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x13705 = x13704 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13705);
reg = x13705;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13706 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x13706 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x13707 = x102 - x13706;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x13708 = x13706 * x13707;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13708);
reg = x13708;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13709 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x13709 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x13710 = x99 - x13706;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x13711 = x13709 * x13710;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x13711 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
}
}
// loc("Top/Mux/4/OneHot/Reg13"("./cirgen/components/mux.h":37:25))
auto x13712 = args[2][107 * steps + ((cycle - 0) & mask)];
assert(x13712 != Fp::invalid());
if (x13712 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13713 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x13713 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":14:23)
auto x13714 = x603 + x85;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13715 = Fp(x13714.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][10 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13715);
reg = x13715;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg"("cirgen/components/bytes.cpp":83:16))
auto x13716 = args[2][10 * steps + ((cycle - 0) & mask)];
assert(x13716 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13717 = x13714 - x13716;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13718 = x13717 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13719 = Fp(x13718.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][11 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13719);
reg = x13719;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x13720 = args[2][11 * steps + ((cycle - 0) & mask)];
assert(x13720 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13721 = x13718 - x13720;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13722 = x13721 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13723 = Fp(x13722.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][12 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13723);
reg = x13723;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg"("cirgen/components/bytes.cpp":83:16))
auto x13724 = args[2][12 * steps + ((cycle - 0) & mask)];
assert(x13724 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13725 = x13722 - x13724;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13726 = x13725 * x96;
{
// loc("cirgen/circuit/rv32im/body.cpp":17:26)
auto x13727 = Fp(x13726.asUInt32() & x84.asUInt32());
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][72 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13727);
reg = x13727;
}
}
// loc("Top/Mux/4/PCReg/Twit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13728 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x13728 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":18:18)
auto x13729 = x13726 - x13728;
// loc("cirgen/circuit/rv32im/body.cpp":18:17)
auto x13730 = x13729 * x83;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][73 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13730);
reg = x13730;
}
// loc("Top/Mux/4/PCReg/Twit1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13731 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x13731 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":22:23)
auto x13732 = x102 - x13731;
// loc("cirgen/circuit/rv32im/body.cpp":22:15)
auto x13733 = x13731 * x13732;
// loc("cirgen/circuit/rv32im/body.cpp":22:3)
{
auto& reg = args[2][92 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13733);
reg = x13733;
}
// loc("Top/Mux/4/PCReg/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13734 = args[2][92 * steps + ((cycle - 0) & mask)];
assert(x13734 != Fp::invalid());
// loc("cirgen/circuit/rv32im/body.cpp":23:17)
auto x13735 = x99 - x13731;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
auto x13736 = x13734 * x13735;
// loc("cirgen/circuit/rv32im/body.cpp":23:7)
if (x13736 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/body.cpp:23");
host_args.at(0) = x603;
host(ctx, "log", " PageFault: PC = 0x%x", host_args.data(), 1, host_outs.data(), 0);
// loc("Top/Code/OneHot/Reg4"("cirgen/circuit/rv32im/page_fault.cpp":84:67))
auto x13737 = args[0][5 * steps + ((cycle - 1) & mask)];
assert(x13737 != Fp::invalid());
if (x13737 != 0) {
// loc("Top/Mux/4/OneHot/Reg13"("cirgen/circuit/rv32im/page_fault.cpp":86:79))
auto x13738 = args[2][107 * steps + ((cycle - 1) & mask)];
assert(x13738 != Fp::invalid());
if (x13738 != 0) {
// loc("Top/Mux/4/Mux/13/IsZero1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13739 = args[2][118 * steps + ((cycle - 1) & mask)];
assert(x13739 != Fp::invalid());
// loc("cirgen/circuit/rv32im/page_fault.cpp":89:23)
auto x13740 = x102 - x13739;
// loc("cirgen/circuit/rv32im/page_fault.cpp":89:7)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13740);
reg = x13740;
}
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":91:27)
auto x13741 = x102 - x13738;
if (x13741 != 0) {
// loc("cirgen/circuit/rv32im/page_fault.cpp":91:31)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":93:20)
auto x13742 = x102 - x13737;
if (x13742 != 0) {
// loc("cirgen/circuit/rv32im/page_fault.cpp":93:24)
{
auto& reg = args[2][108 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Mux/4/Mux/13/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13743 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x13743 != Fp::invalid());
if (x13743 != 0) {
// loc("Top/Mux/4/Mux/13/Reg3"("cirgen/circuit/rv32im/page_fault.cpp":96:44))
auto x13744 = args[2][111 * steps + ((cycle - 1) & mask)];
assert(x13744 != Fp::invalid());
// loc("cirgen/circuit/rv32im/page_fault.cpp":96:5)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13744);
reg = x13744;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":99:20)
auto x13745 = x102 - x13743;
if (x13745 != 0) {
{
host_args.at(0) = x603;
host(ctx, "pageRead", "", host_args.data(), 1, host_outs.data(), 2);
auto x13746 = host_outs.at(0);
auto x13747 = host_outs.at(1);
// loc("cirgen/circuit/rv32im/page_fault.cpp":102:7)
{
auto& reg = args[2][111 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13746);
reg = x13746;
}
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][112 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13747);
reg = x13747;
}
}
}
// loc("Top/Mux/4/Mux/13/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13748 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x13748 != Fp::invalid());
// loc("cirgen/circuit/rv32im/page_fault.cpp":109:20)
auto x13749 = x13748 - x6;
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x13750 = (x13749 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][115 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13750);
reg = x13750;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x13751 = inv(x13749);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][116 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13751);
reg = x13751;
}
}
// loc("Top/Mux/4/Mux/13/IsZero/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13752 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x13752 != Fp::invalid());
if (x13752 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x13749 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x13753 = x102 - x13752;
if (x13753 != 0) {
// loc("Top/Mux/4/Mux/13/IsZero/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13754 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x13754 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x13755 = x13749 * x13754;
// loc("cirgen/components/iszero.cpp":15:26)
auto x13756 = x13755 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x13756 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
if (x13752 != 0) {
// loc("cirgen/circuit/rv32im/page_fault.cpp":111:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x74);
reg = x74;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":112:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
}
if (x13753 != 0) {
// loc("cirgen/circuit/rv32im/page_fault.cpp":115:5)
{
auto& reg = args[2][113 * steps + cycle];
assert(reg == Fp::invalid() || reg == x66);
reg = x66;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":116:5)
{
auto& reg = args[2][114 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
if (x13745 != 0) {
// loc("Top/Mux/4/Mux/13/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13757 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x13757 != Fp::invalid());
// loc("cirgen/circuit/rv32im/page_fault.cpp":122:38)
auto x13758 = x102 - x13757;
// loc("cirgen/circuit/rv32im/page_fault.cpp":122:37)
auto x13759 = x13758 * x18;
// loc("cirgen/circuit/rv32im/page_fault.cpp":122:22)
auto x13760 = x13757 + x13759;
// loc("cirgen/circuit/rv32im/page_fault.cpp":123:22)
auto x13761 = x13757 * x18;
// loc("cirgen/circuit/rv32im/page_fault.cpp":123:51)
auto x13762 = x13758 * x5;
// loc("cirgen/circuit/rv32im/page_fault.cpp":123:22)
auto x13763 = x13761 + x13762;
// loc("cirgen/circuit/rv32im/page_fault.cpp":130:17)
auto x13764 = x13748 - x13760;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13765 = Fp(x13764.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][13 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13765);
reg = x13765;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement1/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x13766 = args[2][13 * steps + ((cycle - 0) & mask)];
assert(x13766 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13767 = x13764 - x13766;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13768 = x13767 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13769 = Fp(x13768.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][14 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13769);
reg = x13769;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement2/Reg"("cirgen/components/bytes.cpp":83:16))
auto x13770 = args[2][14 * steps + ((cycle - 0) & mask)];
assert(x13770 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13771 = x13768 - x13770;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13772 = x13771 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][74 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13772);
reg = x13772;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":131:17)
auto x13773 = x13763 - x102;
// loc("cirgen/circuit/rv32im/page_fault.cpp":131:17)
auto x13774 = x13773 - x13748;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13775 = Fp(x13774.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][15 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13775);
reg = x13775;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement2/Reg1"("cirgen/components/bytes.cpp":83:16))
auto x13776 = args[2][15 * steps + ((cycle - 0) & mask)];
assert(x13776 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13777 = x13774 - x13776;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13778 = x13777 * x96;
{
// loc("cirgen/components/bytes.cpp":82:21)
auto x13779 = Fp(x13778.asUInt32() & x98.asUInt32());
// loc("cirgen/components/bytes.cpp":82:12)
{
auto& reg = args[2][16 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13779);
reg = x13779;
}
}
// loc("Top/Mux/4/BytesBody/PlonkBody/BytesPlonkElement3/Reg"("cirgen/components/bytes.cpp":83:16))
auto x13780 = args[2][16 * steps + ((cycle - 0) & mask)];
assert(x13780 != Fp::invalid());
// loc("cirgen/components/bytes.cpp":83:11)
auto x13781 = x13778 - x13780;
// loc("cirgen/components/bytes.cpp":83:10)
auto x13782 = x13781 * x96;
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][75 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13782);
reg = x13782;
}
if (x13757 != 0) {
// loc("cirgen/circuit/rv32im/page_fault.cpp":134:7)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x4);
reg = x4;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":54:12)
auto x13783 = x13748 * x29;
// loc("cirgen/circuit/rv32im/page_fault.cpp":54:12)
auto x13784 = x13783 * x83;
// loc("Top/Mux/4/Mux/13/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13785 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x13785 != Fp::invalid());
// loc("cirgen/circuit/rv32im/page_fault.cpp":170:16)
auto x13786 = x13785 * x85;
// loc("cirgen/circuit/rv32im/page_fault.cpp":174:9)
auto x13787 = x13784 + x13786;
// loc("cirgen/circuit/rv32im/page_fault.cpp":174:8)
auto x13788 = x13787 * x85;
host_args.at(0) = x13785;
host_args.at(1) = x13748;
host_args.at(2) = x13788;
host(ctx, "log", " count: %u, pageIndex: 0x%x, pageAddr: 0x%x", host_args.data(), 3, host_outs.data(), 0);
{
host_args.at(0) = x13787;
host_args.at(1) = x101;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13789 = host_outs.at(0);
auto x13790 = host_outs.at(1);
auto x13791 = host_outs.at(2);
auto x13792 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13789);
reg = x13789;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13790);
reg = x13790;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13791);
reg = x13791;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13792);
reg = x13792;
}
}
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13793 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x13793 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13794 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x13794 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13795 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x13795 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13796 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x13796 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13787);
reg = x13787;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13713);
reg = x13713;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13793);
reg = x13793;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13794);
reg = x13794;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13795);
reg = x13795;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13796);
reg = x13796;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":176:32)
auto x13797 = x13787 + x102;
{
host_args.at(0) = x13797;
host_args.at(1) = x101;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13798 = host_outs.at(0);
auto x13799 = host_outs.at(1);
auto x13800 = host_outs.at(2);
auto x13801 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13798);
reg = x13798;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13799);
reg = x13799;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13800);
reg = x13800;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13801);
reg = x13801;
}
}
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13802 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x13802 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13803 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x13803 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13804 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x13804 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13805 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x13805 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13797);
reg = x13797;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13713);
reg = x13713;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13802);
reg = x13802;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13803);
reg = x13803;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13804);
reg = x13804;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13805);
reg = x13805;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":176:32)
auto x13806 = x13787 + x99;
{
host_args.at(0) = x13806;
host_args.at(1) = x101;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13807 = host_outs.at(0);
auto x13808 = host_outs.at(1);
auto x13809 = host_outs.at(2);
auto x13810 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13807);
reg = x13807;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13808);
reg = x13808;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13809);
reg = x13809;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13810);
reg = x13810;
}
}
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13811 = args[2][137 * steps + ((cycle - 0) & mask)];
assert(x13811 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13812 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x13812 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13813 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x13813 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13814 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x13814 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13806);
reg = x13806;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13713);
reg = x13713;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13811);
reg = x13811;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13812);
reg = x13812;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13813);
reg = x13813;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13814);
reg = x13814;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":176:32)
auto x13815 = x13787 + x84;
{
host_args.at(0) = x13815;
host_args.at(1) = x101;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13816 = host_outs.at(0);
auto x13817 = host_outs.at(1);
auto x13818 = host_outs.at(2);
auto x13819 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][144 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13816);
reg = x13816;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][145 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13817);
reg = x13817;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][146 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13818);
reg = x13818;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][147 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13819);
reg = x13819;
}
}
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13820 = args[2][144 * steps + ((cycle - 0) & mask)];
assert(x13820 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13821 = args[2][145 * steps + ((cycle - 0) & mask)];
assert(x13821 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13822 = args[2][146 * steps + ((cycle - 0) & mask)];
assert(x13822 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13823 = args[2][147 * steps + ((cycle - 0) & mask)];
assert(x13823 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13815);
reg = x13815;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13713);
reg = x13713;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][143 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][144 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13820);
reg = x13820;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][145 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13821);
reg = x13821;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][146 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13822);
reg = x13822;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][147 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13823);
reg = x13823;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":136:7)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x72);
reg = x72;
}
}
if (x13758 != 0) {
// loc("cirgen/circuit/rv32im/page_fault.cpp":140:28)
auto x13824 = x13748 - x18;
// loc("Top/Mux/4/Mux/13/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13825 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x13825 != Fp::invalid());
// loc("cirgen/circuit/rv32im/page_fault.cpp":140:28)
auto x13826 = x13824 + x13825;
// loc("cirgen/circuit/rv32im/page_fault.cpp":141:40)
auto x13827 = x13826 * x77;
// loc("cirgen/circuit/rv32im/page_fault.cpp":141:23)
auto x13828 = x13827 + x3;
// loc("cirgen/circuit/rv32im/page_fault.cpp":142:7)
{
auto& reg = args[2][109 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13828);
reg = x13828;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":143:7)
{
auto& reg = args[2][110 * steps + cycle];
assert(reg == Fp::invalid() || reg == x2);
reg = x2;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][143 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][144 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][145 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][146 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][147 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":147:7)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":148:7)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x76);
reg = x76;
}
}
}
if (x13743 != 0) {
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][13 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][14 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][74 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][15 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/bytes.cpp":87:3)
{
auto& reg = args[2][16 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":57:23)
{
auto& reg = args[2][75 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("Top/Mux/4/Mux/13/Reg6"("cirgen/circuit/rv32im/page_fault.cpp":156:40))
auto x13829 = args[2][117 * steps + ((cycle - 1) & mask)];
assert(x13829 != Fp::invalid());
// loc("cirgen/circuit/rv32im/page_fault.cpp":156:40)
auto x13830 = x13829 - x102;
// loc("cirgen/circuit/rv32im/page_fault.cpp":156:5)
{
auto& reg = args[2][117 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13830);
reg = x13830;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":54:12)
auto x13831 = x13748 * x29;
// loc("cirgen/circuit/rv32im/page_fault.cpp":54:12)
auto x13832 = x13831 * x83;
// loc("Top/Mux/4/Mux/13/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13833 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x13833 != Fp::invalid());
// loc("cirgen/circuit/rv32im/page_fault.cpp":170:16)
auto x13834 = x13833 * x85;
// loc("cirgen/circuit/rv32im/page_fault.cpp":174:9)
auto x13835 = x13832 + x13834;
// loc("cirgen/circuit/rv32im/page_fault.cpp":174:8)
auto x13836 = x13835 * x85;
host_args.at(0) = x13833;
host_args.at(1) = x13748;
host_args.at(2) = x13836;
host(ctx, "log", " count: %u, pageIndex: 0x%x, pageAddr: 0x%x", host_args.data(), 3, host_outs.data(), 0);
{
host_args.at(0) = x13835;
host_args.at(1) = x101;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13837 = host_outs.at(0);
auto x13838 = host_outs.at(1);
auto x13839 = host_outs.at(2);
auto x13840 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13837);
reg = x13837;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13838);
reg = x13838;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13839);
reg = x13839;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13840);
reg = x13840;
}
}
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13841 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x13841 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13842 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x13842 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13843 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x13843 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13844 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x13844 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][120 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13835);
reg = x13835;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][121 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13713);
reg = x13713;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13841);
reg = x13841;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13842);
reg = x13842;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13843);
reg = x13843;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13844);
reg = x13844;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":176:32)
auto x13845 = x13835 + x102;
{
host_args.at(0) = x13845;
host_args.at(1) = x101;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13846 = host_outs.at(0);
auto x13847 = host_outs.at(1);
auto x13848 = host_outs.at(2);
auto x13849 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13846);
reg = x13846;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13847);
reg = x13847;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13848);
reg = x13848;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13849);
reg = x13849;
}
}
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13850 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x13850 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13851 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x13851 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13852 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x13852 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13853 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x13853 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13845);
reg = x13845;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13713);
reg = x13713;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13850);
reg = x13850;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13851);
reg = x13851;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13852);
reg = x13852;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13853);
reg = x13853;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":176:32)
auto x13854 = x13835 + x99;
{
host_args.at(0) = x13854;
host_args.at(1) = x101;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13855 = host_outs.at(0);
auto x13856 = host_outs.at(1);
auto x13857 = host_outs.at(2);
auto x13858 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13855);
reg = x13855;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13856);
reg = x13856;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13857);
reg = x13857;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13858);
reg = x13858;
}
}
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13859 = args[2][137 * steps + ((cycle - 0) & mask)];
assert(x13859 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13860 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x13860 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13861 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x13861 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13862 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x13862 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13854);
reg = x13854;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13713);
reg = x13713;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13859);
reg = x13859;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13860);
reg = x13860;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13861);
reg = x13861;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13862);
reg = x13862;
}
// loc("cirgen/circuit/rv32im/page_fault.cpp":176:32)
auto x13863 = x13835 + x84;
{
host_args.at(0) = x13863;
host_args.at(1) = x101;
host(ctx, "ramRead", "", host_args.data(), 2, host_outs.data(), 4);
auto x13864 = host_outs.at(0);
auto x13865 = host_outs.at(1);
auto x13866 = host_outs.at(2);
auto x13867 = host_outs.at(3);
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][144 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13864);
reg = x13864;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][145 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13865);
reg = x13865;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][146 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13866);
reg = x13866;
}
// loc("cirgen/components/u32.cpp":82:5)
{
auto& reg = args[2][147 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13867);
reg = x13867;
}
}
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13868 = args[2][144 * steps + ((cycle - 0) & mask)];
assert(x13868 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13869 = args[2][145 * steps + ((cycle - 0) & mask)];
assert(x13869 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13870 = args[2][146 * steps + ((cycle - 0) & mask)];
assert(x13870 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13871 = args[2][147 * steps + ((cycle - 0) & mask)];
assert(x13871 != Fp::invalid());
// loc("cirgen/components/ram.cpp":130:3)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13863);
reg = x13863;
}
// loc("cirgen/components/ram.cpp":131:3)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13713);
reg = x13713;
}
// loc("cirgen/components/ram.cpp":132:3)
{
auto& reg = args[2][143 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][144 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13868);
reg = x13868;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][145 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13869);
reg = x13869;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][146 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13870);
reg = x13870;
}
// loc("cirgen/components/u32.cpp":34:5)
{
auto& reg = args[2][147 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13871);
reg = x13871;
}
}
// loc("Top/Mux/4/Mux/13/Reg6"("./cirgen/compiler/edsl/component.h":85:27))
auto x13872 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x13872 != Fp::invalid());
{
// loc("cirgen/components/iszero.cpp":11:24)
auto x13873 = (x13872 == 0) ? Fp(1) : Fp(0);
// loc("./cirgen/components/bits.h":18:23)
{
auto& reg = args[2][118 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13873);
reg = x13873;
}
// loc("cirgen/components/iszero.cpp":12:21)
auto x13874 = inv(x13872);
// loc("cirgen/components/iszero.cpp":12:5)
{
auto& reg = args[2][119 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13874);
reg = x13874;
}
}
// loc("Top/Mux/4/Mux/13/IsZero1/Bit/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13875 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x13875 != Fp::invalid());
if (x13875 != 0) {
// loc("cirgen/components/iszero.cpp":14:23)
if (x13872 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:14");
}
// loc("cirgen/components/iszero.cpp":15:19)
auto x13876 = x102 - x13875;
if (x13876 != 0) {
// loc("Top/Mux/4/Mux/13/IsZero1/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13877 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x13877 != Fp::invalid());
// loc("cirgen/components/iszero.cpp":15:26)
auto x13878 = x13872 * x13877;
// loc("cirgen/components/iszero.cpp":15:26)
auto x13879 = x13878 - x102;
// loc("cirgen/components/iszero.cpp":15:26)
if (x13879 != 0) throw std::runtime_error("eqz failed at: cirgen/components/iszero.cpp:15");
}
if (x13743 != 0) {
if (x13875 != 0) {
// loc("cirgen/circuit/rv32im/page_fault.cpp":163:31)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x82);
reg = x82;
}
}
if (x13876 != 0) {
// loc("cirgen/circuit/rv32im/page_fault.cpp":164:35)
{
auto& reg = args[2][93 * steps + cycle];
assert(reg == Fp::invalid() || reg == x72);
reg = x72;
}
}
}
}
}
// loc("Top/Code/OneHot/Reg5"("./cirgen/components/mux.h":37:25))
auto x13880 = args[0][6 * steps + ((cycle - 0) & mask)];
assert(x13880 != Fp::invalid());
if (x13880 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13881 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x13881 != Fp::invalid());
host_args.at(0) = x13881;
host(ctx, "log", "%u: RamFini", host_args.data(), 1, host_outs.data(), 0);
// loc("Top/Mux/4/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13882 = args[2][95 * steps + ((cycle - 1) & mask)];
assert(x13882 != Fp::invalid());
// loc("Top/Mux/4/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13883 = args[2][96 * steps + ((cycle - 1) & mask)];
assert(x13883 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13884 = x13883 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x13885 = x13882 + x13884;
// loc("Top/Mux/4/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13886 = args[2][97 * steps + ((cycle - 1) & mask)];
assert(x13886 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13887 = x13886 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x13888 = x13885 + x13887;
// loc("Top/Mux/4/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13889 = args[2][98 * steps + ((cycle - 1) & mask)];
assert(x13889 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13890 = x13889 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x13891 = x13888 + x13890;
// loc("Top/Mux/4/OneHot/Reg5"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13892 = args[2][99 * steps + ((cycle - 1) & mask)];
assert(x13892 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13893 = x13892 * x80;
// loc("./cirgen/components/onehot.h":44:13)
auto x13894 = x13891 + x13893;
// loc("Top/Mux/4/OneHot/Reg6"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13895 = args[2][100 * steps + ((cycle - 1) & mask)];
assert(x13895 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13896 = x13895 * x79;
// loc("./cirgen/components/onehot.h":44:13)
auto x13897 = x13894 + x13896;
// loc("Top/Mux/4/OneHot/Reg7"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13898 = args[2][101 * steps + ((cycle - 1) & mask)];
assert(x13898 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13899 = x13898 * x78;
// loc("./cirgen/components/onehot.h":44:13)
auto x13900 = x13897 + x13899;
// loc("Top/Mux/4/OneHot/Reg8"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13901 = args[2][102 * steps + ((cycle - 1) & mask)];
assert(x13901 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13902 = x13901 * x77;
// loc("./cirgen/components/onehot.h":44:13)
auto x13903 = x13900 + x13902;
// loc("Top/Mux/4/OneHot/Reg9"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13904 = args[2][103 * steps + ((cycle - 1) & mask)];
assert(x13904 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13905 = x13904 * x76;
// loc("./cirgen/components/onehot.h":44:13)
auto x13906 = x13903 + x13905;
// loc("Top/Mux/4/OneHot/Reg10"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13907 = args[2][104 * steps + ((cycle - 1) & mask)];
assert(x13907 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13908 = x13907 * x75;
// loc("./cirgen/components/onehot.h":44:13)
auto x13909 = x13906 + x13908;
// loc("Top/Mux/4/OneHot/Reg11"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13910 = args[2][105 * steps + ((cycle - 1) & mask)];
assert(x13910 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13911 = x13910 * x74;
// loc("./cirgen/components/onehot.h":44:13)
auto x13912 = x13909 + x13911;
// loc("Top/Mux/4/OneHot/Reg12"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13913 = args[2][106 * steps + ((cycle - 1) & mask)];
assert(x13913 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13914 = x13913 * x73;
// loc("./cirgen/components/onehot.h":44:13)
auto x13915 = x13912 + x13914;
// loc("Top/Mux/4/OneHot/Reg13"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13916 = args[2][107 * steps + ((cycle - 1) & mask)];
assert(x13916 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13917 = x13916 * x72;
// loc("./cirgen/components/onehot.h":44:13)
auto x13918 = x13915 + x13917;
// loc("cirgen/circuit/rv32im/top.cpp":49:38)
auto x13919 = x13918 - x77;
// loc("cirgen/circuit/rv32im/top.cpp":49:38)
if (x13919 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/top.cpp:49");
// loc("Top/Mux/4/Mux/8/OneHot/Reg1"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13920 = args[2][177 * steps + ((cycle - 1) & mask)];
assert(x13920 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/OneHot/Reg2"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13921 = args[2][178 * steps + ((cycle - 1) & mask)];
assert(x13921 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13922 = x13921 * x99;
// loc("./cirgen/components/onehot.h":44:13)
auto x13923 = x13920 + x13922;
// loc("Top/Mux/4/Mux/8/OneHot/Reg3"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13924 = args[2][179 * steps + ((cycle - 1) & mask)];
assert(x13924 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13925 = x13924 * x84;
// loc("./cirgen/components/onehot.h":44:13)
auto x13926 = x13923 + x13925;
// loc("Top/Mux/4/Mux/8/OneHot/Reg4"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13927 = args[2][180 * steps + ((cycle - 1) & mask)];
assert(x13927 != Fp::invalid());
// loc("./cirgen/components/onehot.h":44:19)
auto x13928 = x13927 * x85;
// loc("./cirgen/components/onehot.h":44:13)
auto x13929 = x13926 + x13928;
// loc("cirgen/circuit/rv32im/top.cpp":51:39)
if (x13929 != 0) throw std::runtime_error("eqz failed at: cirgen/circuit/rv32im/top.cpp:51");
}
// loc("Top/Code/OneHot/Reg6"("./cirgen/components/mux.h":37:25))
auto x13930 = args[0][7 * steps + ((cycle - 0) & mask)];
assert(x13930 != Fp::invalid());
if (x13930 != 0) {
// loc("Top/Code/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13931 = args[0][0 * steps + ((cycle - 0) & mask)];
assert(x13931 != Fp::invalid());
host_args.at(0) = x13931;
host(ctx, "log", "%u: BytesFini", host_args.data(), 1, host_outs.data(), 0);
}
// loc("Top/Code/OneHot/Reg"("cirgen/circuit/rv32im/top.cpp":72:27))
auto x13932 = args[0][1 * steps + ((cycle - 0) & mask)];
assert(x13932 != Fp::invalid());
// loc("cirgen/circuit/rv32im/top.cpp":72:16)
auto x13933 = x13932 + x103;
// loc("cirgen/circuit/rv32im/top.cpp":72:16)
auto x13934 = x13933 + x428;
// loc("cirgen/circuit/rv32im/top.cpp":72:16)
auto x13935 = x13934 + x481;
// loc("cirgen/circuit/rv32im/top.cpp":72:16)
auto x13936 = x13935 + x589;
// loc("cirgen/circuit/rv32im/top.cpp":72:16)
auto x13937 = x13936 + x13880;
// loc("cirgen/circuit/rv32im/top.cpp":72:16)
auto x13938 = x13937 + x13930;
if (x589 != 0) {
// loc("Top/Mux/4/OneHot/Reg8"("cirgen/circuit/rv32im/top.cpp":80:19))
auto x13939 = args[2][102 * steps + ((cycle - 0) & mask)];
assert(x13939 != Fp::invalid());
if (x13939 != 0) {
// loc("Top/Mux/4/Mux/8/OneHot/Reg"("cirgen/circuit/rv32im/top.cpp":83:20))
auto x13940 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x13940 != Fp::invalid());
// loc("cirgen/circuit/rv32im/top.cpp":84:7)
{
auto& reg = args[2][9 * steps + cycle];
assert(reg == Fp::invalid() || reg == x13940);
reg = x13940;
}
}
// loc("cirgen/circuit/rv32im/top.cpp":86:19)
auto x13941 = x102 - x13939;
if (x13941 != 0) {
// loc("cirgen/circuit/rv32im/top.cpp":86:23)
{
auto& reg = args[2][9 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/circuit/rv32im/top.cpp":88:23)
auto x13942 = x13938 - x589;
if (x13942 != 0) {
// loc("cirgen/circuit/rv32im/top.cpp":88:27)
{
auto& reg = args[2][9 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
// loc("Top/Reg"("./cirgen/compiler/edsl/edsl.h":111:61))
auto x13943 = args[2][9 * steps + ((cycle - 0) & mask)];
assert(x13943 != Fp::invalid());
// loc("cirgen/circuit/rv32im/top.cpp":89:10)
auto x13944 = x102 - x13943;
if (x428 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
if (x481 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
if (x589 != 0) {
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13945 = args[2][94 * steps + ((cycle - 0) & mask)];
assert(x13945 != Fp::invalid());
if (x13945 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13946 = args[2][95 * steps + ((cycle - 0) & mask)];
assert(x13946 != Fp::invalid());
if (x13946 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13947 = args[2][96 * steps + ((cycle - 0) & mask)];
assert(x13947 != Fp::invalid());
if (x13947 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13948 = args[2][97 * steps + ((cycle - 0) & mask)];
assert(x13948 != Fp::invalid());
if (x13948 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13949 = args[2][98 * steps + ((cycle - 0) & mask)];
assert(x13949 != Fp::invalid());
if (x13949 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13950 = args[2][99 * steps + ((cycle - 0) & mask)];
assert(x13950 != Fp::invalid());
if (x13950 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13951 = args[2][100 * steps + ((cycle - 0) & mask)];
assert(x13951 != Fp::invalid());
if (x13951 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][13 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][14 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][15 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][16 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][17 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][18 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][19 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][20 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][21 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][22 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][23 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][24 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][25 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][74 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][75 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][76 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][77 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][78 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13952 = args[2][101 * steps + ((cycle - 0) & mask)];
assert(x13952 != Fp::invalid());
if (x13952 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13953 = args[2][102 * steps + ((cycle - 0) & mask)];
assert(x13953 != Fp::invalid());
if (x13953 != 0) {
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13954 = args[2][176 * steps + ((cycle - 0) & mask)];
assert(x13954 != Fp::invalid());
if (x13954 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][122 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][123 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][124 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][125 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][126 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][127 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][128 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][129 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][130 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][131 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][132 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][133 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][134 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][135 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13955 = args[2][177 * steps + ((cycle - 0) & mask)];
assert(x13955 != Fp::invalid());
if (x13955 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13956 = args[2][178 * steps + ((cycle - 0) & mask)];
assert(x13956 != Fp::invalid());
if (x13956 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13957 = args[2][179 * steps + ((cycle - 0) & mask)];
assert(x13957 != Fp::invalid());
if (x13957 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13958 = args[2][180 * steps + ((cycle - 0) & mask)];
assert(x13958 != Fp::invalid());
if (x13958 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":43:3)
{
auto& reg = args[2][136 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":44:3)
{
auto& reg = args[2][137 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/ram.cpp":45:3)
{
auto& reg = args[2][138 * steps + cycle];
assert(reg == Fp::invalid() || reg == x102);
reg = x102;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][139 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][140 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][141 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("cirgen/components/u32.cpp":28:5)
{
auto& reg = args[2][142 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13959 = args[2][103 * steps + ((cycle - 0) & mask)];
assert(x13959 != Fp::invalid());
if (x13959 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13960 = args[2][104 * steps + ((cycle - 0) & mask)];
assert(x13960 != Fp::invalid());
if (x13960 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13961 = args[2][105 * steps + ((cycle - 0) & mask)];
assert(x13961 != Fp::invalid());
if (x13961 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13962 = args[2][106 * steps + ((cycle - 0) & mask)];
assert(x13962 != Fp::invalid());
if (x13962 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][26 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][27 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][28 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][79 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x13963 = args[2][107 * steps + ((cycle - 0) & mask)];
assert(x13963 != Fp::invalid());
if (x13963 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][29 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][30 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][31 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][32 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][33 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][34 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][35 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][36 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][37 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][38 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][39 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][40 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][41 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][80 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][81 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][82 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][83 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][84 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][85 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][86 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][87 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][88 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][89 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][90 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
// loc("./cirgen/components/bits.h":28:46)
{
auto& reg = args[2][91 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
}
if (x13880 != 0) {
{
// loc("./cirgen/components/bytes.h":37:30)
{
auto& reg = args[2][13 * steps + cycle];
assert(reg == Fp::invalid() || reg == x101);
reg = x101;
}
}
}
if (x428 != 0) {
{
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13964 = args[2][55 * steps + ((cycle - 0) & mask)];
assert(x13964 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13965 = args[2][56 * steps + ((cycle - 0) & mask)];
assert(x13965 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13966 = args[2][57 * steps + ((cycle - 0) & mask)];
assert(x13966 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13967 = args[2][58 * steps + ((cycle - 0) & mask)];
assert(x13967 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13968 = args[2][59 * steps + ((cycle - 0) & mask)];
assert(x13968 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13969 = args[2][60 * steps + ((cycle - 0) & mask)];
assert(x13969 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13970 = args[2][61 * steps + ((cycle - 0) & mask)];
assert(x13970 != Fp::invalid());
host_args.at(0) = x13964;
host_args.at(1) = x13965;
host_args.at(2) = x13966;
host_args.at(3) = x13967;
host_args.at(4) = x13968;
host_args.at(5) = x13969;
host_args.at(6) = x13970;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13971 = args[2][62 * steps + ((cycle - 0) & mask)];
assert(x13971 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13972 = args[2][63 * steps + ((cycle - 0) & mask)];
assert(x13972 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13973 = args[2][64 * steps + ((cycle - 0) & mask)];
assert(x13973 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13974 = args[2][65 * steps + ((cycle - 0) & mask)];
assert(x13974 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13975 = args[2][66 * steps + ((cycle - 0) & mask)];
assert(x13975 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13976 = args[2][67 * steps + ((cycle - 0) & mask)];
assert(x13976 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13977 = args[2][68 * steps + ((cycle - 0) & mask)];
assert(x13977 != Fp::invalid());
host_args.at(0) = x13971;
host_args.at(1) = x13972;
host_args.at(2) = x13973;
host_args.at(3) = x13974;
host_args.at(4) = x13975;
host_args.at(5) = x13976;
host_args.at(6) = x13977;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13978 = args[2][69 * steps + ((cycle - 0) & mask)];
assert(x13978 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13979 = args[2][70 * steps + ((cycle - 0) & mask)];
assert(x13979 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13980 = args[2][71 * steps + ((cycle - 0) & mask)];
assert(x13980 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13981 = args[2][72 * steps + ((cycle - 0) & mask)];
assert(x13981 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13982 = args[2][73 * steps + ((cycle - 0) & mask)];
assert(x13982 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13983 = args[2][74 * steps + ((cycle - 0) & mask)];
assert(x13983 != Fp::invalid());
// loc("Top/Mux/2/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13984 = args[2][75 * steps + ((cycle - 0) & mask)];
assert(x13984 != Fp::invalid());
host_args.at(0) = x13978;
host_args.at(1) = x13979;
host_args.at(2) = x13980;
host_args.at(3) = x13981;
host_args.at(4) = x13982;
host_args.at(5) = x13983;
host_args.at(6) = x13984;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
if (x481 != 0) {
{
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13985 = args[2][94 * steps + ((cycle - 0) & mask)];
assert(x13985 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13986 = args[2][95 * steps + ((cycle - 0) & mask)];
assert(x13986 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13987 = args[2][96 * steps + ((cycle - 0) & mask)];
assert(x13987 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13988 = args[2][97 * steps + ((cycle - 0) & mask)];
assert(x13988 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13989 = args[2][98 * steps + ((cycle - 0) & mask)];
assert(x13989 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13990 = args[2][99 * steps + ((cycle - 0) & mask)];
assert(x13990 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13991 = args[2][100 * steps + ((cycle - 0) & mask)];
assert(x13991 != Fp::invalid());
host_args.at(0) = x13985;
host_args.at(1) = x13986;
host_args.at(2) = x13987;
host_args.at(3) = x13988;
host_args.at(4) = x13989;
host_args.at(5) = x13990;
host_args.at(6) = x13991;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13992 = args[2][101 * steps + ((cycle - 0) & mask)];
assert(x13992 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13993 = args[2][102 * steps + ((cycle - 0) & mask)];
assert(x13993 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13994 = args[2][103 * steps + ((cycle - 0) & mask)];
assert(x13994 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13995 = args[2][104 * steps + ((cycle - 0) & mask)];
assert(x13995 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x13996 = args[2][105 * steps + ((cycle - 0) & mask)];
assert(x13996 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x13997 = args[2][106 * steps + ((cycle - 0) & mask)];
assert(x13997 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x13998 = args[2][107 * steps + ((cycle - 0) & mask)];
assert(x13998 != Fp::invalid());
host_args.at(0) = x13992;
host_args.at(1) = x13993;
host_args.at(2) = x13994;
host_args.at(3) = x13995;
host_args.at(4) = x13996;
host_args.at(5) = x13997;
host_args.at(6) = x13998;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x13999 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x13999 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14000 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14000 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14001 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14001 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14002 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14002 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14003 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14003 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14004 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14004 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14005 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14005 != Fp::invalid());
host_args.at(0) = x13999;
host_args.at(1) = x14000;
host_args.at(2) = x14001;
host_args.at(3) = x14002;
host_args.at(4) = x14003;
host_args.at(5) = x14004;
host_args.at(6) = x14005;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14006 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14006 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement3/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14007 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14007 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement3/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14008 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14008 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14009 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14009 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14010 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14010 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14011 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14011 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14012 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14012 != Fp::invalid());
host_args.at(0) = x14006;
host_args.at(1) = x14007;
host_args.at(2) = x14008;
host_args.at(3) = x14009;
host_args.at(4) = x14010;
host_args.at(5) = x14011;
host_args.at(6) = x14012;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14013 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x14013 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14014 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x14014 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement4/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14015 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x14015 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14016 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x14016 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14017 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x14017 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14018 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x14018 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14019 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x14019 != Fp::invalid());
host_args.at(0) = x14013;
host_args.at(1) = x14014;
host_args.at(2) = x14015;
host_args.at(3) = x14016;
host_args.at(4) = x14017;
host_args.at(5) = x14018;
host_args.at(6) = x14019;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement5/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14020 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x14020 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement5/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14021 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x14021 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement5/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14022 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x14022 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement5/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14023 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x14023 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement5/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14024 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x14024 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement5/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14025 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x14025 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement5/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14026 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x14026 != Fp::invalid());
host_args.at(0) = x14020;
host_args.at(1) = x14021;
host_args.at(2) = x14022;
host_args.at(3) = x14023;
host_args.at(4) = x14024;
host_args.at(5) = x14025;
host_args.at(6) = x14026;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement6/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14027 = args[2][136 * steps + ((cycle - 0) & mask)];
assert(x14027 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement6/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14028 = args[2][137 * steps + ((cycle - 0) & mask)];
assert(x14028 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement6/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14029 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x14029 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement6/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14030 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x14030 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement6/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14031 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x14031 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement6/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14032 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x14032 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement6/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14033 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x14033 != Fp::invalid());
host_args.at(0) = x14027;
host_args.at(1) = x14028;
host_args.at(2) = x14029;
host_args.at(3) = x14030;
host_args.at(4) = x14031;
host_args.at(5) = x14032;
host_args.at(6) = x14033;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement7/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14034 = args[2][143 * steps + ((cycle - 0) & mask)];
assert(x14034 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement7/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14035 = args[2][144 * steps + ((cycle - 0) & mask)];
assert(x14035 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement7/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14036 = args[2][145 * steps + ((cycle - 0) & mask)];
assert(x14036 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement7/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14037 = args[2][146 * steps + ((cycle - 0) & mask)];
assert(x14037 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement7/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14038 = args[2][147 * steps + ((cycle - 0) & mask)];
assert(x14038 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement7/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14039 = args[2][148 * steps + ((cycle - 0) & mask)];
assert(x14039 != Fp::invalid());
// loc("Top/Mux/3/RamBody/PlonkBody/RamPlonkElement7/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14040 = args[2][149 * steps + ((cycle - 0) & mask)];
assert(x14040 != Fp::invalid());
host_args.at(0) = x14034;
host_args.at(1) = x14035;
host_args.at(2) = x14036;
host_args.at(3) = x14037;
host_args.at(4) = x14038;
host_args.at(5) = x14039;
host_args.at(6) = x14040;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
if (x589 != 0) {
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14041 = args[2][94 * steps + ((cycle - 0) & mask)];
assert(x14041 != Fp::invalid());
if (x14041 != 0) {
{
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14042 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x14042 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14043 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14043 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14044 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14044 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14045 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14045 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14046 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14046 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14047 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14047 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14048 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14048 != Fp::invalid());
host_args.at(0) = x14042;
host_args.at(1) = x14043;
host_args.at(2) = x14044;
host_args.at(3) = x14045;
host_args.at(4) = x14046;
host_args.at(5) = x14047;
host_args.at(6) = x14048;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14049 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14049 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14050 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14050 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14051 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14051 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14052 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14052 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14053 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14053 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14054 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14054 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14055 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14055 != Fp::invalid());
host_args.at(0) = x14049;
host_args.at(1) = x14050;
host_args.at(2) = x14051;
host_args.at(3) = x14052;
host_args.at(4) = x14053;
host_args.at(5) = x14054;
host_args.at(6) = x14055;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14056 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x14056 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14057 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x14057 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14058 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x14058 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14059 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x14059 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14060 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x14060 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14061 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x14061 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14062 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x14062 != Fp::invalid());
host_args.at(0) = x14056;
host_args.at(1) = x14057;
host_args.at(2) = x14058;
host_args.at(3) = x14059;
host_args.at(4) = x14060;
host_args.at(5) = x14061;
host_args.at(6) = x14062;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14063 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x14063 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14064 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x14064 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14065 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x14065 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14066 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x14066 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14067 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x14067 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14068 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x14068 != Fp::invalid());
// loc("Top/Mux/4/Mux/0/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14069 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x14069 != Fp::invalid());
host_args.at(0) = x14063;
host_args.at(1) = x14064;
host_args.at(2) = x14065;
host_args.at(3) = x14066;
host_args.at(4) = x14067;
host_args.at(5) = x14068;
host_args.at(6) = x14069;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14070 = args[2][95 * steps + ((cycle - 0) & mask)];
assert(x14070 != Fp::invalid());
if (x14070 != 0) {
{
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14071 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x14071 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14072 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14072 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14073 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14073 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14074 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14074 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14075 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14075 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14076 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14076 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14077 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14077 != Fp::invalid());
host_args.at(0) = x14071;
host_args.at(1) = x14072;
host_args.at(2) = x14073;
host_args.at(3) = x14074;
host_args.at(4) = x14075;
host_args.at(5) = x14076;
host_args.at(6) = x14077;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14078 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14078 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14079 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14079 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14080 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14080 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14081 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14081 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14082 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14082 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14083 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14083 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14084 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14084 != Fp::invalid());
host_args.at(0) = x14078;
host_args.at(1) = x14079;
host_args.at(2) = x14080;
host_args.at(3) = x14081;
host_args.at(4) = x14082;
host_args.at(5) = x14083;
host_args.at(6) = x14084;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14085 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x14085 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14086 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x14086 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14087 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x14087 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14088 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x14088 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14089 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x14089 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14090 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x14090 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14091 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x14091 != Fp::invalid());
host_args.at(0) = x14085;
host_args.at(1) = x14086;
host_args.at(2) = x14087;
host_args.at(3) = x14088;
host_args.at(4) = x14089;
host_args.at(5) = x14090;
host_args.at(6) = x14091;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14092 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x14092 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14093 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x14093 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14094 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x14094 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14095 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x14095 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14096 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x14096 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14097 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x14097 != Fp::invalid());
// loc("Top/Mux/4/Mux/1/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14098 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x14098 != Fp::invalid());
host_args.at(0) = x14092;
host_args.at(1) = x14093;
host_args.at(2) = x14094;
host_args.at(3) = x14095;
host_args.at(4) = x14096;
host_args.at(5) = x14097;
host_args.at(6) = x14098;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14099 = args[2][96 * steps + ((cycle - 0) & mask)];
assert(x14099 != Fp::invalid());
if (x14099 != 0) {
{
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14100 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x14100 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14101 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14101 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14102 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14102 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14103 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14103 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14104 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14104 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14105 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14105 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14106 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14106 != Fp::invalid());
host_args.at(0) = x14100;
host_args.at(1) = x14101;
host_args.at(2) = x14102;
host_args.at(3) = x14103;
host_args.at(4) = x14104;
host_args.at(5) = x14105;
host_args.at(6) = x14106;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14107 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14107 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14108 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14108 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14109 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14109 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14110 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14110 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14111 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14111 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14112 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14112 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14113 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14113 != Fp::invalid());
host_args.at(0) = x14107;
host_args.at(1) = x14108;
host_args.at(2) = x14109;
host_args.at(3) = x14110;
host_args.at(4) = x14111;
host_args.at(5) = x14112;
host_args.at(6) = x14113;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14114 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x14114 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14115 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x14115 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14116 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x14116 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14117 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x14117 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14118 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x14118 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14119 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x14119 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14120 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x14120 != Fp::invalid());
host_args.at(0) = x14114;
host_args.at(1) = x14115;
host_args.at(2) = x14116;
host_args.at(3) = x14117;
host_args.at(4) = x14118;
host_args.at(5) = x14119;
host_args.at(6) = x14120;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14121 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x14121 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14122 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x14122 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14123 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x14123 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14124 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x14124 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14125 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x14125 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14126 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x14126 != Fp::invalid());
// loc("Top/Mux/4/Mux/2/ComputeCycle/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14127 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x14127 != Fp::invalid());
host_args.at(0) = x14121;
host_args.at(1) = x14122;
host_args.at(2) = x14123;
host_args.at(3) = x14124;
host_args.at(4) = x14125;
host_args.at(5) = x14126;
host_args.at(6) = x14127;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14128 = args[2][97 * steps + ((cycle - 0) & mask)];
assert(x14128 != Fp::invalid());
if (x14128 != 0) {
{
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14129 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x14129 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14130 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14130 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14131 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14131 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14132 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14132 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14133 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14133 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14134 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14134 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14135 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14135 != Fp::invalid());
host_args.at(0) = x14129;
host_args.at(1) = x14130;
host_args.at(2) = x14131;
host_args.at(3) = x14132;
host_args.at(4) = x14133;
host_args.at(5) = x14134;
host_args.at(6) = x14135;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14136 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14136 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14137 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14137 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14138 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14138 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14139 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14139 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14140 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14140 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14141 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14141 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14142 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14142 != Fp::invalid());
host_args.at(0) = x14136;
host_args.at(1) = x14137;
host_args.at(2) = x14138;
host_args.at(3) = x14139;
host_args.at(4) = x14140;
host_args.at(5) = x14141;
host_args.at(6) = x14142;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14143 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x14143 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14144 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x14144 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14145 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x14145 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14146 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x14146 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14147 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x14147 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14148 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x14148 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14149 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x14149 != Fp::invalid());
host_args.at(0) = x14143;
host_args.at(1) = x14144;
host_args.at(2) = x14145;
host_args.at(3) = x14146;
host_args.at(4) = x14147;
host_args.at(5) = x14148;
host_args.at(6) = x14149;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14150 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x14150 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement3/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14151 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x14151 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement3/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14152 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x14152 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14153 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x14153 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14154 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x14154 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14155 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x14155 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14156 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x14156 != Fp::invalid());
host_args.at(0) = x14150;
host_args.at(1) = x14151;
host_args.at(2) = x14152;
host_args.at(3) = x14153;
host_args.at(4) = x14154;
host_args.at(5) = x14155;
host_args.at(6) = x14156;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14157 = args[2][136 * steps + ((cycle - 0) & mask)];
assert(x14157 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14158 = args[2][137 * steps + ((cycle - 0) & mask)];
assert(x14158 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14159 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x14159 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14160 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x14160 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14161 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x14161 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14162 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x14162 != Fp::invalid());
// loc("Top/Mux/4/Mux/3/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14163 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x14163 != Fp::invalid());
host_args.at(0) = x14157;
host_args.at(1) = x14158;
host_args.at(2) = x14159;
host_args.at(3) = x14160;
host_args.at(4) = x14161;
host_args.at(5) = x14162;
host_args.at(6) = x14163;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14164 = args[2][98 * steps + ((cycle - 0) & mask)];
assert(x14164 != Fp::invalid());
if (x14164 != 0) {
{
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14165 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x14165 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14166 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14166 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14167 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14167 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14168 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14168 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14169 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14169 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14170 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14170 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14171 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14171 != Fp::invalid());
host_args.at(0) = x14165;
host_args.at(1) = x14166;
host_args.at(2) = x14167;
host_args.at(3) = x14168;
host_args.at(4) = x14169;
host_args.at(5) = x14170;
host_args.at(6) = x14171;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14172 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14172 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14173 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14173 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14174 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14174 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14175 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14175 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14176 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14176 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14177 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14177 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14178 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14178 != Fp::invalid());
host_args.at(0) = x14172;
host_args.at(1) = x14173;
host_args.at(2) = x14174;
host_args.at(3) = x14175;
host_args.at(4) = x14176;
host_args.at(5) = x14177;
host_args.at(6) = x14178;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14179 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x14179 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14180 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x14180 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14181 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x14181 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14182 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x14182 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14183 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x14183 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14184 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x14184 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14185 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x14185 != Fp::invalid());
host_args.at(0) = x14179;
host_args.at(1) = x14180;
host_args.at(2) = x14181;
host_args.at(3) = x14182;
host_args.at(4) = x14183;
host_args.at(5) = x14184;
host_args.at(6) = x14185;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14186 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x14186 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14187 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x14187 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14188 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x14188 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14189 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x14189 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14190 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x14190 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14191 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x14191 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14192 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x14192 != Fp::invalid());
host_args.at(0) = x14186;
host_args.at(1) = x14187;
host_args.at(2) = x14188;
host_args.at(3) = x14189;
host_args.at(4) = x14190;
host_args.at(5) = x14191;
host_args.at(6) = x14192;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14193 = args[2][136 * steps + ((cycle - 0) & mask)];
assert(x14193 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14194 = args[2][137 * steps + ((cycle - 0) & mask)];
assert(x14194 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement4/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14195 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x14195 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14196 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x14196 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14197 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x14197 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14198 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x14198 != Fp::invalid());
// loc("Top/Mux/4/Mux/4/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14199 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x14199 != Fp::invalid());
host_args.at(0) = x14193;
host_args.at(1) = x14194;
host_args.at(2) = x14195;
host_args.at(3) = x14196;
host_args.at(4) = x14197;
host_args.at(5) = x14198;
host_args.at(6) = x14199;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14200 = args[2][99 * steps + ((cycle - 0) & mask)];
assert(x14200 != Fp::invalid());
if (x14200 != 0) {
{
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14201 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x14201 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14202 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14202 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14203 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14203 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14204 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14204 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14205 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14205 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14206 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14206 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14207 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14207 != Fp::invalid());
host_args.at(0) = x14201;
host_args.at(1) = x14202;
host_args.at(2) = x14203;
host_args.at(3) = x14204;
host_args.at(4) = x14205;
host_args.at(5) = x14206;
host_args.at(6) = x14207;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14208 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14208 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14209 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14209 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14210 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14210 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14211 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14211 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14212 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14212 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14213 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14213 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14214 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14214 != Fp::invalid());
host_args.at(0) = x14208;
host_args.at(1) = x14209;
host_args.at(2) = x14210;
host_args.at(3) = x14211;
host_args.at(4) = x14212;
host_args.at(5) = x14213;
host_args.at(6) = x14214;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14215 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x14215 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14216 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x14216 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14217 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x14217 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14218 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x14218 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14219 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x14219 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14220 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x14220 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14221 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x14221 != Fp::invalid());
host_args.at(0) = x14215;
host_args.at(1) = x14216;
host_args.at(2) = x14217;
host_args.at(3) = x14218;
host_args.at(4) = x14219;
host_args.at(5) = x14220;
host_args.at(6) = x14221;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14222 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x14222 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14223 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x14223 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14224 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x14224 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14225 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x14225 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14226 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x14226 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14227 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x14227 != Fp::invalid());
// loc("Top/Mux/4/Mux/5/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14228 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x14228 != Fp::invalid());
host_args.at(0) = x14222;
host_args.at(1) = x14223;
host_args.at(2) = x14224;
host_args.at(3) = x14225;
host_args.at(4) = x14226;
host_args.at(5) = x14227;
host_args.at(6) = x14228;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14229 = args[2][102 * steps + ((cycle - 0) & mask)];
assert(x14229 != Fp::invalid());
if (x14229 != 0) {
{
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14230 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x14230 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14231 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14231 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14232 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14232 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14233 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14233 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14234 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14234 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14235 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14235 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14236 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14236 != Fp::invalid());
host_args.at(0) = x14230;
host_args.at(1) = x14231;
host_args.at(2) = x14232;
host_args.at(3) = x14233;
host_args.at(4) = x14234;
host_args.at(5) = x14235;
host_args.at(6) = x14236;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14237 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14237 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14238 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14238 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14239 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14239 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14240 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14240 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14241 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14241 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14242 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14242 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14243 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14243 != Fp::invalid());
host_args.at(0) = x14237;
host_args.at(1) = x14238;
host_args.at(2) = x14239;
host_args.at(3) = x14240;
host_args.at(4) = x14241;
host_args.at(5) = x14242;
host_args.at(6) = x14243;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14244 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x14244 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14245 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x14245 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14246 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x14246 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14247 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x14247 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14248 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x14248 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14249 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x14249 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14250 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x14250 != Fp::invalid());
host_args.at(0) = x14244;
host_args.at(1) = x14245;
host_args.at(2) = x14246;
host_args.at(3) = x14247;
host_args.at(4) = x14248;
host_args.at(5) = x14249;
host_args.at(6) = x14250;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14251 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x14251 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14252 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x14252 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14253 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x14253 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14254 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x14254 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14255 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x14255 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14256 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x14256 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14257 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x14257 != Fp::invalid());
host_args.at(0) = x14251;
host_args.at(1) = x14252;
host_args.at(2) = x14253;
host_args.at(3) = x14254;
host_args.at(4) = x14255;
host_args.at(5) = x14256;
host_args.at(6) = x14257;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14258 = args[2][136 * steps + ((cycle - 0) & mask)];
assert(x14258 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14259 = args[2][137 * steps + ((cycle - 0) & mask)];
assert(x14259 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14260 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x14260 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14261 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x14261 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14262 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x14262 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14263 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x14263 != Fp::invalid());
// loc("Top/Mux/4/Mux/8/RamBody/PlonkBody/RamPlonkElement4/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14264 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x14264 != Fp::invalid());
host_args.at(0) = x14258;
host_args.at(1) = x14259;
host_args.at(2) = x14260;
host_args.at(3) = x14261;
host_args.at(4) = x14262;
host_args.at(5) = x14263;
host_args.at(6) = x14264;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14265 = args[2][103 * steps + ((cycle - 0) & mask)];
assert(x14265 != Fp::invalid());
if (x14265 != 0) {
{
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14266 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x14266 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14267 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14267 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14268 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14268 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14269 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14269 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14270 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14270 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14271 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14271 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14272 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14272 != Fp::invalid());
host_args.at(0) = x14266;
host_args.at(1) = x14267;
host_args.at(2) = x14268;
host_args.at(3) = x14269;
host_args.at(4) = x14270;
host_args.at(5) = x14271;
host_args.at(6) = x14272;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14273 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14273 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14274 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14274 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14275 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14275 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14276 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14276 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14277 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14277 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14278 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14278 != Fp::invalid());
// loc("Top/Mux/4/Mux/9/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14279 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14279 != Fp::invalid());
host_args.at(0) = x14273;
host_args.at(1) = x14274;
host_args.at(2) = x14275;
host_args.at(3) = x14276;
host_args.at(4) = x14277;
host_args.at(5) = x14278;
host_args.at(6) = x14279;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14280 = args[2][104 * steps + ((cycle - 0) & mask)];
assert(x14280 != Fp::invalid());
if (x14280 != 0) {
{
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14281 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x14281 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14282 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14282 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14283 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14283 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14284 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14284 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14285 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14285 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14286 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14286 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14287 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14287 != Fp::invalid());
host_args.at(0) = x14281;
host_args.at(1) = x14282;
host_args.at(2) = x14283;
host_args.at(3) = x14284;
host_args.at(4) = x14285;
host_args.at(5) = x14286;
host_args.at(6) = x14287;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14288 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14288 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14289 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14289 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14290 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14290 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14291 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14291 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14292 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14292 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14293 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14293 != Fp::invalid());
// loc("Top/Mux/4/Mux/10/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14294 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14294 != Fp::invalid());
host_args.at(0) = x14288;
host_args.at(1) = x14289;
host_args.at(2) = x14290;
host_args.at(3) = x14291;
host_args.at(4) = x14292;
host_args.at(5) = x14293;
host_args.at(6) = x14294;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14295 = args[2][105 * steps + ((cycle - 0) & mask)];
assert(x14295 != Fp::invalid());
if (x14295 != 0) {
{
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14296 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x14296 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14297 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14297 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14298 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14298 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14299 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14299 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14300 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14300 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14301 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14301 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14302 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14302 != Fp::invalid());
host_args.at(0) = x14296;
host_args.at(1) = x14297;
host_args.at(2) = x14298;
host_args.at(3) = x14299;
host_args.at(4) = x14300;
host_args.at(5) = x14301;
host_args.at(6) = x14302;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14303 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14303 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14304 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14304 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14305 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14305 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14306 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14306 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14307 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14307 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14308 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14308 != Fp::invalid());
// loc("Top/Mux/4/Mux/11/ShaCycle/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14309 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14309 != Fp::invalid());
host_args.at(0) = x14303;
host_args.at(1) = x14304;
host_args.at(2) = x14305;
host_args.at(3) = x14306;
host_args.at(4) = x14307;
host_args.at(5) = x14308;
host_args.at(6) = x14309;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14310 = args[2][106 * steps + ((cycle - 0) & mask)];
assert(x14310 != Fp::invalid());
if (x14310 != 0) {
{
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14311 = args[2][108 * steps + ((cycle - 0) & mask)];
assert(x14311 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14312 = args[2][109 * steps + ((cycle - 0) & mask)];
assert(x14312 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14313 = args[2][110 * steps + ((cycle - 0) & mask)];
assert(x14313 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14314 = args[2][111 * steps + ((cycle - 0) & mask)];
assert(x14314 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14315 = args[2][112 * steps + ((cycle - 0) & mask)];
assert(x14315 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14316 = args[2][113 * steps + ((cycle - 0) & mask)];
assert(x14316 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14317 = args[2][114 * steps + ((cycle - 0) & mask)];
assert(x14317 != Fp::invalid());
host_args.at(0) = x14311;
host_args.at(1) = x14312;
host_args.at(2) = x14313;
host_args.at(3) = x14314;
host_args.at(4) = x14315;
host_args.at(5) = x14316;
host_args.at(6) = x14317;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14318 = args[2][115 * steps + ((cycle - 0) & mask)];
assert(x14318 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14319 = args[2][116 * steps + ((cycle - 0) & mask)];
assert(x14319 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14320 = args[2][117 * steps + ((cycle - 0) & mask)];
assert(x14320 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14321 = args[2][118 * steps + ((cycle - 0) & mask)];
assert(x14321 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14322 = args[2][119 * steps + ((cycle - 0) & mask)];
assert(x14322 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14323 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14323 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14324 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14324 != Fp::invalid());
host_args.at(0) = x14318;
host_args.at(1) = x14319;
host_args.at(2) = x14320;
host_args.at(3) = x14321;
host_args.at(4) = x14322;
host_args.at(5) = x14323;
host_args.at(6) = x14324;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14325 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x14325 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14326 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x14326 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14327 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x14327 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14328 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x14328 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14329 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x14329 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14330 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x14330 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14331 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x14331 != Fp::invalid());
host_args.at(0) = x14325;
host_args.at(1) = x14326;
host_args.at(2) = x14327;
host_args.at(3) = x14328;
host_args.at(4) = x14329;
host_args.at(5) = x14330;
host_args.at(6) = x14331;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14332 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x14332 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14333 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x14333 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14334 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x14334 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14335 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x14335 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14336 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x14336 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14337 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x14337 != Fp::invalid());
// loc("Top/Mux/4/Mux/12/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14338 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x14338 != Fp::invalid());
host_args.at(0) = x14332;
host_args.at(1) = x14333;
host_args.at(2) = x14334;
host_args.at(3) = x14335;
host_args.at(4) = x14336;
host_args.at(5) = x14337;
host_args.at(6) = x14338;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
// loc("cirgen/compiler/edsl/component.cpp":39:15)
auto x14339 = args[2][107 * steps + ((cycle - 0) & mask)];
assert(x14339 != Fp::invalid());
if (x14339 != 0) {
{
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14340 = args[2][120 * steps + ((cycle - 0) & mask)];
assert(x14340 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14341 = args[2][121 * steps + ((cycle - 0) & mask)];
assert(x14341 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14342 = args[2][122 * steps + ((cycle - 0) & mask)];
assert(x14342 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14343 = args[2][123 * steps + ((cycle - 0) & mask)];
assert(x14343 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14344 = args[2][124 * steps + ((cycle - 0) & mask)];
assert(x14344 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14345 = args[2][125 * steps + ((cycle - 0) & mask)];
assert(x14345 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14346 = args[2][126 * steps + ((cycle - 0) & mask)];
assert(x14346 != Fp::invalid());
host_args.at(0) = x14340;
host_args.at(1) = x14341;
host_args.at(2) = x14342;
host_args.at(3) = x14343;
host_args.at(4) = x14344;
host_args.at(5) = x14345;
host_args.at(6) = x14346;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14347 = args[2][127 * steps + ((cycle - 0) & mask)];
assert(x14347 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14348 = args[2][128 * steps + ((cycle - 0) & mask)];
assert(x14348 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14349 = args[2][129 * steps + ((cycle - 0) & mask)];
assert(x14349 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14350 = args[2][130 * steps + ((cycle - 0) & mask)];
assert(x14350 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14351 = args[2][131 * steps + ((cycle - 0) & mask)];
assert(x14351 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14352 = args[2][132 * steps + ((cycle - 0) & mask)];
assert(x14352 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement1/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14353 = args[2][133 * steps + ((cycle - 0) & mask)];
assert(x14353 != Fp::invalid());
host_args.at(0) = x14347;
host_args.at(1) = x14348;
host_args.at(2) = x14349;
host_args.at(3) = x14350;
host_args.at(4) = x14351;
host_args.at(5) = x14352;
host_args.at(6) = x14353;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14354 = args[2][134 * steps + ((cycle - 0) & mask)];
assert(x14354 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14355 = args[2][135 * steps + ((cycle - 0) & mask)];
assert(x14355 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14356 = args[2][136 * steps + ((cycle - 0) & mask)];
assert(x14356 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14357 = args[2][137 * steps + ((cycle - 0) & mask)];
assert(x14357 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14358 = args[2][138 * steps + ((cycle - 0) & mask)];
assert(x14358 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14359 = args[2][139 * steps + ((cycle - 0) & mask)];
assert(x14359 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement2/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14360 = args[2][140 * steps + ((cycle - 0) & mask)];
assert(x14360 != Fp::invalid());
host_args.at(0) = x14354;
host_args.at(1) = x14355;
host_args.at(2) = x14356;
host_args.at(3) = x14357;
host_args.at(4) = x14358;
host_args.at(5) = x14359;
host_args.at(6) = x14360;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14361 = args[2][141 * steps + ((cycle - 0) & mask)];
assert(x14361 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14362 = args[2][142 * steps + ((cycle - 0) & mask)];
assert(x14362 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14363 = args[2][143 * steps + ((cycle - 0) & mask)];
assert(x14363 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg"("./cirgen/compiler/edsl/component.h":85:27))
auto x14364 = args[2][144 * steps + ((cycle - 0) & mask)];
assert(x14364 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg1"("./cirgen/compiler/edsl/component.h":85:27))
auto x14365 = args[2][145 * steps + ((cycle - 0) & mask)];
assert(x14365 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg2"("./cirgen/compiler/edsl/component.h":85:27))
auto x14366 = args[2][146 * steps + ((cycle - 0) & mask)];
assert(x14366 != Fp::invalid());
// loc("Top/Mux/4/Mux/13/RamBody/PlonkBody/RamPlonkElement3/U32Reg/Reg3"("./cirgen/compiler/edsl/component.h":85:27))
auto x14367 = args[2][147 * steps + ((cycle - 0) & mask)];
assert(x14367 != Fp::invalid());
host_args.at(0) = x14361;
host_args.at(1) = x14362;
host_args.at(2) = x14363;
host_args.at(3) = x14364;
host_args.at(4) = x14365;
host_args.at(5) = x14366;
host_args.at(6) = x14367;
host(ctx, "plonkWrite", "ram", host_args.data(), 7, host_outs.data(), 0);
}
}
}
return x13944;
}
} // namespace risc0::circuit::rv32im
// clang-format on