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// Written for Graviola by Joe Birr-Pixton, 2024.
// SPDX-License-Identifier: Apache-2.0 OR ISC OR MIT-0
use core::sync::atomic::{AtomicU8, Ordering};
pub(crate) fn enter_cpu_state() -> u32 {
dit::maybe_enable()
}
pub(crate) fn leave_cpu_state(old: u32) {
dit::maybe_disable(old);
}
/// Effectively memset(ptr, 0, len), but not visible to optimiser
///
/// # Safety:
/// There must be `len` writable bytes at `ptr`; with no alignment
/// requirement.
pub(in crate::low) fn zero_bytes(ptr: *mut u8, len: usize) {
// SAFETY: inline assembly.
unsafe {
core::arch::asm!(
" eor {zero}.16b, {zero}.16b, {zero}.16b",
// by-16 loop
" 2: cmp {len}, #16",
" blt 3f",
" st1 {{{zero}.16b}}, [{ptr}]",
" add {ptr}, {ptr}, #16",
" sub {len}, {len}, #16",
" b 2b",
// by-8 loop
" 3: cmp {len}, #8",
" blt 4f",
" str xzr, [{ptr}], #8",
" sub {len}, {len}, #8",
" b 3b",
// by-1 loop
" 4: subs {len}, {len}, #1",
" blt 5f",
" strb wzr, [{ptr}], #1",
" b 4b",
" 5: ",
ptr = inout(reg) ptr => _,
len = inout(reg) len => _,
// clobbers
zero = out(vreg) _,
)
}
}
/// Effectively memcmp(a, b, len), but guaranteed to visit every element
/// of a and b.
///
/// The return value does not follow memcmp semantics: it is zero if
/// `a == b`, otherwise it is non-zero.
///
/// # Safety
/// The caller must ensure that there are `len` bytes readable at `a` and `b`,
pub(in crate::low) unsafe fn ct_compare_bytes(a: *const u8, b: *const u8, len: usize) -> u8 {
// SAFETY: inline assembly.
unsafe {
let mut acc = 0u8;
core::arch::asm!(
" 2: cmp {len}, 0",
" beq 3f",
" ldrb {tmpa:w}, [{a}]",
" ldrb {tmpb:w}, [{b}]",
" eor {tmpa:w}, {tmpa:w}, {tmpb:w}",
" orr {acc:w}, {acc:w}, {tmpa:w}",
" add {a}, {a}, 1",
" add {b}, {b}, 1",
" sub {len}, {len}, 1",
" b 2b",
" 3: ",
a = inout(reg) a => _,
b = inout(reg) b => _,
len = inout(reg) len => _,
tmpa = inout(reg) 0u8 => _,
tmpb = inout(reg) 0u8 => _,
acc = inout(reg) acc,
);
acc
}
}
/// Proof that the CPU has the crypto extension: AES, PMULL, SHA-1, and
/// SHA-256.
///
/// Cores without it (such as the Raspberry Pi 4's Cortex-A72) lack all of it,
/// so one token covers it.
#[derive(Clone, Copy, Debug)]
pub(crate) struct HaveCryptoExt(());
impl HaveCryptoExt {
/// Detects the extension once, then answers from the cached result.
pub(crate) fn check() -> Option<Self> {
(features() & CRYPTO_EXT != 0).then_some(Self(()))
}
}
/// Token type reflecting the check for the SHA3 CPU feature
///
/// A value of this type is proof that the CPU dynamic feature check has happened.
#[derive(Clone, Copy, Debug)]
pub(crate) struct HaveSha3(());
impl HaveSha3 {
pub(crate) fn check() -> Option<Self> {
(features() & SHA3 != 0).then_some(Self(()))
}
}
/// Returns the first CPU feature we require unconditionally that this CPU lacks.
pub(crate) fn missing_cpu_feature() -> Option<&'static str> {
(features() & NEON == 0).then_some("neon")
}
const NEON: u8 = 1 << 0;
const CRYPTO_EXT: u8 = 1 << 1;
const SHA3: u8 = 1 << 2;
const DIT: u8 = 1 << 3;
const DETECTED: u8 = 1 << 7;
/// The detected features, read once.
fn features() -> u8 {
static FEATURES: AtomicU8 = AtomicU8::new(0);
match FEATURES.load(Ordering::Relaxed) {
0 => {
let features = detect() | DETECTED;
FEATURES.store(features, Ordering::Relaxed);
features
}
features => features,
}
}
fn detect() -> u8 {
use std::arch::is_aarch64_feature_detected as detected;
let neon = test_toggle("neon", detected!("neon"));
let crypto_ext = test_toggle("aes", detected!("aes"))
&& test_toggle("pmull", detected!("pmull"))
// Rust's `sha2` covers the SHA-1 instructions too.
&& test_toggle("sha2", detected!("sha2"));
let sha3 = test_toggle("sha3", detected!("sha3"));
let dit = test_toggle("dit", detected!("dit"));
(if neon { NEON } else { 0 })
| (if crypto_ext { CRYPTO_EXT } else { 0 })
| (if sha3 { SHA3 } else { 0 })
| (if dit { DIT } else { 0 })
}
mod dit {
pub(super) fn maybe_enable() -> u32 {
if super::features() & super::DIT != 0 {
// SAFETY: in this branch, we verified `dit` cpu feature is supported
match unsafe { read() } {
0 => {
// SAFETY: in this branch, we verified `dit` cpu feature is supported
unsafe {
write(1);
};
1
}
_ => 0,
}
} else {
0
}
}
pub(super) fn maybe_disable(we_enabled: u32) {
if we_enabled > 0 {
// SAFETY: `we_enabled > 0` implies `dit` cpu feature was supported earlier
unsafe { write(0) }
}
}
#[target_feature(enable = "dit")]
fn read() -> u32 {
let mut out: u64;
// SAFETY: `mrs _, DIT` is defined only if `dit` cpu feature is supported
unsafe {
core::arch::asm!(
"mrs {r}, DIT",
r = out(reg) out,
);
}
const DIT: u64 = 0x01000000;
(out & DIT == DIT) as u32
}
#[target_feature(enable = "dit")]
fn write(on: u32) {
if on > 0 {
// SAFETY: `msr DIT, _` is defined only if `dit` cpu feature is supported
unsafe { core::arch::asm!("msr DIT, #1") }
} else {
// SAFETY: `msr DIT, _` is defined only if `dit` cpu feature is supported
unsafe { core::arch::asm!("msr DIT, #0") }
}
}
}
#[cfg(not(any(debug_assertions, rind_cpu_disable)))]
fn test_toggle(_id: &str, detected: bool) -> bool {
detected
}
/// Lets a debug build, or a release one with `--cfg rind_cpu_disable`, deny a
/// feature with `RIND_CPU_DISABLE_<id>`, as on x86_64, so a CPU with the
/// crypto extension also tests the code for one without.
#[cfg(any(debug_assertions, rind_cpu_disable))]
fn test_toggle(id: &str, detected: bool) -> bool {
if std::env::var(format!("RIND_CPU_DISABLE_{id}")).is_ok() {
println!("DEBUG: denying cpuid {id:?}");
false
} else {
detected
}
}
/// Read-only prefetch hint.
pub(in crate::low) fn prefetch_ro<T>(ptr: *const T) {
// SAFETY: inline assembly
unsafe {
core::arch::asm!(
"prfm pldl1strm, [{ptr}]",
ptr = in(reg) ptr,
options(readonly, nostack)
);
}
}
#[cfg(test)]
#[cfg_attr(coverage_nightly, coverage(off))]
mod tests {
use super::*;
// CI runs the aarch64 suite on a CPU with the crypto extension, then
// again with it denied, and names which, so neither run silently tests
// only one path.
#[test]
fn detects_the_expected_cpu() {
if let Some(expected) = std::env::var_os("RIND_TEST_ARM_CRYPTO_EXT") {
assert_eq!(HaveCryptoExt::check().is_some(), expected == "1");
}
}
}