rill-graph
Static DAG signal graph — topology and port connections only.
Processing is driven by Port::propagate (not an external engine).
Key components
SignalGraph— immutable DAG container, topology is fixed at build timeGraphBuilder— the only way to build a graph (Source→Processor→Sink), fillsdownstream_input_ptrs,parent,upstream_bufferfor zero-copy routing- Kahn's algorithm — topological sort with cycle detection
Port::propagate— recursive signal propagation:- Copy data to downstream input ports (skipped for zero-copy
upstream_bufferports) - Run port algorithm (
run_action) - Call
pre_process(feedback mix) - Call the downstream node's
process_block(generate/process/consume) snapshot_feedbackon output ports- Recurse through output ports'
downstream_input_ptrs
- Copy data to downstream input ports (skipped for zero-copy
- Zero-copy routing — 1:1 and fan-out connections read directly from upstream
output buffer via
upstream_buffer. Copy only for fan-in and feedback. - Hard-RT safe — no heap allocations, no locks, no syscalls in the
signal path. All
Port::propagatedata structures are pre-allocated at graph construction time (downstream_nodes,downstream_input_ptrs). Communication with the control thread is exclusively through lock-freeMpscQueue<ParameterCommand>. - SIMD-friendly — fixed buffer position in memory for the graph's lifetime
- Port routing — connections and feedback buffers live on ports
- Feedback support —
port.pre_process/port.snapshot_feedback - Port types —
Signal,Control,Clock,Feedback,Param
Top-level processing entry point
No SignalEngine. The source node (e.g. AudioInput from rill-io) creates its
own processing callback. The callback drains the command queue, calls
Source::generate, then Port::propagate to cascade through the DAG.
Dependencies
rill-core—SignalNode,Source/Processor/Sinktraits,ClockTick
Links
- Repository: https://github.com/DigitalRats/rill
- Documentation: https://docs.rs/rill-graph