// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Every peripheral instance of `STM32H743` from `STM32H743.svd`.
use rigless::soc::{Cpu, Endian, Peripheral};
pub mod adc3;
pub mod adc3_common;
pub mod axi;
pub mod bdma;
pub mod can_ccu;
pub mod cec;
pub mod comp1;
pub mod crc;
pub mod crs;
pub mod dac;
pub mod dbgmcu;
pub mod dcmi;
pub mod delay_block_sdmmc1;
pub mod dfsdm;
pub mod dma1;
pub mod dma2d;
pub mod dmamux1;
pub mod dmamux2;
pub mod exti;
pub mod ethernet_dma;
pub mod ethernet_mac;
pub mod ethernet_mtl;
pub mod fdcan1;
pub mod fmc;
pub mod flash;
pub mod gpioa;
pub mod hrtim_common;
pub mod hrtim_master;
pub mod hrtim_tima;
pub mod hrtim_timb;
pub mod hrtim_timc;
pub mod hrtim_timd;
pub mod hrtim_time;
pub mod hsem;
pub mod i2c1;
pub mod iwdg;
pub mod jpeg;
pub mod lptim1;
pub mod lptim3;
pub mod lpuart1;
pub mod ltdc;
pub mod mdios;
pub mod mdma;
pub mod opamp;
pub mod otg1_hs_device;
pub mod otg1_hs_global;
pub mod otg1_hs_host;
pub mod otg1_hs_pwrclk;
pub mod pwr;
pub mod quadspi;
pub mod ramecc1;
pub mod ramecc2;
pub mod ramecc3;
pub mod rcc;
pub mod rng;
pub mod rtc;
pub mod sai4;
pub mod sdmmc1;
pub mod spdifrx;
pub mod spi1;
pub mod swpmi;
pub mod syscfg;
pub mod tim1;
pub mod tim15;
pub mod tim16;
pub mod tim17;
pub mod tim2;
pub mod tim6;
pub mod usart1;
pub mod vrefbuf;
pub mod wwdg;
/// The CPU as the SVD describes it. The SVD names no interrupt count, so this is the highest line it names plus one.
pub static CPU: Cpu = Cpu::new("CM7", true, 150, Endian::Little);
/// `TIM2` at `0x4000_0000`, layout `tim2`, interrupts 28.
pub static TIM2: Peripheral = Peripheral { name: "TIM2", base: 0x4000_0000, size: 0x400, interrupts: &[28], registers: &tim2::REGISTERS };
/// `TIM3` at `0x4000_0400`, layout `tim2`, interrupts 29.
pub static TIM3: Peripheral = Peripheral { name: "TIM3", base: 0x4000_0400, size: 0x400, interrupts: &[29], registers: &tim2::REGISTERS };
/// `TIM4` at `0x4000_0800`, layout `tim2`, interrupts 30.
pub static TIM4: Peripheral = Peripheral { name: "TIM4", base: 0x4000_0800, size: 0x400, interrupts: &[30], registers: &tim2::REGISTERS };
/// `TIM5` at `0x4000_0C00`, layout `tim2`, interrupts 50.
pub static TIM5: Peripheral = Peripheral { name: "TIM5", base: 0x4000_0C00, size: 0x400, interrupts: &[50], registers: &tim2::REGISTERS };
/// `TIM6` at `0x4000_1000`, layout `tim6`, interrupts 54.
pub static TIM6: Peripheral = Peripheral { name: "TIM6", base: 0x4000_1000, size: 0x400, interrupts: &[54], registers: &tim6::REGISTERS };
/// `TIM7` at `0x4000_1400`, layout `tim6`, interrupts 55.
pub static TIM7: Peripheral = Peripheral { name: "TIM7", base: 0x4000_1400, size: 0x400, interrupts: &[55], registers: &tim6::REGISTERS };
/// `TIM12` at `0x4000_1800`, layout `tim2`, interrupts 28.
pub static TIM12: Peripheral = Peripheral { name: "TIM12", base: 0x4000_1800, size: 0x400, interrupts: &[28], registers: &tim2::REGISTERS };
/// `TIM13` at `0x4000_1C00`, layout `tim2`, interrupts 28.
pub static TIM13: Peripheral = Peripheral { name: "TIM13", base: 0x4000_1C00, size: 0x400, interrupts: &[28], registers: &tim2::REGISTERS };
/// `TIM14` at `0x4000_2000`, layout `tim2`, interrupts 28.
pub static TIM14: Peripheral = Peripheral { name: "TIM14", base: 0x4000_2000, size: 0x400, interrupts: &[28], registers: &tim2::REGISTERS };
/// `LPTIM1` at `0x4000_2400`, layout `lptim1`, interrupts 93.
pub static LPTIM1: Peripheral = Peripheral { name: "LPTIM1", base: 0x4000_2400, size: 0x400, interrupts: &[93], registers: &lptim1::REGISTERS };
/// `SPI2` at `0x4000_3800`, layout `spi1`, interrupts 36.
pub static SPI2: Peripheral = Peripheral { name: "SPI2", base: 0x4000_3800, size: 0x400, interrupts: &[36], registers: &spi1::REGISTERS };
/// `SPI3` at `0x4000_3C00`, layout `spi1`, interrupts 51.
pub static SPI3: Peripheral = Peripheral { name: "SPI3", base: 0x4000_3C00, size: 0x400, interrupts: &[51], registers: &spi1::REGISTERS };
/// `SPDIFRX` at `0x4000_4000`, layout `spdifrx`, interrupts 97.
pub static SPDIFRX: Peripheral = Peripheral { name: "SPDIFRX", base: 0x4000_4000, size: 0x400, interrupts: &[97], registers: &spdifrx::REGISTERS };
/// `USART2` at `0x4000_4400`, layout `usart1`, interrupts 38.
pub static USART2: Peripheral = Peripheral { name: "USART2", base: 0x4000_4400, size: 0x400, interrupts: &[38], registers: &usart1::REGISTERS };
/// `USART3` at `0x4000_4800`, layout `usart1`, interrupts 39.
pub static USART3: Peripheral = Peripheral { name: "USART3", base: 0x4000_4800, size: 0x400, interrupts: &[39], registers: &usart1::REGISTERS };
/// `UART4` at `0x4000_4C00`, layout `usart1`, interrupts 52.
pub static UART4: Peripheral = Peripheral { name: "UART4", base: 0x4000_4C00, size: 0x400, interrupts: &[52], registers: &usart1::REGISTERS };
/// `UART5` at `0x4000_5000`, layout `usart1`, interrupts 53.
pub static UART5: Peripheral = Peripheral { name: "UART5", base: 0x4000_5000, size: 0x400, interrupts: &[53], registers: &usart1::REGISTERS };
/// `I2C1` at `0x4000_5400`, layout `i2c1`, interrupts 31, 32.
pub static I2C1: Peripheral = Peripheral { name: "I2C1", base: 0x4000_5400, size: 0x400, interrupts: &[31, 32], registers: &i2c1::REGISTERS };
/// `I2C2` at `0x4000_5800`, layout `i2c1`, interrupts 33, 34.
pub static I2C2: Peripheral = Peripheral { name: "I2C2", base: 0x4000_5800, size: 0x400, interrupts: &[33, 34], registers: &i2c1::REGISTERS };
/// `I2C3` at `0x4000_5C00`, layout `i2c1`, interrupts 72, 73.
pub static I2C3: Peripheral = Peripheral { name: "I2C3", base: 0x4000_5C00, size: 0x400, interrupts: &[72, 73], registers: &i2c1::REGISTERS };
/// `CEC` at `0x4000_6C00`, layout `cec`, interrupts 94.
pub static CEC: Peripheral = Peripheral { name: "CEC", base: 0x4000_6C00, size: 0x400, interrupts: &[94], registers: &cec::REGISTERS };
/// `DAC` at `0x4000_7400`, layout `dac`.
pub static DAC: Peripheral = Peripheral { name: "DAC", base: 0x4000_7400, size: 0x400, interrupts: &[], registers: &dac::REGISTERS };
/// `UART7` at `0x4000_7800`, layout `usart1`, interrupts 82.
pub static UART7: Peripheral = Peripheral { name: "UART7", base: 0x4000_7800, size: 0x400, interrupts: &[82], registers: &usart1::REGISTERS };
/// `UART8` at `0x4000_7C00`, layout `usart1`, interrupts 83.
pub static UART8: Peripheral = Peripheral { name: "UART8", base: 0x4000_7C00, size: 0x400, interrupts: &[83], registers: &usart1::REGISTERS };
/// `CRS` at `0x4000_8400`, layout `crs`, interrupts 144.
pub static CRS: Peripheral = Peripheral { name: "CRS", base: 0x4000_8400, size: 0x400, interrupts: &[144], registers: &crs::REGISTERS };
/// `SWPMI` at `0x4000_8800`, layout `swpmi`, interrupts 115.
pub static SWPMI: Peripheral = Peripheral { name: "SWPMI", base: 0x4000_8800, size: 0x400, interrupts: &[115], registers: &swpmi::REGISTERS };
/// `OPAMP` at `0x4000_9000`, layout `opamp`.
pub static OPAMP: Peripheral = Peripheral { name: "OPAMP", base: 0x4000_9000, size: 0x400, interrupts: &[], registers: &opamp::REGISTERS };
/// `MDIOS` at `0x4000_9400`, layout `mdios`, interrupts 119, 120.
pub static MDIOS: Peripheral = Peripheral { name: "MDIOS", base: 0x4000_9400, size: 0x400, interrupts: &[119, 120], registers: &mdios::REGISTERS };
/// `FDCAN1` at `0x4000_A000`, layout `fdcan1`, interrupts 19, 21, 63.
pub static FDCAN1: Peripheral = Peripheral { name: "FDCAN1", base: 0x4000_A000, size: 0x400, interrupts: &[19, 21, 63], registers: &fdcan1::REGISTERS };
/// `FDCAN2` at `0x4000_A400`, layout `fdcan1`, interrupts 20, 22.
pub static FDCAN2: Peripheral = Peripheral { name: "FDCAN2", base: 0x4000_A400, size: 0x400, interrupts: &[20, 22], registers: &fdcan1::REGISTERS };
/// `CAN_CCU` at `0x4000_A800`, layout `can_ccu`.
pub static CAN_CCU: Peripheral = Peripheral { name: "CAN_CCU", base: 0x4000_A800, size: 0x400, interrupts: &[], registers: &can_ccu::REGISTERS };
/// `TIM1` at `0x4001_0000`, layout `tim1`, interrupts 24, 25, 26, 27.
pub static TIM1: Peripheral = Peripheral { name: "TIM1", base: 0x4001_0000, size: 0x400, interrupts: &[24, 25, 26, 27], registers: &tim1::REGISTERS };
/// `TIM8` at `0x4001_0400`, layout `tim1`, interrupts 43, 44, 45, 46.
pub static TIM8: Peripheral = Peripheral { name: "TIM8", base: 0x4001_0400, size: 0x400, interrupts: &[43, 44, 45, 46], registers: &tim1::REGISTERS };
/// `USART1` at `0x4001_1000`, layout `usart1`, interrupts 37.
pub static USART1: Peripheral = Peripheral { name: "USART1", base: 0x4001_1000, size: 0x400, interrupts: &[37], registers: &usart1::REGISTERS };
/// `USART6` at `0x4001_1400`, layout `usart1`, interrupts 71.
pub static USART6: Peripheral = Peripheral { name: "USART6", base: 0x4001_1400, size: 0x400, interrupts: &[71], registers: &usart1::REGISTERS };
/// `SPI1` at `0x4001_3000`, layout `spi1`, interrupts 35.
pub static SPI1: Peripheral = Peripheral { name: "SPI1", base: 0x4001_3000, size: 0x400, interrupts: &[35], registers: &spi1::REGISTERS };
/// `SPI4` at `0x4001_3400`, layout `spi1`, interrupts 84.
pub static SPI4: Peripheral = Peripheral { name: "SPI4", base: 0x4001_3400, size: 0x400, interrupts: &[84], registers: &spi1::REGISTERS };
/// `TIM15` at `0x4001_4000`, layout `tim15`, interrupts 116.
pub static TIM15: Peripheral = Peripheral { name: "TIM15", base: 0x4001_4000, size: 0x400, interrupts: &[116], registers: &tim15::REGISTERS };
/// `TIM16` at `0x4001_4400`, layout `tim16`, interrupts 117.
pub static TIM16: Peripheral = Peripheral { name: "TIM16", base: 0x4001_4400, size: 0x400, interrupts: &[117], registers: &tim16::REGISTERS };
/// `TIM17` at `0x4001_4800`, layout `tim17`, interrupts 118.
pub static TIM17: Peripheral = Peripheral { name: "TIM17", base: 0x4001_4800, size: 0x400, interrupts: &[118], registers: &tim17::REGISTERS };
/// `SPI5` at `0x4001_5000`, layout `spi1`, interrupts 85.
pub static SPI5: Peripheral = Peripheral { name: "SPI5", base: 0x4001_5000, size: 0x400, interrupts: &[85], registers: &spi1::REGISTERS };
/// `SAI1` at `0x4001_5800`, layout `sai4`, interrupts 87.
pub static SAI1: Peripheral = Peripheral { name: "SAI1", base: 0x4001_5800, size: 0x400, interrupts: &[87], registers: &sai4::REGISTERS };
/// `SAI2` at `0x4001_5C00`, layout `sai4`, interrupts 91.
pub static SAI2: Peripheral = Peripheral { name: "SAI2", base: 0x4001_5C00, size: 0x400, interrupts: &[91], registers: &sai4::REGISTERS };
/// `SAI3` at `0x4001_6000`, layout `sai4`, interrupts 114.
pub static SAI3: Peripheral = Peripheral { name: "SAI3", base: 0x4001_6000, size: 0x400, interrupts: &[114], registers: &sai4::REGISTERS };
/// `DFSDM` at `0x4001_7000`, layout `dfsdm`, interrupts 110, 111, 112, 113.
pub static DFSDM: Peripheral = Peripheral { name: "DFSDM", base: 0x4001_7000, size: 0x400, interrupts: &[110, 111, 112, 113], registers: &dfsdm::REGISTERS };
/// `HRTIM_Master` at `0x4001_7400`, layout `hrtim_master`.
pub static HRTIM_MASTER: Peripheral = Peripheral { name: "HRTIM_Master", base: 0x4001_7400, size: 0x80, interrupts: &[], registers: &hrtim_master::REGISTERS };
/// `HRTIM_TIMA` at `0x4001_7480`, layout `hrtim_tima`, interrupts 103, 109.
pub static HRTIM_TIMA: Peripheral = Peripheral { name: "HRTIM_TIMA", base: 0x4001_7480, size: 0x80, interrupts: &[103, 109], registers: &hrtim_tima::REGISTERS };
/// `HRTIM_TIMB` at `0x4001_7500`, layout `hrtim_timb`, interrupts 104.
pub static HRTIM_TIMB: Peripheral = Peripheral { name: "HRTIM_TIMB", base: 0x4001_7500, size: 0x80, interrupts: &[104], registers: &hrtim_timb::REGISTERS };
/// `HRTIM_TIMC` at `0x4001_7580`, layout `hrtim_timc`, interrupts 105.
pub static HRTIM_TIMC: Peripheral = Peripheral { name: "HRTIM_TIMC", base: 0x4001_7580, size: 0x80, interrupts: &[105], registers: &hrtim_timc::REGISTERS };
/// `HRTIM_TIMD` at `0x4001_7600`, layout `hrtim_timd`, interrupts 106.
pub static HRTIM_TIMD: Peripheral = Peripheral { name: "HRTIM_TIMD", base: 0x4001_7600, size: 0x80, interrupts: &[106], registers: &hrtim_timd::REGISTERS };
/// `HRTIM_TIME` at `0x4001_7680`, layout `hrtim_time`, interrupts 107.
pub static HRTIM_TIME: Peripheral = Peripheral { name: "HRTIM_TIME", base: 0x4001_7680, size: 0x80, interrupts: &[107], registers: &hrtim_time::REGISTERS };
/// `HRTIM_Common` at `0x4001_7780`, layout `hrtim_common`, interrupts 108.
pub static HRTIM_COMMON: Peripheral = Peripheral { name: "HRTIM_Common", base: 0x4001_7780, size: 0x80, interrupts: &[108], registers: &hrtim_common::REGISTERS };
/// `DMA1` at `0x4002_0000`, layout `dma1`, interrupts 11, 12, 47.
pub static DMA1: Peripheral = Peripheral { name: "DMA1", base: 0x4002_0000, size: 0x400, interrupts: &[11, 12, 47], registers: &dma1::REGISTERS };
/// `DMA2` at `0x4002_0400`, layout `dma1`, interrupts 13, 14, 15, 16, 17, 56, 57, 58, 59, 60, 68, 69, 70.
pub static DMA2: Peripheral = Peripheral { name: "DMA2", base: 0x4002_0400, size: 0x400, interrupts: &[13, 14, 15, 16, 17, 56, 57, 58, 59, 60, 68, 69, 70], registers: &dma1::REGISTERS };
/// `DMAMUX1` at `0x4002_0800`, layout `dmamux1`, interrupts 102.
pub static DMAMUX1: Peripheral = Peripheral { name: "DMAMUX1", base: 0x4002_0800, size: 0x400, interrupts: &[102], registers: &dmamux1::REGISTERS };
/// `ADC1` at `0x4002_2000`, layout `adc3`, interrupts 18.
pub static ADC1: Peripheral = Peripheral { name: "ADC1", base: 0x4002_2000, size: 0xD1, interrupts: &[18], registers: &adc3::REGISTERS };
/// `ADC2` at `0x4002_2100`, layout `adc3`, interrupts 127.
pub static ADC2: Peripheral = Peripheral { name: "ADC2", base: 0x4002_2100, size: 0xD1, interrupts: &[127], registers: &adc3::REGISTERS };
/// `ADC12_Common` at `0x4002_2300`, layout `adc3_common`.
pub static ADC12_COMMON: Peripheral = Peripheral { name: "ADC12_Common", base: 0x4002_2300, size: 0x100, interrupts: &[], registers: &adc3_common::REGISTERS };
/// `Ethernet_MAC` at `0x4002_8000`, layout `ethernet_mac`, interrupts 61, 62.
pub static ETHERNET_MAC: Peripheral = Peripheral { name: "Ethernet_MAC", base: 0x4002_8000, size: 0xBDF, interrupts: &[61, 62], registers: ðernet_mac::REGISTERS };
/// `Ethernet_MTL` at `0x4002_8C00`, layout `ethernet_mtl`.
pub static ETHERNET_MTL: Peripheral = Peripheral { name: "Ethernet_MTL", base: 0x4002_8C00, size: 0x200, interrupts: &[], registers: ðernet_mtl::REGISTERS };
/// `Ethernet_DMA` at `0x4002_9000`, layout `ethernet_dma`.
pub static ETHERNET_DMA: Peripheral = Peripheral { name: "Ethernet_DMA", base: 0x4002_9000, size: 0x400, interrupts: &[], registers: ðernet_dma::REGISTERS };
/// `OTG1_HS_GLOBAL` at `0x4004_0000`, layout `otg1_hs_global`, interrupts 74, 75, 76, 77.
pub static OTG1_HS_GLOBAL: Peripheral = Peripheral { name: "OTG1_HS_GLOBAL", base: 0x4004_0000, size: 0x400, interrupts: &[74, 75, 76, 77], registers: &otg1_hs_global::REGISTERS };
/// `OTG1_HS_HOST` at `0x4004_0400`, layout `otg1_hs_host`, interrupts 101.
pub static OTG1_HS_HOST: Peripheral = Peripheral { name: "OTG1_HS_HOST", base: 0x4004_0400, size: 0x400, interrupts: &[101], registers: &otg1_hs_host::REGISTERS };
/// `OTG1_HS_DEVICE` at `0x4004_0800`, layout `otg1_hs_device`.
pub static OTG1_HS_DEVICE: Peripheral = Peripheral { name: "OTG1_HS_DEVICE", base: 0x4004_0800, size: 0x400, interrupts: &[], registers: &otg1_hs_device::REGISTERS };
/// `OTG1_HS_PWRCLK` at `0x4004_0E00`, layout `otg1_hs_pwrclk`.
pub static OTG1_HS_PWRCLK: Peripheral = Peripheral { name: "OTG1_HS_PWRCLK", base: 0x4004_0E00, size: 0x3_F200, interrupts: &[], registers: &otg1_hs_pwrclk::REGISTERS };
/// `OTG2_HS_GLOBAL` at `0x4008_0000`, layout `otg1_hs_global`, interrupts 98, 99, 100.
pub static OTG2_HS_GLOBAL: Peripheral = Peripheral { name: "OTG2_HS_GLOBAL", base: 0x4008_0000, size: 0x400, interrupts: &[98, 99, 100], registers: &otg1_hs_global::REGISTERS };
/// `OTG2_HS_HOST` at `0x4008_0400`, layout `otg1_hs_host`, interrupts 101.
pub static OTG2_HS_HOST: Peripheral = Peripheral { name: "OTG2_HS_HOST", base: 0x4008_0400, size: 0x400, interrupts: &[101], registers: &otg1_hs_host::REGISTERS };
/// `OTG2_HS_DEVICE` at `0x4008_0800`, layout `otg1_hs_device`.
pub static OTG2_HS_DEVICE: Peripheral = Peripheral { name: "OTG2_HS_DEVICE", base: 0x4008_0800, size: 0x400, interrupts: &[], registers: &otg1_hs_device::REGISTERS };
/// `OTG2_HS_PWRCLK` at `0x4008_0E00`, layout `otg1_hs_pwrclk`.
pub static OTG2_HS_PWRCLK: Peripheral = Peripheral { name: "OTG2_HS_PWRCLK", base: 0x4008_0E00, size: 0x3_F200, interrupts: &[], registers: &otg1_hs_pwrclk::REGISTERS };
/// `DCMI` at `0x4802_0000`, layout `dcmi`, interrupts 78.
pub static DCMI: Peripheral = Peripheral { name: "DCMI", base: 0x4802_0000, size: 0x400, interrupts: &[78], registers: &dcmi::REGISTERS };
/// `RNG` at `0x4802_1800`, layout `rng`, interrupts 80.
pub static RNG: Peripheral = Peripheral { name: "RNG", base: 0x4802_1800, size: 0x400, interrupts: &[80], registers: &rng::REGISTERS };
/// `SDMMC2` at `0x4802_2400`, layout `sdmmc1`, interrupts 49, 124.
pub static SDMMC2: Peripheral = Peripheral { name: "SDMMC2", base: 0x4802_2400, size: 0x3FD, interrupts: &[49, 124], registers: &sdmmc1::REGISTERS };
/// `DELAY_Block_SDMMC2` at `0x4802_2800`, layout `delay_block_sdmmc1`, interrupts 149.
pub static DELAY_BLOCK_SDMMC2: Peripheral = Peripheral { name: "DELAY_Block_SDMMC2", base: 0x4802_2800, size: 0x8, interrupts: &[149], registers: &delay_block_sdmmc1::REGISTERS };
/// `RAMECC2` at `0x4802_3000`, layout `ramecc2`.
pub static RAMECC2: Peripheral = Peripheral { name: "RAMECC2", base: 0x4802_3000, size: 0x400, interrupts: &[], registers: &ramecc2::REGISTERS };
/// `LTDC` at `0x5000_1000`, layout `ltdc`, interrupts 88, 89.
pub static LTDC: Peripheral = Peripheral { name: "LTDC", base: 0x5000_1000, size: 0x1000, interrupts: &[88, 89], registers: <dc::REGISTERS };
/// `WWDG` at `0x5000_3000`, layout `wwdg`, interrupts 0, 143.
pub static WWDG: Peripheral = Peripheral { name: "WWDG", base: 0x5000_3000, size: 0x400, interrupts: &[0, 143], registers: &wwdg::REGISTERS };
/// `AXI` at `0x5100_0000`, layout `axi`.
pub static AXI: Peripheral = Peripheral { name: "AXI", base: 0x5100_0000, size: 0x10_0000, interrupts: &[], registers: &axi::REGISTERS };
/// `MDMA` at `0x5200_0000`, layout `mdma`, interrupts 122.
pub static MDMA: Peripheral = Peripheral { name: "MDMA", base: 0x5200_0000, size: 0x1000, interrupts: &[122], registers: &mdma::REGISTERS };
/// `DMA2D` at `0x5200_1000`, layout `dma2d`, interrupts 90.
pub static DMA2D: Peripheral = Peripheral { name: "DMA2D", base: 0x5200_1000, size: 0x400, interrupts: &[90], registers: &dma2d::REGISTERS };
/// `Flash` at `0x5200_2000`, layout `flash`, interrupts 4.
pub static FLASH: Peripheral = Peripheral { name: "Flash", base: 0x5200_2000, size: 0x1000, interrupts: &[4], registers: &flash::REGISTERS };
/// `JPEG` at `0x5200_3000`, layout `jpeg`, interrupts 121.
pub static JPEG: Peripheral = Peripheral { name: "JPEG", base: 0x5200_3000, size: 0x400, interrupts: &[121], registers: &jpeg::REGISTERS };
/// `FMC` at `0x5200_4000`, layout `fmc`, interrupts 48.
pub static FMC: Peripheral = Peripheral { name: "FMC", base: 0x5200_4000, size: 0x400, interrupts: &[48], registers: &fmc::REGISTERS };
/// `QUADSPI` at `0x5200_5000`, layout `quadspi`, interrupts 92.
pub static QUADSPI: Peripheral = Peripheral { name: "QUADSPI", base: 0x5200_5000, size: 0x400, interrupts: &[92], registers: &quadspi::REGISTERS };
/// `DELAY_Block_QUADSPI` at `0x5200_6000`, layout `delay_block_sdmmc1`, interrupts 149.
pub static DELAY_BLOCK_QUADSPI: Peripheral = Peripheral { name: "DELAY_Block_QUADSPI", base: 0x5200_6000, size: 0x8, interrupts: &[149], registers: &delay_block_sdmmc1::REGISTERS };
/// `SDMMC1` at `0x5200_7000`, layout `sdmmc1`, interrupts 49, 124.
pub static SDMMC1: Peripheral = Peripheral { name: "SDMMC1", base: 0x5200_7000, size: 0x3FD, interrupts: &[49, 124], registers: &sdmmc1::REGISTERS };
/// `DELAY_Block_SDMMC1` at `0x5200_8000`, layout `delay_block_sdmmc1`, interrupts 149.
pub static DELAY_BLOCK_SDMMC1: Peripheral = Peripheral { name: "DELAY_Block_SDMMC1", base: 0x5200_8000, size: 0x8, interrupts: &[149], registers: &delay_block_sdmmc1::REGISTERS };
/// `RAMECC1` at `0x5200_9000`, layout `ramecc1`.
pub static RAMECC1: Peripheral = Peripheral { name: "RAMECC1", base: 0x5200_9000, size: 0x400, interrupts: &[], registers: &ramecc1::REGISTERS };
/// `EXTI` at `0x5800_0000`, layout `exti`, interrupts 1, 6, 7, 8, 9, 10, 23, 40, 81.
pub static EXTI: Peripheral = Peripheral { name: "EXTI", base: 0x5800_0000, size: 0x400, interrupts: &[1, 6, 7, 8, 9, 10, 23, 40, 81], registers: &exti::REGISTERS };
/// `SYSCFG` at `0x5800_0400`, layout `syscfg`.
pub static SYSCFG: Peripheral = Peripheral { name: "SYSCFG", base: 0x5800_0400, size: 0x400, interrupts: &[], registers: &syscfg::REGISTERS };
/// `LPUART1` at `0x5800_0C00`, layout `lpuart1`, interrupts 142.
pub static LPUART1: Peripheral = Peripheral { name: "LPUART1", base: 0x5800_0C00, size: 0x400, interrupts: &[142], registers: &lpuart1::REGISTERS };
/// `SPI6` at `0x5800_1400`, layout `spi1`, interrupts 86.
pub static SPI6: Peripheral = Peripheral { name: "SPI6", base: 0x5800_1400, size: 0x400, interrupts: &[86], registers: &spi1::REGISTERS };
/// `I2C4` at `0x5800_1C00`, layout `i2c1`, interrupts 95, 96.
pub static I2C4: Peripheral = Peripheral { name: "I2C4", base: 0x5800_1C00, size: 0x400, interrupts: &[95, 96], registers: &i2c1::REGISTERS };
/// `LPTIM2` at `0x5800_2400`, layout `lptim1`, interrupts 138.
pub static LPTIM2: Peripheral = Peripheral { name: "LPTIM2", base: 0x5800_2400, size: 0x400, interrupts: &[138], registers: &lptim1::REGISTERS };
/// `LPTIM3` at `0x5800_2800`, layout `lptim3`, interrupts 139.
pub static LPTIM3: Peripheral = Peripheral { name: "LPTIM3", base: 0x5800_2800, size: 0x400, interrupts: &[139], registers: &lptim3::REGISTERS };
/// `LPTIM4` at `0x5800_2C00`, layout `lptim3`, interrupts 140.
pub static LPTIM4: Peripheral = Peripheral { name: "LPTIM4", base: 0x5800_2C00, size: 0x400, interrupts: &[140], registers: &lptim3::REGISTERS };
/// `LPTIM5` at `0x5800_3000`, layout `lptim3`, interrupts 141.
pub static LPTIM5: Peripheral = Peripheral { name: "LPTIM5", base: 0x5800_3000, size: 0x400, interrupts: &[141], registers: &lptim3::REGISTERS };
/// `COMP1` at `0x5800_3800`, layout `comp1`, interrupts 137.
pub static COMP1: Peripheral = Peripheral { name: "COMP1", base: 0x5800_3800, size: 0x400, interrupts: &[137], registers: &comp1::REGISTERS };
/// `VREFBUF` at `0x5800_3C00`, layout `vrefbuf`.
pub static VREFBUF: Peripheral = Peripheral { name: "VREFBUF", base: 0x5800_3C00, size: 0x400, interrupts: &[], registers: &vrefbuf::REGISTERS };
/// `RTC` at `0x5800_4000`, layout `rtc`, interrupts 2, 3, 41.
pub static RTC: Peripheral = Peripheral { name: "RTC", base: 0x5800_4000, size: 0x400, interrupts: &[2, 3, 41], registers: &rtc::REGISTERS };
/// `IWDG` at `0x5800_4800`, layout `iwdg`.
pub static IWDG: Peripheral = Peripheral { name: "IWDG", base: 0x5800_4800, size: 0x400, interrupts: &[], registers: &iwdg::REGISTERS };
/// `SAI4` at `0x5800_5400`, layout `sai4`, interrupts 146.
pub static SAI4: Peripheral = Peripheral { name: "SAI4", base: 0x5800_5400, size: 0x400, interrupts: &[146], registers: &sai4::REGISTERS };
/// `GPIOA` at `0x5802_0000`, layout `gpioa`.
pub static GPIOA: Peripheral = Peripheral { name: "GPIOA", base: 0x5802_0000, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `GPIOB` at `0x5802_0400`, layout `gpioa`.
pub static GPIOB: Peripheral = Peripheral { name: "GPIOB", base: 0x5802_0400, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `GPIOC` at `0x5802_0800`, layout `gpioa`.
pub static GPIOC: Peripheral = Peripheral { name: "GPIOC", base: 0x5802_0800, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `GPIOD` at `0x5802_0C00`, layout `gpioa`.
pub static GPIOD: Peripheral = Peripheral { name: "GPIOD", base: 0x5802_0C00, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `GPIOE` at `0x5802_1000`, layout `gpioa`.
pub static GPIOE: Peripheral = Peripheral { name: "GPIOE", base: 0x5802_1000, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `GPIOF` at `0x5802_1400`, layout `gpioa`.
pub static GPIOF: Peripheral = Peripheral { name: "GPIOF", base: 0x5802_1400, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `GPIOG` at `0x5802_1800`, layout `gpioa`.
pub static GPIOG: Peripheral = Peripheral { name: "GPIOG", base: 0x5802_1800, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `GPIOH` at `0x5802_1C00`, layout `gpioa`.
pub static GPIOH: Peripheral = Peripheral { name: "GPIOH", base: 0x5802_1C00, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `GPIOI` at `0x5802_2000`, layout `gpioa`.
pub static GPIOI: Peripheral = Peripheral { name: "GPIOI", base: 0x5802_2000, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `GPIOJ` at `0x5802_2400`, layout `gpioa`.
pub static GPIOJ: Peripheral = Peripheral { name: "GPIOJ", base: 0x5802_2400, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `GPIOK` at `0x5802_2800`, layout `gpioa`.
pub static GPIOK: Peripheral = Peripheral { name: "GPIOK", base: 0x5802_2800, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `RCC` at `0x5802_4400`, layout `rcc`, interrupts 5.
pub static RCC: Peripheral = Peripheral { name: "RCC", base: 0x5802_4400, size: 0x400, interrupts: &[5], registers: &rcc::REGISTERS };
/// `PWR` at `0x5802_4800`, layout `pwr`.
pub static PWR: Peripheral = Peripheral { name: "PWR", base: 0x5802_4800, size: 0x400, interrupts: &[], registers: &pwr::REGISTERS };
/// `CRC` at `0x5802_4C00`, layout `crc`.
pub static CRC: Peripheral = Peripheral { name: "CRC", base: 0x5802_4C00, size: 0x400, interrupts: &[], registers: &crc::REGISTERS };
/// `BDMA` at `0x5802_5400`, layout `bdma`, interrupts 129, 130, 131, 132, 133, 134, 135, 136.
pub static BDMA: Peripheral = Peripheral { name: "BDMA", base: 0x5802_5400, size: 0x400, interrupts: &[129, 130, 131, 132, 133, 134, 135, 136], registers: &bdma::REGISTERS };
/// `DMAMUX2` at `0x5802_5800`, layout `dmamux2`, interrupts 128.
pub static DMAMUX2: Peripheral = Peripheral { name: "DMAMUX2", base: 0x5802_5800, size: 0x400, interrupts: &[128], registers: &dmamux2::REGISTERS };
/// `ADC3` at `0x5802_6000`, layout `adc3`, interrupts 127.
pub static ADC3: Peripheral = Peripheral { name: "ADC3", base: 0x5802_6000, size: 0xD1, interrupts: &[127], registers: &adc3::REGISTERS };
/// `ADC3_Common` at `0x5802_6300`, layout `adc3_common`.
pub static ADC3_COMMON: Peripheral = Peripheral { name: "ADC3_Common", base: 0x5802_6300, size: 0x100, interrupts: &[], registers: &adc3_common::REGISTERS };
/// `HSEM` at `0x5802_6400`, layout `hsem`, interrupts 125.
pub static HSEM: Peripheral = Peripheral { name: "HSEM", base: 0x5802_6400, size: 0x400, interrupts: &[125], registers: &hsem::REGISTERS };
/// `RAMECC3` at `0x5802_7000`, layout `ramecc3`.
pub static RAMECC3: Peripheral = Peripheral { name: "RAMECC3", base: 0x5802_7000, size: 0x400, interrupts: &[], registers: &ramecc3::REGISTERS };
/// `DBGMCU` at `0x5C00_1000`, layout `dbgmcu`.
pub static DBGMCU: Peripheral = Peripheral { name: "DBGMCU", base: 0x5C00_1000, size: 0x400, interrupts: &[], registers: &dbgmcu::REGISTERS };
/// Every instance, by ascending base address.
pub static PERIPHERALS: [Peripheral; 122] = [TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1, I2C2, I2C3, CEC, DAC, UART7, UART8, CRS, SWPMI, OPAMP, MDIOS, FDCAN1, FDCAN2, CAN_CCU, TIM1, TIM8, USART1, USART6, SPI1, SPI4, TIM15, TIM16, TIM17, SPI5, SAI1, SAI2, SAI3, DFSDM, HRTIM_MASTER, HRTIM_TIMA, HRTIM_TIMB, HRTIM_TIMC, HRTIM_TIMD, HRTIM_TIME, HRTIM_COMMON, DMA1, DMA2, DMAMUX1, ADC1, ADC2, ADC12_COMMON, ETHERNET_MAC, ETHERNET_MTL, ETHERNET_DMA, OTG1_HS_GLOBAL, OTG1_HS_HOST, OTG1_HS_DEVICE, OTG1_HS_PWRCLK, OTG2_HS_GLOBAL, OTG2_HS_HOST, OTG2_HS_DEVICE, OTG2_HS_PWRCLK, DCMI, RNG, SDMMC2, DELAY_BLOCK_SDMMC2, RAMECC2, LTDC, WWDG, AXI, MDMA, DMA2D, FLASH, JPEG, FMC, QUADSPI, DELAY_BLOCK_QUADSPI, SDMMC1, DELAY_BLOCK_SDMMC1, RAMECC1, EXTI, SYSCFG, LPUART1, SPI6, I2C4, LPTIM2, LPTIM3, LPTIM4, LPTIM5, COMP1, VREFBUF, RTC, IWDG, SAI4, GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, RCC, PWR, CRC, BDMA, DMAMUX2, ADC3, ADC3_COMMON, HSEM, RAMECC3, DBGMCU];