rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230

// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Every peripheral instance of `STM32F427` from `STM32F427.svd`.

use rigless::soc::{Cpu, Endian, Peripheral};

pub mod adc1;
pub mod can1;
pub mod crc;
pub mod cryp;
pub mod c_adc;
pub mod dac;
pub mod dbg;
pub mod dcmi;
pub mod dma2;
pub mod dma2d;
pub mod exti;
pub mod ethernet_dma;
pub mod ethernet_mac;
pub mod ethernet_mmc;
pub mod ethernet_ptp;
pub mod flash;
pub mod fmc;
pub mod gpioa;
pub mod gpiob;
pub mod gpioi;
pub mod hash;
pub mod i2c3;
pub mod iwdg;
pub mod otg_fs_device;
pub mod otg_fs_global;
pub mod otg_fs_host;
pub mod otg_fs_pwrclk;
pub mod otg_hs_device;
pub mod otg_hs_global;
pub mod otg_hs_host;
pub mod otg_hs_pwrclk;
pub mod pwr;
pub mod rcc;
pub mod rng;
pub mod rtc;
pub mod sai1;
pub mod sdio;
pub mod spi1;
pub mod syscfg;
pub mod tim1;
pub mod tim10;
pub mod tim11;
pub mod tim2;
pub mod tim3;
pub mod tim5;
pub mod tim6;
pub mod tim9;
pub mod uart4;
pub mod usart6;
pub mod wwdg;

/// The CPU as the SVD describes it. The SVD names no interrupt count, so this is the highest line it names plus one.
pub static CPU: Cpu = Cpu::new("CM4", true, 87, Endian::Little);

/// `TIM2` at `0x4000_0000`, layout `tim2`, interrupts 28.
pub static TIM2: Peripheral = Peripheral { name: "TIM2", base: 0x4000_0000, size: 0x400, interrupts: &[28], registers: &tim2::REGISTERS };
/// `TIM3` at `0x4000_0400`, layout `tim3`, interrupts 29.
pub static TIM3: Peripheral = Peripheral { name: "TIM3", base: 0x4000_0400, size: 0x400, interrupts: &[29], registers: &tim3::REGISTERS };
/// `TIM4` at `0x4000_0800`, layout `tim3`, interrupts 30.
pub static TIM4: Peripheral = Peripheral { name: "TIM4", base: 0x4000_0800, size: 0x400, interrupts: &[30], registers: &tim3::REGISTERS };
/// `TIM5` at `0x4000_0C00`, layout `tim5`, interrupts 50.
pub static TIM5: Peripheral = Peripheral { name: "TIM5", base: 0x4000_0C00, size: 0x400, interrupts: &[50], registers: &tim5::REGISTERS };
/// `TIM6` at `0x4000_1000`, layout `tim6`.
pub static TIM6: Peripheral = Peripheral { name: "TIM6", base: 0x4000_1000, size: 0x400, interrupts: &[], registers: &tim6::REGISTERS };
/// `TIM7` at `0x4000_1400`, layout `tim6`, interrupts 55.
pub static TIM7: Peripheral = Peripheral { name: "TIM7", base: 0x4000_1400, size: 0x400, interrupts: &[55], registers: &tim6::REGISTERS };
/// `TIM12` at `0x4000_1800`, layout `tim9`.
pub static TIM12: Peripheral = Peripheral { name: "TIM12", base: 0x4000_1800, size: 0x400, interrupts: &[], registers: &tim9::REGISTERS };
/// `TIM13` at `0x4000_1C00`, layout `tim10`, interrupts 44.
pub static TIM13: Peripheral = Peripheral { name: "TIM13", base: 0x4000_1C00, size: 0x400, interrupts: &[44], registers: &tim10::REGISTERS };
/// `TIM14` at `0x4000_2000`, layout `tim10`, interrupts 45.
pub static TIM14: Peripheral = Peripheral { name: "TIM14", base: 0x4000_2000, size: 0x400, interrupts: &[45], registers: &tim10::REGISTERS };
/// `RTC` at `0x4000_2800`, layout `rtc`, interrupts 3, 41.
pub static RTC: Peripheral = Peripheral { name: "RTC", base: 0x4000_2800, size: 0x400, interrupts: &[3, 41], registers: &rtc::REGISTERS };
/// `WWDG` at `0x4000_2C00`, layout `wwdg`, interrupts 0.
pub static WWDG: Peripheral = Peripheral { name: "WWDG", base: 0x4000_2C00, size: 0x400, interrupts: &[0], registers: &wwdg::REGISTERS };
/// `IWDG` at `0x4000_3000`, layout `iwdg`.
pub static IWDG: Peripheral = Peripheral { name: "IWDG", base: 0x4000_3000, size: 0x400, interrupts: &[], registers: &iwdg::REGISTERS };
/// `I2S2ext` at `0x4000_3400`, layout `spi1`, interrupts 35.
pub static I2S2EXT: Peripheral = Peripheral { name: "I2S2ext", base: 0x4000_3400, size: 0x400, interrupts: &[35], registers: &spi1::REGISTERS };
/// `SPI2` at `0x4000_3800`, layout `spi1`, interrupts 36.
pub static SPI2: Peripheral = Peripheral { name: "SPI2", base: 0x4000_3800, size: 0x400, interrupts: &[36], registers: &spi1::REGISTERS };
/// `SPI3` at `0x4000_3C00`, layout `spi1`, interrupts 51.
pub static SPI3: Peripheral = Peripheral { name: "SPI3", base: 0x4000_3C00, size: 0x400, interrupts: &[51], registers: &spi1::REGISTERS };
/// `I2S3ext` at `0x4000_4000`, layout `spi1`, interrupts 35.
pub static I2S3EXT: Peripheral = Peripheral { name: "I2S3ext", base: 0x4000_4000, size: 0x400, interrupts: &[35], registers: &spi1::REGISTERS };
/// `USART2` at `0x4000_4400`, layout `usart6`, interrupts 38.
pub static USART2: Peripheral = Peripheral { name: "USART2", base: 0x4000_4400, size: 0x400, interrupts: &[38], registers: &usart6::REGISTERS };
/// `USART3` at `0x4000_4800`, layout `usart6`, interrupts 39.
pub static USART3: Peripheral = Peripheral { name: "USART3", base: 0x4000_4800, size: 0x400, interrupts: &[39], registers: &usart6::REGISTERS };
/// `UART4` at `0x4000_4C00`, layout `uart4`, interrupts 52.
pub static UART4: Peripheral = Peripheral { name: "UART4", base: 0x4000_4C00, size: 0x400, interrupts: &[52], registers: &uart4::REGISTERS };
/// `UART5` at `0x4000_5000`, layout `uart4`, interrupts 53.
pub static UART5: Peripheral = Peripheral { name: "UART5", base: 0x4000_5000, size: 0x400, interrupts: &[53], registers: &uart4::REGISTERS };
/// `I2C1` at `0x4000_5400`, layout `i2c3`, interrupts 31, 32.
pub static I2C1: Peripheral = Peripheral { name: "I2C1", base: 0x4000_5400, size: 0x400, interrupts: &[31, 32], registers: &i2c3::REGISTERS };
/// `I2C2` at `0x4000_5800`, layout `i2c3`, interrupts 33, 34.
pub static I2C2: Peripheral = Peripheral { name: "I2C2", base: 0x4000_5800, size: 0x400, interrupts: &[33, 34], registers: &i2c3::REGISTERS };
/// `I2C3` at `0x4000_5C00`, layout `i2c3`, interrupts 72, 73.
pub static I2C3: Peripheral = Peripheral { name: "I2C3", base: 0x4000_5C00, size: 0x400, interrupts: &[72, 73], registers: &i2c3::REGISTERS };
/// `CAN1` at `0x4000_6400`, layout `can1`, interrupts 19, 20, 21, 22.
pub static CAN1: Peripheral = Peripheral { name: "CAN1", base: 0x4000_6400, size: 0x400, interrupts: &[19, 20, 21, 22], registers: &can1::REGISTERS };
/// `CAN2` at `0x4000_6800`, layout `can1`, interrupts 63, 64, 65, 66.
pub static CAN2: Peripheral = Peripheral { name: "CAN2", base: 0x4000_6800, size: 0x400, interrupts: &[63, 64, 65, 66], registers: &can1::REGISTERS };
/// `PWR` at `0x4000_7000`, layout `pwr`, interrupts 1.
pub static PWR: Peripheral = Peripheral { name: "PWR", base: 0x4000_7000, size: 0x400, interrupts: &[1], registers: &pwr::REGISTERS };
/// `DAC` at `0x4000_7400`, layout `dac`, interrupts 54.
pub static DAC: Peripheral = Peripheral { name: "DAC", base: 0x4000_7400, size: 0x400, interrupts: &[54], registers: &dac::REGISTERS };
/// `UART7` at `0x4000_7800`, layout `usart6`, interrupts 82.
pub static UART7: Peripheral = Peripheral { name: "UART7", base: 0x4000_7800, size: 0x400, interrupts: &[82], registers: &usart6::REGISTERS };
/// `UART8` at `0x4000_7C00`, layout `usart6`, interrupts 83.
pub static UART8: Peripheral = Peripheral { name: "UART8", base: 0x4000_7C00, size: 0x400, interrupts: &[83], registers: &usart6::REGISTERS };
/// `TIM1` at `0x4001_0000`, layout `tim1`, interrupts 24, 25, 26, 27.
pub static TIM1: Peripheral = Peripheral { name: "TIM1", base: 0x4001_0000, size: 0x400, interrupts: &[24, 25, 26, 27], registers: &tim1::REGISTERS };
/// `TIM8` at `0x4001_0400`, layout `tim1`, interrupts 43, 46.
pub static TIM8: Peripheral = Peripheral { name: "TIM8", base: 0x4001_0400, size: 0x400, interrupts: &[43, 46], registers: &tim1::REGISTERS };
/// `USART1` at `0x4001_1000`, layout `usart6`, interrupts 37.
pub static USART1: Peripheral = Peripheral { name: "USART1", base: 0x4001_1000, size: 0x400, interrupts: &[37], registers: &usart6::REGISTERS };
/// `USART6` at `0x4001_1400`, layout `usart6`, interrupts 71.
pub static USART6: Peripheral = Peripheral { name: "USART6", base: 0x4001_1400, size: 0x400, interrupts: &[71], registers: &usart6::REGISTERS };
/// `ADC1` at `0x4001_2000`, layout `adc1`.
pub static ADC1: Peripheral = Peripheral { name: "ADC1", base: 0x4001_2000, size: 0x51, interrupts: &[], registers: &adc1::REGISTERS };
/// `ADC2` at `0x4001_2100`, layout `adc1`.
pub static ADC2: Peripheral = Peripheral { name: "ADC2", base: 0x4001_2100, size: 0x51, interrupts: &[], registers: &adc1::REGISTERS };
/// `ADC3` at `0x4001_2200`, layout `adc1`, interrupts 18.
pub static ADC3: Peripheral = Peripheral { name: "ADC3", base: 0x4001_2200, size: 0x51, interrupts: &[18], registers: &adc1::REGISTERS };
/// `C_ADC` at `0x4001_2300`, layout `c_adc`.
pub static C_ADC: Peripheral = Peripheral { name: "C_ADC", base: 0x4001_2300, size: 0xD, interrupts: &[], registers: &c_adc::REGISTERS };
/// `SDIO` at `0x4001_2C00`, layout `sdio`, interrupts 49.
pub static SDIO: Peripheral = Peripheral { name: "SDIO", base: 0x4001_2C00, size: 0x400, interrupts: &[49], registers: &sdio::REGISTERS };
/// `SPI1` at `0x4001_3000`, layout `spi1`, interrupts 35.
pub static SPI1: Peripheral = Peripheral { name: "SPI1", base: 0x4001_3000, size: 0x400, interrupts: &[35], registers: &spi1::REGISTERS };
/// `SPI4` at `0x4001_3400`, layout `spi1`, interrupts 84.
pub static SPI4: Peripheral = Peripheral { name: "SPI4", base: 0x4001_3400, size: 0x400, interrupts: &[84], registers: &spi1::REGISTERS };
/// `SYSCFG` at `0x4001_3800`, layout `syscfg`.
pub static SYSCFG: Peripheral = Peripheral { name: "SYSCFG", base: 0x4001_3800, size: 0x400, interrupts: &[], registers: &syscfg::REGISTERS };
/// `EXTI` at `0x4001_3C00`, layout `exti`, interrupts 2, 6, 7, 8, 9, 10, 23, 40.
pub static EXTI: Peripheral = Peripheral { name: "EXTI", base: 0x4001_3C00, size: 0x400, interrupts: &[2, 6, 7, 8, 9, 10, 23, 40], registers: &exti::REGISTERS };
/// `TIM9` at `0x4001_4000`, layout `tim9`.
pub static TIM9: Peripheral = Peripheral { name: "TIM9", base: 0x4001_4000, size: 0x400, interrupts: &[], registers: &tim9::REGISTERS };
/// `TIM10` at `0x4001_4400`, layout `tim10`.
pub static TIM10: Peripheral = Peripheral { name: "TIM10", base: 0x4001_4400, size: 0x400, interrupts: &[], registers: &tim10::REGISTERS };
/// `TIM11` at `0x4001_4800`, layout `tim11`.
pub static TIM11: Peripheral = Peripheral { name: "TIM11", base: 0x4001_4800, size: 0x400, interrupts: &[], registers: &tim11::REGISTERS };
/// `SPI5` at `0x4001_5000`, layout `spi1`, interrupts 85.
pub static SPI5: Peripheral = Peripheral { name: "SPI5", base: 0x4001_5000, size: 0x400, interrupts: &[85], registers: &spi1::REGISTERS };
/// `SPI6` at `0x4001_5400`, layout `spi1`, interrupts 86.
pub static SPI6: Peripheral = Peripheral { name: "SPI6", base: 0x4001_5400, size: 0x400, interrupts: &[86], registers: &spi1::REGISTERS };
/// `SAI1` at `0x4001_5800`, layout `sai1`.
pub static SAI1: Peripheral = Peripheral { name: "SAI1", base: 0x4001_5800, size: 0x400, interrupts: &[], registers: &sai1::REGISTERS };
/// `GPIOA` at `0x4002_0000`, layout `gpioa`.
pub static GPIOA: Peripheral = Peripheral { name: "GPIOA", base: 0x4002_0000, size: 0x400, interrupts: &[], registers: &gpioa::REGISTERS };
/// `GPIOB` at `0x4002_0400`, layout `gpiob`.
pub static GPIOB: Peripheral = Peripheral { name: "GPIOB", base: 0x4002_0400, size: 0x400, interrupts: &[], registers: &gpiob::REGISTERS };
/// `GPIOC` at `0x4002_0800`, layout `gpioi`.
pub static GPIOC: Peripheral = Peripheral { name: "GPIOC", base: 0x4002_0800, size: 0x400, interrupts: &[], registers: &gpioi::REGISTERS };
/// `GPIOD` at `0x4002_0C00`, layout `gpioi`.
pub static GPIOD: Peripheral = Peripheral { name: "GPIOD", base: 0x4002_0C00, size: 0x400, interrupts: &[], registers: &gpioi::REGISTERS };
/// `GPIOE` at `0x4002_1000`, layout `gpioi`.
pub static GPIOE: Peripheral = Peripheral { name: "GPIOE", base: 0x4002_1000, size: 0x400, interrupts: &[], registers: &gpioi::REGISTERS };
/// `GPIOF` at `0x4002_1400`, layout `gpioi`.
pub static GPIOF: Peripheral = Peripheral { name: "GPIOF", base: 0x4002_1400, size: 0x400, interrupts: &[], registers: &gpioi::REGISTERS };
/// `GPIOG` at `0x4002_1800`, layout `gpioi`.
pub static GPIOG: Peripheral = Peripheral { name: "GPIOG", base: 0x4002_1800, size: 0x400, interrupts: &[], registers: &gpioi::REGISTERS };
/// `GPIOH` at `0x4002_1C00`, layout `gpioi`.
pub static GPIOH: Peripheral = Peripheral { name: "GPIOH", base: 0x4002_1C00, size: 0x400, interrupts: &[], registers: &gpioi::REGISTERS };
/// `GPIOI` at `0x4002_2000`, layout `gpioi`.
pub static GPIOI: Peripheral = Peripheral { name: "GPIOI", base: 0x4002_2000, size: 0x400, interrupts: &[], registers: &gpioi::REGISTERS };
/// `GPIOJ` at `0x4002_2400`, layout `gpioi`.
pub static GPIOJ: Peripheral = Peripheral { name: "GPIOJ", base: 0x4002_2400, size: 0x400, interrupts: &[], registers: &gpioi::REGISTERS };
/// `GPIOK` at `0x4002_2800`, layout `gpioi`.
pub static GPIOK: Peripheral = Peripheral { name: "GPIOK", base: 0x4002_2800, size: 0x400, interrupts: &[], registers: &gpioi::REGISTERS };
/// `CRC` at `0x4002_3000`, layout `crc`.
pub static CRC: Peripheral = Peripheral { name: "CRC", base: 0x4002_3000, size: 0x400, interrupts: &[], registers: &crc::REGISTERS };
/// `RCC` at `0x4002_3800`, layout `rcc`, interrupts 5.
pub static RCC: Peripheral = Peripheral { name: "RCC", base: 0x4002_3800, size: 0x400, interrupts: &[5], registers: &rcc::REGISTERS };
/// `FLASH` at `0x4002_3C00`, layout `flash`, interrupts 4.
pub static FLASH: Peripheral = Peripheral { name: "FLASH", base: 0x4002_3C00, size: 0x400, interrupts: &[4], registers: &flash::REGISTERS };
/// `DMA1` at `0x4002_6000`, layout `dma2`, interrupts 11, 12, 13, 14, 15, 16, 17, 47.
pub static DMA1: Peripheral = Peripheral { name: "DMA1", base: 0x4002_6000, size: 0x400, interrupts: &[11, 12, 13, 14, 15, 16, 17, 47], registers: &dma2::REGISTERS };
/// `DMA2` at `0x4002_6400`, layout `dma2`, interrupts 56, 57, 58, 59, 60, 68, 69, 70.
pub static DMA2: Peripheral = Peripheral { name: "DMA2", base: 0x4002_6400, size: 0x400, interrupts: &[56, 57, 58, 59, 60, 68, 69, 70], registers: &dma2::REGISTERS };
/// `Ethernet_MAC` at `0x4002_8000`, layout `ethernet_mac`, interrupts 61, 62.
pub static ETHERNET_MAC: Peripheral = Peripheral { name: "Ethernet_MAC", base: 0x4002_8000, size: 0x61, interrupts: &[61, 62], registers: &ethernet_mac::REGISTERS };
/// `Ethernet_MMC` at `0x4002_8100`, layout `ethernet_mmc`.
pub static ETHERNET_MMC: Peripheral = Peripheral { name: "Ethernet_MMC", base: 0x4002_8100, size: 0x400, interrupts: &[], registers: &ethernet_mmc::REGISTERS };
/// `Ethernet_PTP` at `0x4002_8700`, layout `ethernet_ptp`.
pub static ETHERNET_PTP: Peripheral = Peripheral { name: "Ethernet_PTP", base: 0x4002_8700, size: 0x400, interrupts: &[], registers: &ethernet_ptp::REGISTERS };
/// `Ethernet_DMA` at `0x4002_9000`, layout `ethernet_dma`.
pub static ETHERNET_DMA: Peripheral = Peripheral { name: "Ethernet_DMA", base: 0x4002_9000, size: 0x400, interrupts: &[], registers: &ethernet_dma::REGISTERS };
/// `DMA2D` at `0x4002_B000`, layout `dma2d`.
pub static DMA2D: Peripheral = Peripheral { name: "DMA2D", base: 0x4002_B000, size: 0xC00, interrupts: &[], registers: &dma2d::REGISTERS };
/// `OTG_HS_GLOBAL` at `0x4004_0000`, layout `otg_hs_global`, interrupts 74, 75, 76, 77.
pub static OTG_HS_GLOBAL: Peripheral = Peripheral { name: "OTG_HS_GLOBAL", base: 0x4004_0000, size: 0x400, interrupts: &[74, 75, 76, 77], registers: &otg_hs_global::REGISTERS };
/// `OTG_HS_HOST` at `0x4004_0400`, layout `otg_hs_host`.
pub static OTG_HS_HOST: Peripheral = Peripheral { name: "OTG_HS_HOST", base: 0x4004_0400, size: 0x400, interrupts: &[], registers: &otg_hs_host::REGISTERS };
/// `OTG_HS_DEVICE` at `0x4004_0800`, layout `otg_hs_device`.
pub static OTG_HS_DEVICE: Peripheral = Peripheral { name: "OTG_HS_DEVICE", base: 0x4004_0800, size: 0x400, interrupts: &[], registers: &otg_hs_device::REGISTERS };
/// `OTG_HS_PWRCLK` at `0x4004_0E00`, layout `otg_hs_pwrclk`.
pub static OTG_HS_PWRCLK: Peripheral = Peripheral { name: "OTG_HS_PWRCLK", base: 0x4004_0E00, size: 0x3_F200, interrupts: &[], registers: &otg_hs_pwrclk::REGISTERS };
/// `OTG_FS_GLOBAL` at `0x5000_0000`, layout `otg_fs_global`, interrupts 42, 67.
pub static OTG_FS_GLOBAL: Peripheral = Peripheral { name: "OTG_FS_GLOBAL", base: 0x5000_0000, size: 0x400, interrupts: &[42, 67], registers: &otg_fs_global::REGISTERS };
/// `OTG_FS_HOST` at `0x5000_0400`, layout `otg_fs_host`.
pub static OTG_FS_HOST: Peripheral = Peripheral { name: "OTG_FS_HOST", base: 0x5000_0400, size: 0x400, interrupts: &[], registers: &otg_fs_host::REGISTERS };
/// `OTG_FS_DEVICE` at `0x5000_0800`, layout `otg_fs_device`.
pub static OTG_FS_DEVICE: Peripheral = Peripheral { name: "OTG_FS_DEVICE", base: 0x5000_0800, size: 0x400, interrupts: &[], registers: &otg_fs_device::REGISTERS };
/// `OTG_FS_PWRCLK` at `0x5000_0E00`, layout `otg_fs_pwrclk`.
pub static OTG_FS_PWRCLK: Peripheral = Peripheral { name: "OTG_FS_PWRCLK", base: 0x5000_0E00, size: 0x400, interrupts: &[], registers: &otg_fs_pwrclk::REGISTERS };
/// `DCMI` at `0x5005_0000`, layout `dcmi`, interrupts 78.
pub static DCMI: Peripheral = Peripheral { name: "DCMI", base: 0x5005_0000, size: 0x400, interrupts: &[78], registers: &dcmi::REGISTERS };
/// `CRYP` at `0x5006_0000`, layout `cryp`, interrupts 79.
pub static CRYP: Peripheral = Peripheral { name: "CRYP", base: 0x5006_0000, size: 0x400, interrupts: &[79], registers: &cryp::REGISTERS };
/// `HASH` at `0x5006_0400`, layout `hash`, interrupts 80.
pub static HASH: Peripheral = Peripheral { name: "HASH", base: 0x5006_0400, size: 0x400, interrupts: &[80], registers: &hash::REGISTERS };
/// `RNG` at `0x5006_0800`, layout `rng`, interrupts 81.
pub static RNG: Peripheral = Peripheral { name: "RNG", base: 0x5006_0800, size: 0x400, interrupts: &[81], registers: &rng::REGISTERS };
/// `FMC` at `0xA000_0000`, layout `fmc`, interrupts 48.
pub static FMC: Peripheral = Peripheral { name: "FMC", base: 0xA000_0000, size: 0x400, interrupts: &[48], registers: &fmc::REGISTERS };
/// `DBG` at `0xE004_2000`, layout `dbg`.
pub static DBG: Peripheral = Peripheral { name: "DBG", base: 0xE004_2000, size: 0x400, interrupts: &[], registers: &dbg::REGISTERS };

/// Every instance, by ascending base address.
pub static PERIPHERALS: [Peripheral; 83] = [TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14, RTC, WWDG, IWDG, I2S2EXT, SPI2, SPI3, I2S3EXT, USART2, USART3, UART4, UART5, I2C1, I2C2, I2C3, CAN1, CAN2, PWR, DAC, UART7, UART8, TIM1, TIM8, USART1, USART6, ADC1, ADC2, ADC3, C_ADC, SDIO, SPI1, SPI4, SYSCFG, EXTI, TIM9, TIM10, TIM11, SPI5, SPI6, SAI1, GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, CRC, RCC, FLASH, DMA1, DMA2, ETHERNET_MAC, ETHERNET_MMC, ETHERNET_PTP, ETHERNET_DMA, DMA2D, OTG_HS_GLOBAL, OTG_HS_HOST, OTG_HS_DEVICE, OTG_HS_PWRCLK, OTG_FS_GLOBAL, OTG_FS_HOST, OTG_FS_DEVICE, OTG_FS_PWRCLK, DCMI, CRYP, HASH, RNG, FMC, DBG];