rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `CRS` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR` at offset `0x0`, resets to `0x0000_2000`, read-write.
    Cr = 0,
    /// `CFGR` at offset `0x4`, resets to `0x2022_BB7F`, read-write.
    Cfgr = 1,
    /// `ISR` at offset `0x8`, resets to `0x0000_0000`, read-only.
    Isr = 2,
    /// `ICR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Icr = 3,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 4] = [Self::Cr, Self::Cfgr, Self::Isr, Self::Icr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `SYNCOKIE`, bit 0.
    pub const SYNCOKIE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `SYNCWARNIE`, bit 1.
    pub const SYNCWARNIE: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `ERRIE`, bit 2.
    pub const ERRIE: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `ESYNCIE`, bit 3.
    pub const ESYNCIE: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `CEN`, bit 5.
    pub const CEN: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `AUTOTRIMEN`, bit 6.
    pub const AUTOTRIMEN: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `SWSYNC`, bit 7, read-only.
    pub const SWSYNC: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `TRIM`, bits 8..=13.
    pub const TRIM: &FieldSpec = &super::REGISTERS[0].fields[7];
}

/// The fields of `CFGR`.
pub mod cfgr {
    use super::FieldSpec;
    /// `RELOAD`, bits 0..=15.
    pub const RELOAD: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `FELIM`, bits 16..=23.
    pub const FELIM: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `SYNCDIV`, bits 24..=26.
    pub const SYNCDIV: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `SYNCSRC`, bits 28..=29.
    pub const SYNCSRC: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `SYNCPOL`, bit 31.
    pub const SYNCPOL: &FieldSpec = &super::REGISTERS[1].fields[4];
}

/// The fields of `ISR`.
pub mod isr {
    use super::FieldSpec;
    /// `SYNCOKF`, bit 0.
    pub const SYNCOKF: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `SYNCWARNF`, bit 1.
    pub const SYNCWARNF: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `ERRF`, bit 2.
    pub const ERRF: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `ESYNCF`, bit 3.
    pub const ESYNCF: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `SYNCERR`, bit 8.
    pub const SYNCERR: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `SYNCMISS`, bit 9.
    pub const SYNCMISS: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `TRIMOVF`, bit 10.
    pub const TRIMOVF: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `FEDIR`, bit 15.
    pub const FEDIR: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `FECAP`, bits 16..=31.
    pub const FECAP: &FieldSpec = &super::REGISTERS[2].fields[8];
}

/// The fields of `ICR`.
pub mod icr {
    use super::FieldSpec;
    /// `SYNCOKC`, bit 0.
    pub const SYNCOKC: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `SYNCWARNC`, bit 1.
    pub const SYNCWARNC: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `ERRC`, bit 2.
    pub const ERRC: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `ESYNCC`, bit 3.
    pub const ESYNCC: &FieldSpec = &super::REGISTERS[3].fields[3];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 4] = [
    RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_2000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SYNCOKIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCWARNIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERRIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ESYNCIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AUTOTRIMEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWSYNC", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIM", bit: 8, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFGR", offset: 0x4, width: Width::W32, reset: 0x2022_BB7F, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RELOAD", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FELIM", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCDIV", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCSRC", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCPOL", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ISR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SYNCOKF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCWARNF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERRF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ESYNCF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCERR", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCMISS", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIMOVF", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEDIR", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FECAP", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ICR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SYNCOKC", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCWARNC", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERRC", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ESYNCC", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];