rigless 0.2.1

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `FDCAN1` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `FDCAN_CREL` at offset `0x0`, resets to `0x0000_0000`, read-only.
    FdcanCrel = 0,
    /// `FDCAN_ENDN` at offset `0x4`, resets to `0x0000_0000`, read-only.
    FdcanEndn = 1,
    /// `FDCAN_DBTP` at offset `0xC`, resets to `0x0000_0000`, read-only.
    FdcanDbtp = 2,
    /// `FDCAN_TEST` at offset `0x10`, resets to `0x0000_0000`, read-only.
    FdcanTest = 3,
    /// `FDCAN_RWD` at offset `0x14`, resets to `0x0000_0000`, read-only.
    FdcanRwd = 4,
    /// `FDCAN_CCCR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    FdcanCccr = 5,
    /// `FDCAN_NBTP` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    FdcanNbtp = 6,
    /// `FDCAN_TSCC` at offset `0x20`, resets to `0x0000_0000`, read-write.
    FdcanTscc = 7,
    /// `FDCAN_TSCV` at offset `0x24`, resets to `0x0000_0000`, read-write.
    FdcanTscv = 8,
    /// `FDCAN_TOCC` at offset `0x28`, resets to `0x0000_0000`, read-write.
    FdcanTocc = 9,
    /// `FDCAN_TOCV` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    FdcanTocv = 10,
    /// `FDCAN_ECR` at offset `0x40`, resets to `0x0000_0000`, read-write.
    FdcanEcr = 11,
    /// `FDCAN_PSR` at offset `0x44`, resets to `0x0000_0000`, read-write.
    FdcanPsr = 12,
    /// `FDCAN_TDCR` at offset `0x48`, resets to `0x0000_0000`, read-only.
    FdcanTdcr = 13,
    /// `FDCAN_IR` at offset `0x50`, resets to `0x0000_0000`, read-only.
    FdcanIr = 14,
    /// `FDCAN_IE` at offset `0x54`, resets to `0x0000_0000`, read-only.
    FdcanIe = 15,
    /// `FDCAN_ILS` at offset `0x58`, resets to `0x0000_0000`, read-only.
    FdcanIls = 16,
    /// `FDCAN_ILE` at offset `0x5C`, resets to `0x0000_0000`, read-write.
    FdcanIle = 17,
    /// `FDCAN_GFC` at offset `0x80`, resets to `0x0000_0000`, read-write.
    FdcanGfc = 18,
    /// `FDCAN_SIDFC` at offset `0x84`, resets to `0x0000_0000`, read-write.
    FdcanSidfc = 19,
    /// `FDCAN_XIDFC` at offset `0x88`, resets to `0x0000_0000`, read-write.
    FdcanXidfc = 20,
    /// `FDCAN_XIDAM` at offset `0x90`, resets to `0x0000_0000`, read-write.
    FdcanXidam = 21,
    /// `FDCAN_HPMS` at offset `0x94`, resets to `0x0000_0000`, read-only.
    FdcanHpms = 22,
    /// `FDCAN_NDAT1` at offset `0x98`, resets to `0x0000_0000`, read-only.
    FdcanNdat1 = 23,
    /// `FDCAN_NDAT2` at offset `0x9C`, resets to `0x0000_0000`, read-only.
    FdcanNdat2 = 24,
    /// `FDCAN_RXF0C` at offset `0xA0`, resets to `0x0000_0000`, read-write.
    FdcanRxf0c = 25,
    /// `FDCAN_RXF0S` at offset `0xA4`, resets to `0x0000_0000`, read-write.
    FdcanRxf0s = 26,
    /// `FDCAN_RXF0A` at offset `0xA8`, resets to `0x0000_0000`, read-write.
    FdcanRxf0a = 27,
    /// `FDCAN_RXBC` at offset `0xAC`, resets to `0x0000_0000`, read-write.
    FdcanRxbc = 28,
    /// `FDCAN_RXF1C` at offset `0xB0`, resets to `0x0000_0000`, read-write.
    FdcanRxf1c = 29,
    /// `FDCAN_RXF1S` at offset `0xB4`, resets to `0x0000_0000`, read-write.
    FdcanRxf1s = 30,
    /// `FDCAN_RXF1A` at offset `0xB8`, resets to `0x0000_0000`, read-write.
    FdcanRxf1a = 31,
    /// `FDCAN_RXESC` at offset `0xBC`, resets to `0x0000_0000`, read-write.
    FdcanRxesc = 32,
    /// `FDCAN_TXBC` at offset `0xC0`, resets to `0x0000_0000`, read-write.
    FdcanTxbc = 33,
    /// `FDCAN_TXFQS` at offset `0xC4`, resets to `0x0000_0000`, read-only.
    FdcanTxfqs = 34,
    /// `FDCAN_TXESC` at offset `0xC8`, resets to `0x0000_0000`, read-write.
    FdcanTxesc = 35,
    /// `FDCAN_TXBRP` at offset `0xCC`, resets to `0x0000_0000`, read-only.
    FdcanTxbrp = 36,
    /// `FDCAN_TXBAR` at offset `0xD0`, resets to `0x0000_0000`, read-write.
    FdcanTxbar = 37,
    /// `FDCAN_TXBCR` at offset `0xD4`, resets to `0x0000_0000`, read-write.
    FdcanTxbcr = 38,
    /// `FDCAN_TXBTO` at offset `0xD8`, resets to `0x0000_0000`, read-write.
    FdcanTxbto = 39,
    /// `FDCAN_TXBCF` at offset `0xDC`, resets to `0x0000_0000`, read-only.
    FdcanTxbcf = 40,
    /// `FDCAN_TXBTIE` at offset `0xE0`, resets to `0x0000_0000`, read-write.
    FdcanTxbtie = 41,
    /// `FDCAN_TXBCIE` at offset `0xE4`, resets to `0x0000_0000`, read-write.
    FdcanTxbcie = 42,
    /// `FDCAN_TXEFC` at offset `0xF0`, resets to `0x0000_0000`, read-write.
    FdcanTxefc = 43,
    /// `FDCAN_TXEFS` at offset `0xF4`, resets to `0x0000_0000`, read-write.
    FdcanTxefs = 44,
    /// `FDCAN_TXEFA` at offset `0xF8`, resets to `0x0000_0000`, read-write.
    FdcanTxefa = 45,
    /// `FDCAN_TTTMC` at offset `0x100`, resets to `0x0000_0000`, read-write.
    FdcanTttmc = 46,
    /// `FDCAN_TTRMC` at offset `0x104`, resets to `0x0000_0000`, read-write.
    FdcanTtrmc = 47,
    /// `FDCAN_TTOCF` at offset `0x108`, resets to `0x0000_0000`, read-write.
    FdcanTtocf = 48,
    /// `FDCAN_TTMLM` at offset `0x10C`, resets to `0x0000_0000`, read-write.
    FdcanTtmlm = 49,
    /// `FDCAN_TURCF` at offset `0x110`, resets to `0x0000_0000`, read-write.
    FdcanTurcf = 50,
    /// `FDCAN_TTOCN` at offset `0x114`, resets to `0x0000_0000`, read-write.
    FdcanTtocn = 51,
    /// `CAN_TTGTP` at offset `0x118`, resets to `0x0000_0000`, read-write.
    CanTtgtp = 52,
    /// `FDCAN_TTTMK` at offset `0x11C`, resets to `0x0000_0000`, read-write.
    FdcanTttmk = 53,
    /// `FDCAN_TTIR` at offset `0x120`, resets to `0x0000_0000`, read-write.
    FdcanTtir = 54,
    /// `FDCAN_TTIE` at offset `0x124`, resets to `0x0000_0000`, read-write.
    FdcanTtie = 55,
    /// `FDCAN_TTILS` at offset `0x128`, resets to `0x0000_0000`, read-write.
    FdcanTtils = 56,
    /// `FDCAN_TTOST` at offset `0x12C`, resets to `0x0000_0000`, read-write.
    FdcanTtost = 57,
    /// `FDCAN_TURNA` at offset `0x130`, resets to `0x0000_0000`, read-only.
    FdcanTurna = 58,
    /// `FDCAN_TTLGT` at offset `0x134`, resets to `0x0000_0000`, read-only.
    FdcanTtlgt = 59,
    /// `FDCAN_TTCTC` at offset `0x138`, resets to `0x0000_0000`, read-only.
    FdcanTtctc = 60,
    /// `FDCAN_TTCPT` at offset `0x13C`, resets to `0x0000_0000`, read-only.
    FdcanTtcpt = 61,
    /// `FDCAN_TTCSM` at offset `0x140`, resets to `0x0000_0000`, read-only.
    FdcanTtcsm = 62,
    /// `FDCAN_TTTS` at offset `0x300`, resets to `0x0000_0000`, read-write.
    FdcanTtts = 63,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 64] = [Self::FdcanCrel, Self::FdcanEndn, Self::FdcanDbtp, Self::FdcanTest, Self::FdcanRwd, Self::FdcanCccr, Self::FdcanNbtp, Self::FdcanTscc, Self::FdcanTscv, Self::FdcanTocc, Self::FdcanTocv, Self::FdcanEcr, Self::FdcanPsr, Self::FdcanTdcr, Self::FdcanIr, Self::FdcanIe, Self::FdcanIls, Self::FdcanIle, Self::FdcanGfc, Self::FdcanSidfc, Self::FdcanXidfc, Self::FdcanXidam, Self::FdcanHpms, Self::FdcanNdat1, Self::FdcanNdat2, Self::FdcanRxf0c, Self::FdcanRxf0s, Self::FdcanRxf0a, Self::FdcanRxbc, Self::FdcanRxf1c, Self::FdcanRxf1s, Self::FdcanRxf1a, Self::FdcanRxesc, Self::FdcanTxbc, Self::FdcanTxfqs, Self::FdcanTxesc, Self::FdcanTxbrp, Self::FdcanTxbar, Self::FdcanTxbcr, Self::FdcanTxbto, Self::FdcanTxbcf, Self::FdcanTxbtie, Self::FdcanTxbcie, Self::FdcanTxefc, Self::FdcanTxefs, Self::FdcanTxefa, Self::FdcanTttmc, Self::FdcanTtrmc, Self::FdcanTtocf, Self::FdcanTtmlm, Self::FdcanTurcf, Self::FdcanTtocn, Self::CanTtgtp, Self::FdcanTttmk, Self::FdcanTtir, Self::FdcanTtie, Self::FdcanTtils, Self::FdcanTtost, Self::FdcanTurna, Self::FdcanTtlgt, Self::FdcanTtctc, Self::FdcanTtcpt, Self::FdcanTtcsm, Self::FdcanTtts];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `FDCAN_CREL`.
pub mod fdcan_crel {
    use super::FieldSpec;
    /// `DAY`, bits 0..=7.
    pub const DAY: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `MON`, bits 8..=15.
    pub const MON: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `YEAR`, bits 16..=19.
    pub const YEAR: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `SUBSTEP`, bits 20..=23.
    pub const SUBSTEP: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `STEP`, bits 24..=27.
    pub const STEP: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `REL`, bits 28..=31.
    pub const REL: &FieldSpec = &super::REGISTERS[0].fields[5];
}

/// The fields of `FDCAN_ENDN`.
pub mod fdcan_endn {
    use super::FieldSpec;
    /// `ETV`, bits 0..=31.
    pub const ETV: &FieldSpec = &super::REGISTERS[1].fields[0];
}

/// The fields of `FDCAN_DBTP`.
pub mod fdcan_dbtp {
    use super::FieldSpec;
    /// `DSJW`, bits 0..=3.
    pub const DSJW: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `DTSEG2`, bits 4..=7.
    pub const DTSEG2: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `DTSEG1`, bits 8..=12.
    pub const DTSEG1: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `DBRP`, bits 16..=20.
    pub const DBRP: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `TDC`, bit 23.
    pub const TDC: &FieldSpec = &super::REGISTERS[2].fields[4];
}

/// The fields of `FDCAN_TEST`.
pub mod fdcan_test {
    use super::FieldSpec;
    /// `LBCK`, bit 4.
    pub const LBCK: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `TX`, bits 5..=6.
    pub const TX: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `RX`, bit 7.
    pub const RX: &FieldSpec = &super::REGISTERS[3].fields[2];
}

/// The fields of `FDCAN_RWD`.
pub mod fdcan_rwd {
    use super::FieldSpec;
    /// `WDC`, bits 0..=7.
    pub const WDC: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `WDV`, bits 8..=15.
    pub const WDV: &FieldSpec = &super::REGISTERS[4].fields[1];
}

/// The fields of `FDCAN_CCCR`.
pub mod fdcan_cccr {
    use super::FieldSpec;
    /// `INIT`, bit 0.
    pub const INIT: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `CCE`, bit 1.
    pub const CCE: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `ASM`, bit 2.
    pub const ASM: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `CSA`, bit 3.
    pub const CSA: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `CSR`, bit 4.
    pub const CSR: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `MON`, bit 5.
    pub const MON: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `DAR`, bit 6.
    pub const DAR: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `TEST`, bit 7.
    pub const TEST: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `FDOE`, bit 8.
    pub const FDOE: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `BSE`, bit 9.
    pub const BSE: &FieldSpec = &super::REGISTERS[5].fields[9];
    /// `PXHD`, bit 12.
    pub const PXHD: &FieldSpec = &super::REGISTERS[5].fields[10];
    /// `EFBI`, bit 13.
    pub const EFBI: &FieldSpec = &super::REGISTERS[5].fields[11];
    /// `TXP`, bit 14.
    pub const TXP: &FieldSpec = &super::REGISTERS[5].fields[12];
    /// `NISO`, bit 15.
    pub const NISO: &FieldSpec = &super::REGISTERS[5].fields[13];
}

/// The fields of `FDCAN_NBTP`.
pub mod fdcan_nbtp {
    use super::FieldSpec;
    /// `TSEG2`, bits 0..=6.
    pub const TSEG2: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `NTSEG1`, bits 8..=15.
    pub const NTSEG1: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `NBRP`, bits 16..=24.
    pub const NBRP: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `NSJW`, bits 25..=31.
    pub const NSJW: &FieldSpec = &super::REGISTERS[6].fields[3];
}

/// The fields of `FDCAN_TSCC`.
pub mod fdcan_tscc {
    use super::FieldSpec;
    /// `TSS`, bits 0..=1.
    pub const TSS: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `TCP`, bits 16..=19.
    pub const TCP: &FieldSpec = &super::REGISTERS[7].fields[1];
}

/// The fields of `FDCAN_TSCV`.
pub mod fdcan_tscv {
    use super::FieldSpec;
    /// `TSC`, bits 0..=15.
    pub const TSC: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `FDCAN_TOCC`.
pub mod fdcan_tocc {
    use super::FieldSpec;
    /// `ETOC`, bit 0.
    pub const ETOC: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `TOS`, bits 1..=2.
    pub const TOS: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `TOP`, bits 16..=31.
    pub const TOP: &FieldSpec = &super::REGISTERS[9].fields[2];
}

/// The fields of `FDCAN_TOCV`.
pub mod fdcan_tocv {
    use super::FieldSpec;
    /// `TOC`, bits 0..=15.
    pub const TOC: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `FDCAN_ECR`.
pub mod fdcan_ecr {
    use super::FieldSpec;
    /// `TEC`, bits 0..=7.
    pub const TEC: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `TREC`, bits 8..=14.
    pub const TREC: &FieldSpec = &super::REGISTERS[11].fields[1];
    /// `RP`, bit 15.
    pub const RP: &FieldSpec = &super::REGISTERS[11].fields[2];
    /// `CEL`, bits 16..=23.
    pub const CEL: &FieldSpec = &super::REGISTERS[11].fields[3];
}

/// The fields of `FDCAN_PSR`.
pub mod fdcan_psr {
    use super::FieldSpec;
    /// `LEC`, bits 0..=2.
    pub const LEC: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `ACT`, bits 3..=4.
    pub const ACT: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `EP`, bit 5.
    pub const EP: &FieldSpec = &super::REGISTERS[12].fields[2];
    /// `EW`, bit 6.
    pub const EW: &FieldSpec = &super::REGISTERS[12].fields[3];
    /// `BO`, bit 7.
    pub const BO: &FieldSpec = &super::REGISTERS[12].fields[4];
    /// `DLEC`, bits 8..=10.
    pub const DLEC: &FieldSpec = &super::REGISTERS[12].fields[5];
    /// `RESI`, bit 11.
    pub const RESI: &FieldSpec = &super::REGISTERS[12].fields[6];
    /// `RBRS`, bit 12.
    pub const RBRS: &FieldSpec = &super::REGISTERS[12].fields[7];
    /// `REDL`, bit 13.
    pub const REDL: &FieldSpec = &super::REGISTERS[12].fields[8];
    /// `PXE`, bit 14.
    pub const PXE: &FieldSpec = &super::REGISTERS[12].fields[9];
    /// `TDCV`, bits 16..=22.
    pub const TDCV: &FieldSpec = &super::REGISTERS[12].fields[10];
}

/// The fields of `FDCAN_TDCR`.
pub mod fdcan_tdcr {
    use super::FieldSpec;
    /// `TDCF`, bits 0..=6.
    pub const TDCF: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `TDCO`, bits 8..=14.
    pub const TDCO: &FieldSpec = &super::REGISTERS[13].fields[1];
}

/// The fields of `FDCAN_IR`.
pub mod fdcan_ir {
    use super::FieldSpec;
    /// `RF0N`, bit 0.
    pub const RF0N: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `RF0W`, bit 1.
    pub const RF0W: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `RF0F`, bit 2.
    pub const RF0F: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `RF0L`, bit 3.
    pub const RF0L: &FieldSpec = &super::REGISTERS[14].fields[3];
    /// `RF1N`, bit 4.
    pub const RF1N: &FieldSpec = &super::REGISTERS[14].fields[4];
    /// `RF1W`, bit 5.
    pub const RF1W: &FieldSpec = &super::REGISTERS[14].fields[5];
    /// `RF1F`, bit 6.
    pub const RF1F: &FieldSpec = &super::REGISTERS[14].fields[6];
    /// `RF1L`, bit 7.
    pub const RF1L: &FieldSpec = &super::REGISTERS[14].fields[7];
    /// `HPM`, bit 8.
    pub const HPM: &FieldSpec = &super::REGISTERS[14].fields[8];
    /// `TC`, bit 9.
    pub const TC: &FieldSpec = &super::REGISTERS[14].fields[9];
    /// `TCF`, bit 10.
    pub const TCF: &FieldSpec = &super::REGISTERS[14].fields[10];
    /// `TEF`, bit 11.
    pub const TEF: &FieldSpec = &super::REGISTERS[14].fields[11];
    /// `TEFN`, bit 12.
    pub const TEFN: &FieldSpec = &super::REGISTERS[14].fields[12];
    /// `TEFW`, bit 13.
    pub const TEFW: &FieldSpec = &super::REGISTERS[14].fields[13];
    /// `TEFF`, bit 14.
    pub const TEFF: &FieldSpec = &super::REGISTERS[14].fields[14];
    /// `TEFL`, bit 15.
    pub const TEFL: &FieldSpec = &super::REGISTERS[14].fields[15];
    /// `TSW`, bit 16.
    pub const TSW: &FieldSpec = &super::REGISTERS[14].fields[16];
    /// `MRAF`, bit 17.
    pub const MRAF: &FieldSpec = &super::REGISTERS[14].fields[17];
    /// `TOO`, bit 18.
    pub const TOO: &FieldSpec = &super::REGISTERS[14].fields[18];
    /// `DRX`, bit 19.
    pub const DRX: &FieldSpec = &super::REGISTERS[14].fields[19];
    /// `ELO`, bit 22.
    pub const ELO: &FieldSpec = &super::REGISTERS[14].fields[20];
    /// `EP`, bit 23.
    pub const EP: &FieldSpec = &super::REGISTERS[14].fields[21];
    /// `EW`, bit 24.
    pub const EW: &FieldSpec = &super::REGISTERS[14].fields[22];
    /// `BO`, bit 25.
    pub const BO: &FieldSpec = &super::REGISTERS[14].fields[23];
    /// `WDI`, bit 26.
    pub const WDI: &FieldSpec = &super::REGISTERS[14].fields[24];
    /// `PEA`, bit 27.
    pub const PEA: &FieldSpec = &super::REGISTERS[14].fields[25];
    /// `PED`, bit 28.
    pub const PED: &FieldSpec = &super::REGISTERS[14].fields[26];
    /// `ARA`, bit 29.
    pub const ARA: &FieldSpec = &super::REGISTERS[14].fields[27];
}

/// The fields of `FDCAN_IE`.
pub mod fdcan_ie {
    use super::FieldSpec;
    /// `RF0NE`, bit 0.
    pub const RF0NE: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `RF0WE`, bit 1.
    pub const RF0WE: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `RF0FE`, bit 2.
    pub const RF0FE: &FieldSpec = &super::REGISTERS[15].fields[2];
    /// `RF0LE`, bit 3.
    pub const RF0LE: &FieldSpec = &super::REGISTERS[15].fields[3];
    /// `RF1NE`, bit 4.
    pub const RF1NE: &FieldSpec = &super::REGISTERS[15].fields[4];
    /// `RF1WE`, bit 5.
    pub const RF1WE: &FieldSpec = &super::REGISTERS[15].fields[5];
    /// `RF1FE`, bit 6.
    pub const RF1FE: &FieldSpec = &super::REGISTERS[15].fields[6];
    /// `RF1LE`, bit 7.
    pub const RF1LE: &FieldSpec = &super::REGISTERS[15].fields[7];
    /// `HPME`, bit 8.
    pub const HPME: &FieldSpec = &super::REGISTERS[15].fields[8];
    /// `TCE`, bit 9.
    pub const TCE: &FieldSpec = &super::REGISTERS[15].fields[9];
    /// `TCFE`, bit 10.
    pub const TCFE: &FieldSpec = &super::REGISTERS[15].fields[10];
    /// `TEFE`, bit 11.
    pub const TEFE: &FieldSpec = &super::REGISTERS[15].fields[11];
    /// `TEFNE`, bit 12.
    pub const TEFNE: &FieldSpec = &super::REGISTERS[15].fields[12];
    /// `TEFWE`, bit 13.
    pub const TEFWE: &FieldSpec = &super::REGISTERS[15].fields[13];
    /// `TEFFE`, bit 14.
    pub const TEFFE: &FieldSpec = &super::REGISTERS[15].fields[14];
    /// `TEFLE`, bit 15.
    pub const TEFLE: &FieldSpec = &super::REGISTERS[15].fields[15];
    /// `TSWE`, bit 16.
    pub const TSWE: &FieldSpec = &super::REGISTERS[15].fields[16];
    /// `MRAFE`, bit 17.
    pub const MRAFE: &FieldSpec = &super::REGISTERS[15].fields[17];
    /// `TOOE`, bit 18.
    pub const TOOE: &FieldSpec = &super::REGISTERS[15].fields[18];
    /// `DRXE`, bit 19.
    pub const DRXE: &FieldSpec = &super::REGISTERS[15].fields[19];
    /// `BECE`, bit 20.
    pub const BECE: &FieldSpec = &super::REGISTERS[15].fields[20];
    /// `BEUE`, bit 21.
    pub const BEUE: &FieldSpec = &super::REGISTERS[15].fields[21];
    /// `ELOE`, bit 22.
    pub const ELOE: &FieldSpec = &super::REGISTERS[15].fields[22];
    /// `EPE`, bit 23.
    pub const EPE: &FieldSpec = &super::REGISTERS[15].fields[23];
    /// `EWE`, bit 24.
    pub const EWE: &FieldSpec = &super::REGISTERS[15].fields[24];
    /// `BOE`, bit 25.
    pub const BOE: &FieldSpec = &super::REGISTERS[15].fields[25];
    /// `WDIE`, bit 26.
    pub const WDIE: &FieldSpec = &super::REGISTERS[15].fields[26];
    /// `PEAE`, bit 27.
    pub const PEAE: &FieldSpec = &super::REGISTERS[15].fields[27];
    /// `PEDE`, bit 28.
    pub const PEDE: &FieldSpec = &super::REGISTERS[15].fields[28];
    /// `ARAE`, bit 29.
    pub const ARAE: &FieldSpec = &super::REGISTERS[15].fields[29];
}

/// The fields of `FDCAN_ILS`.
pub mod fdcan_ils {
    use super::FieldSpec;
    /// `RF0NL`, bit 0.
    pub const RF0NL: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `RF0WL`, bit 1.
    pub const RF0WL: &FieldSpec = &super::REGISTERS[16].fields[1];
    /// `RF0FL`, bit 2.
    pub const RF0FL: &FieldSpec = &super::REGISTERS[16].fields[2];
    /// `RF0LL`, bit 3.
    pub const RF0LL: &FieldSpec = &super::REGISTERS[16].fields[3];
    /// `RF1NL`, bit 4.
    pub const RF1NL: &FieldSpec = &super::REGISTERS[16].fields[4];
    /// `RF1WL`, bit 5.
    pub const RF1WL: &FieldSpec = &super::REGISTERS[16].fields[5];
    /// `RF1FL`, bit 6.
    pub const RF1FL: &FieldSpec = &super::REGISTERS[16].fields[6];
    /// `RF1LL`, bit 7.
    pub const RF1LL: &FieldSpec = &super::REGISTERS[16].fields[7];
    /// `HPML`, bit 8.
    pub const HPML: &FieldSpec = &super::REGISTERS[16].fields[8];
    /// `TCL`, bit 9.
    pub const TCL: &FieldSpec = &super::REGISTERS[16].fields[9];
    /// `TCFL`, bit 10.
    pub const TCFL: &FieldSpec = &super::REGISTERS[16].fields[10];
    /// `TEFL`, bit 11.
    pub const TEFL: &FieldSpec = &super::REGISTERS[16].fields[11];
    /// `TEFNL`, bit 12.
    pub const TEFNL: &FieldSpec = &super::REGISTERS[16].fields[12];
    /// `TEFWL`, bit 13.
    pub const TEFWL: &FieldSpec = &super::REGISTERS[16].fields[13];
    /// `TEFFL`, bit 14.
    pub const TEFFL: &FieldSpec = &super::REGISTERS[16].fields[14];
    /// `TEFLL`, bit 15.
    pub const TEFLL: &FieldSpec = &super::REGISTERS[16].fields[15];
    /// `TSWL`, bit 16.
    pub const TSWL: &FieldSpec = &super::REGISTERS[16].fields[16];
    /// `MRAFL`, bit 17.
    pub const MRAFL: &FieldSpec = &super::REGISTERS[16].fields[17];
    /// `TOOL`, bit 18.
    pub const TOOL: &FieldSpec = &super::REGISTERS[16].fields[18];
    /// `DRXL`, bit 19.
    pub const DRXL: &FieldSpec = &super::REGISTERS[16].fields[19];
    /// `BECL`, bit 20.
    pub const BECL: &FieldSpec = &super::REGISTERS[16].fields[20];
    /// `BEUL`, bit 21.
    pub const BEUL: &FieldSpec = &super::REGISTERS[16].fields[21];
    /// `ELOL`, bit 22.
    pub const ELOL: &FieldSpec = &super::REGISTERS[16].fields[22];
    /// `EPL`, bit 23.
    pub const EPL: &FieldSpec = &super::REGISTERS[16].fields[23];
    /// `EWL`, bit 24.
    pub const EWL: &FieldSpec = &super::REGISTERS[16].fields[24];
    /// `BOL`, bit 25.
    pub const BOL: &FieldSpec = &super::REGISTERS[16].fields[25];
    /// `WDIL`, bit 26.
    pub const WDIL: &FieldSpec = &super::REGISTERS[16].fields[26];
    /// `PEAL`, bit 27.
    pub const PEAL: &FieldSpec = &super::REGISTERS[16].fields[27];
    /// `PEDL`, bit 28.
    pub const PEDL: &FieldSpec = &super::REGISTERS[16].fields[28];
    /// `ARAL`, bit 29.
    pub const ARAL: &FieldSpec = &super::REGISTERS[16].fields[29];
}

/// The fields of `FDCAN_ILE`.
pub mod fdcan_ile {
    use super::FieldSpec;
    /// `EINT0`, bit 0.
    pub const EINT0: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `EINT1`, bit 1.
    pub const EINT1: &FieldSpec = &super::REGISTERS[17].fields[1];
}

/// The fields of `FDCAN_GFC`.
pub mod fdcan_gfc {
    use super::FieldSpec;
    /// `RRFE`, bit 0.
    pub const RRFE: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `RRFS`, bit 1.
    pub const RRFS: &FieldSpec = &super::REGISTERS[18].fields[1];
    /// `ANFE`, bits 2..=3.
    pub const ANFE: &FieldSpec = &super::REGISTERS[18].fields[2];
    /// `ANFS`, bits 4..=5.
    pub const ANFS: &FieldSpec = &super::REGISTERS[18].fields[3];
}

/// The fields of `FDCAN_SIDFC`.
pub mod fdcan_sidfc {
    use super::FieldSpec;
    /// `FLSSA`, bits 2..=15.
    pub const FLSSA: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `LSS`, bits 16..=23.
    pub const LSS: &FieldSpec = &super::REGISTERS[19].fields[1];
}

/// The fields of `FDCAN_XIDFC`.
pub mod fdcan_xidfc {
    use super::FieldSpec;
    /// `FLESA`, bits 2..=15.
    pub const FLESA: &FieldSpec = &super::REGISTERS[20].fields[0];
    /// `LSE`, bits 16..=23.
    pub const LSE: &FieldSpec = &super::REGISTERS[20].fields[1];
}

/// The fields of `FDCAN_XIDAM`.
pub mod fdcan_xidam {
    use super::FieldSpec;
    /// `EIDM`, bits 0..=28.
    pub const EIDM: &FieldSpec = &super::REGISTERS[21].fields[0];
}

/// The fields of `FDCAN_HPMS`.
pub mod fdcan_hpms {
    use super::FieldSpec;
    /// `BIDX`, bits 0..=5.
    pub const BIDX: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `MSI`, bits 6..=7.
    pub const MSI: &FieldSpec = &super::REGISTERS[22].fields[1];
    /// `FIDX`, bits 8..=14.
    pub const FIDX: &FieldSpec = &super::REGISTERS[22].fields[2];
    /// `FLST`, bit 15.
    pub const FLST: &FieldSpec = &super::REGISTERS[22].fields[3];
}

/// The fields of `FDCAN_NDAT1`.
pub mod fdcan_ndat1 {
    use super::FieldSpec;
    /// `ND0`, bit 0.
    pub const ND0: &FieldSpec = &super::REGISTERS[23].fields[0];
    /// `ND1`, bit 1.
    pub const ND1: &FieldSpec = &super::REGISTERS[23].fields[1];
    /// `ND2`, bit 2.
    pub const ND2: &FieldSpec = &super::REGISTERS[23].fields[2];
    /// `ND3`, bit 3.
    pub const ND3: &FieldSpec = &super::REGISTERS[23].fields[3];
    /// `ND4`, bit 4.
    pub const ND4: &FieldSpec = &super::REGISTERS[23].fields[4];
    /// `ND5`, bit 5.
    pub const ND5: &FieldSpec = &super::REGISTERS[23].fields[5];
    /// `ND6`, bit 6.
    pub const ND6: &FieldSpec = &super::REGISTERS[23].fields[6];
    /// `ND7`, bit 7.
    pub const ND7: &FieldSpec = &super::REGISTERS[23].fields[7];
    /// `ND8`, bit 8.
    pub const ND8: &FieldSpec = &super::REGISTERS[23].fields[8];
    /// `ND9`, bit 9.
    pub const ND9: &FieldSpec = &super::REGISTERS[23].fields[9];
    /// `ND10`, bit 10.
    pub const ND10: &FieldSpec = &super::REGISTERS[23].fields[10];
    /// `ND11`, bit 11.
    pub const ND11: &FieldSpec = &super::REGISTERS[23].fields[11];
    /// `ND12`, bit 12.
    pub const ND12: &FieldSpec = &super::REGISTERS[23].fields[12];
    /// `ND13`, bit 13.
    pub const ND13: &FieldSpec = &super::REGISTERS[23].fields[13];
    /// `ND14`, bit 14.
    pub const ND14: &FieldSpec = &super::REGISTERS[23].fields[14];
    /// `ND15`, bit 15.
    pub const ND15: &FieldSpec = &super::REGISTERS[23].fields[15];
    /// `ND16`, bit 16.
    pub const ND16: &FieldSpec = &super::REGISTERS[23].fields[16];
    /// `ND17`, bit 17.
    pub const ND17: &FieldSpec = &super::REGISTERS[23].fields[17];
    /// `ND18`, bit 18.
    pub const ND18: &FieldSpec = &super::REGISTERS[23].fields[18];
    /// `ND19`, bit 19.
    pub const ND19: &FieldSpec = &super::REGISTERS[23].fields[19];
    /// `ND20`, bit 20.
    pub const ND20: &FieldSpec = &super::REGISTERS[23].fields[20];
    /// `ND21`, bit 21.
    pub const ND21: &FieldSpec = &super::REGISTERS[23].fields[21];
    /// `ND22`, bit 22.
    pub const ND22: &FieldSpec = &super::REGISTERS[23].fields[22];
    /// `ND23`, bit 23.
    pub const ND23: &FieldSpec = &super::REGISTERS[23].fields[23];
    /// `ND24`, bit 24.
    pub const ND24: &FieldSpec = &super::REGISTERS[23].fields[24];
    /// `ND25`, bit 25.
    pub const ND25: &FieldSpec = &super::REGISTERS[23].fields[25];
    /// `ND26`, bit 26.
    pub const ND26: &FieldSpec = &super::REGISTERS[23].fields[26];
    /// `ND27`, bit 27.
    pub const ND27: &FieldSpec = &super::REGISTERS[23].fields[27];
    /// `ND28`, bit 28.
    pub const ND28: &FieldSpec = &super::REGISTERS[23].fields[28];
    /// `ND29`, bit 29.
    pub const ND29: &FieldSpec = &super::REGISTERS[23].fields[29];
    /// `ND30`, bit 30.
    pub const ND30: &FieldSpec = &super::REGISTERS[23].fields[30];
    /// `ND31`, bit 31.
    pub const ND31: &FieldSpec = &super::REGISTERS[23].fields[31];
}

/// The fields of `FDCAN_NDAT2`.
pub mod fdcan_ndat2 {
    use super::FieldSpec;
    /// `ND32`, bit 0.
    pub const ND32: &FieldSpec = &super::REGISTERS[24].fields[0];
    /// `ND33`, bit 1.
    pub const ND33: &FieldSpec = &super::REGISTERS[24].fields[1];
    /// `ND34`, bit 2.
    pub const ND34: &FieldSpec = &super::REGISTERS[24].fields[2];
    /// `ND35`, bit 3.
    pub const ND35: &FieldSpec = &super::REGISTERS[24].fields[3];
    /// `ND36`, bit 4.
    pub const ND36: &FieldSpec = &super::REGISTERS[24].fields[4];
    /// `ND37`, bit 5.
    pub const ND37: &FieldSpec = &super::REGISTERS[24].fields[5];
    /// `ND38`, bit 6.
    pub const ND38: &FieldSpec = &super::REGISTERS[24].fields[6];
    /// `ND39`, bit 7.
    pub const ND39: &FieldSpec = &super::REGISTERS[24].fields[7];
    /// `ND40`, bit 8.
    pub const ND40: &FieldSpec = &super::REGISTERS[24].fields[8];
    /// `ND41`, bit 9.
    pub const ND41: &FieldSpec = &super::REGISTERS[24].fields[9];
    /// `ND42`, bit 10.
    pub const ND42: &FieldSpec = &super::REGISTERS[24].fields[10];
    /// `ND43`, bit 11.
    pub const ND43: &FieldSpec = &super::REGISTERS[24].fields[11];
    /// `ND44`, bit 12.
    pub const ND44: &FieldSpec = &super::REGISTERS[24].fields[12];
    /// `ND45`, bit 13.
    pub const ND45: &FieldSpec = &super::REGISTERS[24].fields[13];
    /// `ND46`, bit 14.
    pub const ND46: &FieldSpec = &super::REGISTERS[24].fields[14];
    /// `ND47`, bit 15.
    pub const ND47: &FieldSpec = &super::REGISTERS[24].fields[15];
    /// `ND48`, bit 16.
    pub const ND48: &FieldSpec = &super::REGISTERS[24].fields[16];
    /// `ND49`, bit 17.
    pub const ND49: &FieldSpec = &super::REGISTERS[24].fields[17];
    /// `ND50`, bit 18.
    pub const ND50: &FieldSpec = &super::REGISTERS[24].fields[18];
    /// `ND51`, bit 19.
    pub const ND51: &FieldSpec = &super::REGISTERS[24].fields[19];
    /// `ND52`, bit 20.
    pub const ND52: &FieldSpec = &super::REGISTERS[24].fields[20];
    /// `ND53`, bit 21.
    pub const ND53: &FieldSpec = &super::REGISTERS[24].fields[21];
    /// `ND54`, bit 22.
    pub const ND54: &FieldSpec = &super::REGISTERS[24].fields[22];
    /// `ND55`, bit 23.
    pub const ND55: &FieldSpec = &super::REGISTERS[24].fields[23];
    /// `ND56`, bit 24.
    pub const ND56: &FieldSpec = &super::REGISTERS[24].fields[24];
    /// `ND57`, bit 25.
    pub const ND57: &FieldSpec = &super::REGISTERS[24].fields[25];
    /// `ND58`, bit 26.
    pub const ND58: &FieldSpec = &super::REGISTERS[24].fields[26];
    /// `ND59`, bit 27.
    pub const ND59: &FieldSpec = &super::REGISTERS[24].fields[27];
    /// `ND60`, bit 28.
    pub const ND60: &FieldSpec = &super::REGISTERS[24].fields[28];
    /// `ND61`, bit 29.
    pub const ND61: &FieldSpec = &super::REGISTERS[24].fields[29];
    /// `ND62`, bit 30.
    pub const ND62: &FieldSpec = &super::REGISTERS[24].fields[30];
    /// `ND63`, bit 31.
    pub const ND63: &FieldSpec = &super::REGISTERS[24].fields[31];
}

/// The fields of `FDCAN_RXF0C`.
pub mod fdcan_rxf0c {
    use super::FieldSpec;
    /// `F0SA`, bits 2..=15.
    pub const F0SA: &FieldSpec = &super::REGISTERS[25].fields[0];
    /// `F0S`, bits 16..=23.
    pub const F0S: &FieldSpec = &super::REGISTERS[25].fields[1];
    /// `F0WM`, bits 24..=31.
    pub const F0WM: &FieldSpec = &super::REGISTERS[25].fields[2];
}

/// The fields of `FDCAN_RXF0S`.
pub mod fdcan_rxf0s {
    use super::FieldSpec;
    /// `F0FL`, bits 0..=6.
    pub const F0FL: &FieldSpec = &super::REGISTERS[26].fields[0];
    /// `F0G`, bits 8..=13.
    pub const F0G: &FieldSpec = &super::REGISTERS[26].fields[1];
    /// `F0P`, bits 16..=21.
    pub const F0P: &FieldSpec = &super::REGISTERS[26].fields[2];
    /// `F0F`, bit 24.
    pub const F0F: &FieldSpec = &super::REGISTERS[26].fields[3];
    /// `RF0L`, bit 25.
    pub const RF0L: &FieldSpec = &super::REGISTERS[26].fields[4];
}

/// The fields of `FDCAN_RXF0A`.
pub mod fdcan_rxf0a {
    use super::FieldSpec;
    /// `FA01`, bits 0..=5.
    pub const FA01: &FieldSpec = &super::REGISTERS[27].fields[0];
}

/// The fields of `FDCAN_RXBC`.
pub mod fdcan_rxbc {
    use super::FieldSpec;
    /// `RBSA`, bits 2..=15.
    pub const RBSA: &FieldSpec = &super::REGISTERS[28].fields[0];
}

/// The fields of `FDCAN_RXF1C`.
pub mod fdcan_rxf1c {
    use super::FieldSpec;
    /// `F1SA`, bits 2..=15.
    pub const F1SA: &FieldSpec = &super::REGISTERS[29].fields[0];
    /// `F1S`, bits 16..=22.
    pub const F1S: &FieldSpec = &super::REGISTERS[29].fields[1];
    /// `F1WM`, bits 24..=30.
    pub const F1WM: &FieldSpec = &super::REGISTERS[29].fields[2];
}

/// The fields of `FDCAN_RXF1S`.
pub mod fdcan_rxf1s {
    use super::FieldSpec;
    /// `F1FL`, bits 0..=6.
    pub const F1FL: &FieldSpec = &super::REGISTERS[30].fields[0];
    /// `F1GI`, bits 8..=14.
    pub const F1GI: &FieldSpec = &super::REGISTERS[30].fields[1];
    /// `F1PI`, bits 16..=22.
    pub const F1PI: &FieldSpec = &super::REGISTERS[30].fields[2];
    /// `F1F`, bit 24.
    pub const F1F: &FieldSpec = &super::REGISTERS[30].fields[3];
    /// `RF1L`, bit 25.
    pub const RF1L: &FieldSpec = &super::REGISTERS[30].fields[4];
    /// `DMS`, bits 30..=31.
    pub const DMS: &FieldSpec = &super::REGISTERS[30].fields[5];
}

/// The fields of `FDCAN_RXF1A`.
pub mod fdcan_rxf1a {
    use super::FieldSpec;
    /// `F1AI`, bits 0..=5.
    pub const F1AI: &FieldSpec = &super::REGISTERS[31].fields[0];
}

/// The fields of `FDCAN_RXESC`.
pub mod fdcan_rxesc {
    use super::FieldSpec;
    /// `F0DS`, bits 0..=2.
    pub const F0DS: &FieldSpec = &super::REGISTERS[32].fields[0];
    /// `F1DS`, bits 4..=6.
    pub const F1DS: &FieldSpec = &super::REGISTERS[32].fields[1];
    /// `RBDS`, bits 8..=10.
    pub const RBDS: &FieldSpec = &super::REGISTERS[32].fields[2];
}

/// The fields of `FDCAN_TXBC`.
pub mod fdcan_txbc {
    use super::FieldSpec;
    /// `TBSA`, bits 2..=15.
    pub const TBSA: &FieldSpec = &super::REGISTERS[33].fields[0];
    /// `NDTB`, bits 16..=21.
    pub const NDTB: &FieldSpec = &super::REGISTERS[33].fields[1];
    /// `TFQS`, bits 24..=29.
    pub const TFQS: &FieldSpec = &super::REGISTERS[33].fields[2];
    /// `TFQM`, bit 30.
    pub const TFQM: &FieldSpec = &super::REGISTERS[33].fields[3];
}

/// The fields of `FDCAN_TXFQS`.
pub mod fdcan_txfqs {
    use super::FieldSpec;
    /// `TFFL`, bits 0..=5.
    pub const TFFL: &FieldSpec = &super::REGISTERS[34].fields[0];
    /// `TFGI`, bits 8..=12.
    pub const TFGI: &FieldSpec = &super::REGISTERS[34].fields[1];
    /// `TFQPI`, bits 16..=20.
    pub const TFQPI: &FieldSpec = &super::REGISTERS[34].fields[2];
    /// `TFQF`, bit 21.
    pub const TFQF: &FieldSpec = &super::REGISTERS[34].fields[3];
}

/// The fields of `FDCAN_TXESC`.
pub mod fdcan_txesc {
    use super::FieldSpec;
    /// `TBDS`, bits 0..=2.
    pub const TBDS: &FieldSpec = &super::REGISTERS[35].fields[0];
}

/// The fields of `FDCAN_TXBRP`.
pub mod fdcan_txbrp {
    use super::FieldSpec;
    /// `TRP`, bits 0..=31.
    pub const TRP: &FieldSpec = &super::REGISTERS[36].fields[0];
}

/// The fields of `FDCAN_TXBAR`.
pub mod fdcan_txbar {
    use super::FieldSpec;
    /// `AR`, bits 0..=31.
    pub const AR: &FieldSpec = &super::REGISTERS[37].fields[0];
}

/// The fields of `FDCAN_TXBCR`.
pub mod fdcan_txbcr {
    use super::FieldSpec;
    /// `CR`, bits 0..=31.
    pub const CR: &FieldSpec = &super::REGISTERS[38].fields[0];
}

/// The fields of `FDCAN_TXBTO`.
pub mod fdcan_txbto {
    use super::FieldSpec;
    /// `TO`, bits 0..=31.
    pub const TO: &FieldSpec = &super::REGISTERS[39].fields[0];
}

/// The fields of `FDCAN_TXBCF`.
pub mod fdcan_txbcf {
    use super::FieldSpec;
    /// `CF`, bits 0..=31.
    pub const CF: &FieldSpec = &super::REGISTERS[40].fields[0];
}

/// The fields of `FDCAN_TXBTIE`.
pub mod fdcan_txbtie {
    use super::FieldSpec;
    /// `TIE`, bits 0..=31.
    pub const TIE: &FieldSpec = &super::REGISTERS[41].fields[0];
}

/// The fields of `FDCAN_TXBCIE`.
pub mod fdcan_txbcie {
    use super::FieldSpec;
    /// `CF`, bits 0..=31.
    pub const CF: &FieldSpec = &super::REGISTERS[42].fields[0];
}

/// The fields of `FDCAN_TXEFC`.
pub mod fdcan_txefc {
    use super::FieldSpec;
    /// `EFSA`, bits 2..=15.
    pub const EFSA: &FieldSpec = &super::REGISTERS[43].fields[0];
    /// `EFS`, bits 16..=21.
    pub const EFS: &FieldSpec = &super::REGISTERS[43].fields[1];
    /// `EFWM`, bits 24..=29.
    pub const EFWM: &FieldSpec = &super::REGISTERS[43].fields[2];
}

/// The fields of `FDCAN_TXEFS`.
pub mod fdcan_txefs {
    use super::FieldSpec;
    /// `EFFL`, bits 0..=5.
    pub const EFFL: &FieldSpec = &super::REGISTERS[44].fields[0];
    /// `EFGI`, bits 8..=12.
    pub const EFGI: &FieldSpec = &super::REGISTERS[44].fields[1];
    /// `EFPI`, bits 16..=20.
    pub const EFPI: &FieldSpec = &super::REGISTERS[44].fields[2];
    /// `EFF`, bit 24.
    pub const EFF: &FieldSpec = &super::REGISTERS[44].fields[3];
    /// `TEFL`, bit 25.
    pub const TEFL: &FieldSpec = &super::REGISTERS[44].fields[4];
}

/// The fields of `FDCAN_TXEFA`.
pub mod fdcan_txefa {
    use super::FieldSpec;
    /// `EFAI`, bits 0..=4.
    pub const EFAI: &FieldSpec = &super::REGISTERS[45].fields[0];
}

/// The fields of `FDCAN_TTTMC`.
pub mod fdcan_tttmc {
    use super::FieldSpec;
    /// `TMSA`, bits 2..=15.
    pub const TMSA: &FieldSpec = &super::REGISTERS[46].fields[0];
    /// `TME`, bits 16..=22.
    pub const TME: &FieldSpec = &super::REGISTERS[46].fields[1];
}

/// The fields of `FDCAN_TTRMC`.
pub mod fdcan_ttrmc {
    use super::FieldSpec;
    /// `RID`, bits 0..=28.
    pub const RID: &FieldSpec = &super::REGISTERS[47].fields[0];
    /// `XTD`, bit 30.
    pub const XTD: &FieldSpec = &super::REGISTERS[47].fields[1];
    /// `RMPS`, bit 31.
    pub const RMPS: &FieldSpec = &super::REGISTERS[47].fields[2];
}

/// The fields of `FDCAN_TTOCF`.
pub mod fdcan_ttocf {
    use super::FieldSpec;
    /// `OM`, bits 0..=1.
    pub const OM: &FieldSpec = &super::REGISTERS[48].fields[0];
    /// `GEN`, bit 3.
    pub const GEN: &FieldSpec = &super::REGISTERS[48].fields[1];
    /// `TM`, bit 4.
    pub const TM: &FieldSpec = &super::REGISTERS[48].fields[2];
    /// `LDSDL`, bits 5..=7.
    pub const LDSDL: &FieldSpec = &super::REGISTERS[48].fields[3];
    /// `IRTO`, bits 8..=14.
    pub const IRTO: &FieldSpec = &super::REGISTERS[48].fields[4];
    /// `EECS`, bit 15.
    pub const EECS: &FieldSpec = &super::REGISTERS[48].fields[5];
    /// `AWL`, bits 16..=23.
    pub const AWL: &FieldSpec = &super::REGISTERS[48].fields[6];
    /// `EGTF`, bit 24.
    pub const EGTF: &FieldSpec = &super::REGISTERS[48].fields[7];
    /// `ECC`, bit 25.
    pub const ECC: &FieldSpec = &super::REGISTERS[48].fields[8];
    /// `EVTP`, bit 26.
    pub const EVTP: &FieldSpec = &super::REGISTERS[48].fields[9];
}

/// The fields of `FDCAN_TTMLM`.
pub mod fdcan_ttmlm {
    use super::FieldSpec;
    /// `CCM`, bits 0..=5.
    pub const CCM: &FieldSpec = &super::REGISTERS[49].fields[0];
    /// `CSS`, bits 6..=7.
    pub const CSS: &FieldSpec = &super::REGISTERS[49].fields[1];
    /// `TXEW`, bits 8..=11.
    pub const TXEW: &FieldSpec = &super::REGISTERS[49].fields[2];
    /// `ENTT`, bits 16..=27.
    pub const ENTT: &FieldSpec = &super::REGISTERS[49].fields[3];
}

/// The fields of `FDCAN_TURCF`.
pub mod fdcan_turcf {
    use super::FieldSpec;
    /// `NCL`, bits 0..=15.
    pub const NCL: &FieldSpec = &super::REGISTERS[50].fields[0];
    /// `DC`, bits 16..=29.
    pub const DC: &FieldSpec = &super::REGISTERS[50].fields[1];
    /// `ELT`, bit 31.
    pub const ELT: &FieldSpec = &super::REGISTERS[50].fields[2];
}

/// The fields of `FDCAN_TTOCN`.
pub mod fdcan_ttocn {
    use super::FieldSpec;
    /// `SGT`, bit 0.
    pub const SGT: &FieldSpec = &super::REGISTERS[51].fields[0];
    /// `ECS`, bit 1.
    pub const ECS: &FieldSpec = &super::REGISTERS[51].fields[1];
    /// `SWP`, bit 2.
    pub const SWP: &FieldSpec = &super::REGISTERS[51].fields[2];
    /// `SWS`, bits 3..=4.
    pub const SWS: &FieldSpec = &super::REGISTERS[51].fields[3];
    /// `RTIE`, bit 5.
    pub const RTIE: &FieldSpec = &super::REGISTERS[51].fields[4];
    /// `TMC`, bits 6..=7.
    pub const TMC: &FieldSpec = &super::REGISTERS[51].fields[5];
    /// `TTIE`, bit 8.
    pub const TTIE: &FieldSpec = &super::REGISTERS[51].fields[6];
    /// `GCS`, bit 9.
    pub const GCS: &FieldSpec = &super::REGISTERS[51].fields[7];
    /// `FGP`, bit 10.
    pub const FGP: &FieldSpec = &super::REGISTERS[51].fields[8];
    /// `TMG`, bit 11.
    pub const TMG: &FieldSpec = &super::REGISTERS[51].fields[9];
    /// `NIG`, bit 12.
    pub const NIG: &FieldSpec = &super::REGISTERS[51].fields[10];
    /// `ESCN`, bit 13.
    pub const ESCN: &FieldSpec = &super::REGISTERS[51].fields[11];
    /// `LCKC`, bit 15.
    pub const LCKC: &FieldSpec = &super::REGISTERS[51].fields[12];
}

/// The fields of `CAN_TTGTP`.
pub mod can_ttgtp {
    use super::FieldSpec;
    /// `NCL`, bits 0..=15.
    pub const NCL: &FieldSpec = &super::REGISTERS[52].fields[0];
    /// `CTP`, bits 16..=31.
    pub const CTP: &FieldSpec = &super::REGISTERS[52].fields[1];
}

/// The fields of `FDCAN_TTTMK`.
pub mod fdcan_tttmk {
    use super::FieldSpec;
    /// `TM`, bits 0..=15.
    pub const TM: &FieldSpec = &super::REGISTERS[53].fields[0];
    /// `TICC`, bits 16..=22.
    pub const TICC: &FieldSpec = &super::REGISTERS[53].fields[1];
    /// `LCKM`, bit 31.
    pub const LCKM: &FieldSpec = &super::REGISTERS[53].fields[2];
}

/// The fields of `FDCAN_TTIR`.
pub mod fdcan_ttir {
    use super::FieldSpec;
    /// `SBC`, bit 0.
    pub const SBC: &FieldSpec = &super::REGISTERS[54].fields[0];
    /// `SMC`, bit 1.
    pub const SMC: &FieldSpec = &super::REGISTERS[54].fields[1];
    /// `CSM`, bit 2.
    pub const CSM: &FieldSpec = &super::REGISTERS[54].fields[2];
    /// `SOG`, bit 3.
    pub const SOG: &FieldSpec = &super::REGISTERS[54].fields[3];
    /// `RTMI`, bit 4.
    pub const RTMI: &FieldSpec = &super::REGISTERS[54].fields[4];
    /// `TTMI`, bit 5.
    pub const TTMI: &FieldSpec = &super::REGISTERS[54].fields[5];
    /// `SWE`, bit 6.
    pub const SWE: &FieldSpec = &super::REGISTERS[54].fields[6];
    /// `GTW`, bit 7.
    pub const GTW: &FieldSpec = &super::REGISTERS[54].fields[7];
    /// `GTD`, bit 8.
    pub const GTD: &FieldSpec = &super::REGISTERS[54].fields[8];
    /// `GTE`, bit 9.
    pub const GTE: &FieldSpec = &super::REGISTERS[54].fields[9];
    /// `TXU`, bit 10.
    pub const TXU: &FieldSpec = &super::REGISTERS[54].fields[10];
    /// `TXO`, bit 11.
    pub const TXO: &FieldSpec = &super::REGISTERS[54].fields[11];
    /// `SE1`, bit 12.
    pub const SE1: &FieldSpec = &super::REGISTERS[54].fields[12];
    /// `SE2`, bit 13.
    pub const SE2: &FieldSpec = &super::REGISTERS[54].fields[13];
    /// `ELC`, bit 14.
    pub const ELC: &FieldSpec = &super::REGISTERS[54].fields[14];
    /// `IWTG`, bit 15.
    pub const IWTG: &FieldSpec = &super::REGISTERS[54].fields[15];
    /// `WT`, bit 16.
    pub const WT: &FieldSpec = &super::REGISTERS[54].fields[16];
    /// `AW`, bit 17.
    pub const AW: &FieldSpec = &super::REGISTERS[54].fields[17];
    /// `CER`, bit 18.
    pub const CER: &FieldSpec = &super::REGISTERS[54].fields[18];
}

/// The fields of `FDCAN_TTIE`.
pub mod fdcan_ttie {
    use super::FieldSpec;
    /// `SBCE`, bit 0.
    pub const SBCE: &FieldSpec = &super::REGISTERS[55].fields[0];
    /// `SMCE`, bit 1.
    pub const SMCE: &FieldSpec = &super::REGISTERS[55].fields[1];
    /// `CSME`, bit 2.
    pub const CSME: &FieldSpec = &super::REGISTERS[55].fields[2];
    /// `SOGE`, bit 3.
    pub const SOGE: &FieldSpec = &super::REGISTERS[55].fields[3];
    /// `RTMIE`, bit 4.
    pub const RTMIE: &FieldSpec = &super::REGISTERS[55].fields[4];
    /// `TTMIE`, bit 5.
    pub const TTMIE: &FieldSpec = &super::REGISTERS[55].fields[5];
    /// `SWEE`, bit 6.
    pub const SWEE: &FieldSpec = &super::REGISTERS[55].fields[6];
    /// `GTWE`, bit 7.
    pub const GTWE: &FieldSpec = &super::REGISTERS[55].fields[7];
    /// `GTDE`, bit 8.
    pub const GTDE: &FieldSpec = &super::REGISTERS[55].fields[8];
    /// `GTEE`, bit 9.
    pub const GTEE: &FieldSpec = &super::REGISTERS[55].fields[9];
    /// `TXUE`, bit 10.
    pub const TXUE: &FieldSpec = &super::REGISTERS[55].fields[10];
    /// `TXOE`, bit 11.
    pub const TXOE: &FieldSpec = &super::REGISTERS[55].fields[11];
    /// `SE1E`, bit 12.
    pub const SE1E: &FieldSpec = &super::REGISTERS[55].fields[12];
    /// `SE2E`, bit 13.
    pub const SE2E: &FieldSpec = &super::REGISTERS[55].fields[13];
    /// `ELCE`, bit 14.
    pub const ELCE: &FieldSpec = &super::REGISTERS[55].fields[14];
    /// `IWTGE`, bit 15.
    pub const IWTGE: &FieldSpec = &super::REGISTERS[55].fields[15];
    /// `WTE`, bit 16.
    pub const WTE: &FieldSpec = &super::REGISTERS[55].fields[16];
    /// `AWE`, bit 17.
    pub const AWE: &FieldSpec = &super::REGISTERS[55].fields[17];
    /// `CERE`, bit 18.
    pub const CERE: &FieldSpec = &super::REGISTERS[55].fields[18];
}

/// The fields of `FDCAN_TTILS`.
pub mod fdcan_ttils {
    use super::FieldSpec;
    /// `SBCL`, bit 0.
    pub const SBCL: &FieldSpec = &super::REGISTERS[56].fields[0];
    /// `SMCL`, bit 1.
    pub const SMCL: &FieldSpec = &super::REGISTERS[56].fields[1];
    /// `CSML`, bit 2.
    pub const CSML: &FieldSpec = &super::REGISTERS[56].fields[2];
    /// `SOGL`, bit 3.
    pub const SOGL: &FieldSpec = &super::REGISTERS[56].fields[3];
    /// `RTMIL`, bit 4.
    pub const RTMIL: &FieldSpec = &super::REGISTERS[56].fields[4];
    /// `TTMIL`, bit 5.
    pub const TTMIL: &FieldSpec = &super::REGISTERS[56].fields[5];
    /// `SWEL`, bit 6.
    pub const SWEL: &FieldSpec = &super::REGISTERS[56].fields[6];
    /// `GTWL`, bit 7.
    pub const GTWL: &FieldSpec = &super::REGISTERS[56].fields[7];
    /// `GTDL`, bit 8.
    pub const GTDL: &FieldSpec = &super::REGISTERS[56].fields[8];
    /// `GTEL`, bit 9.
    pub const GTEL: &FieldSpec = &super::REGISTERS[56].fields[9];
    /// `TXUL`, bit 10.
    pub const TXUL: &FieldSpec = &super::REGISTERS[56].fields[10];
    /// `TXOL`, bit 11.
    pub const TXOL: &FieldSpec = &super::REGISTERS[56].fields[11];
    /// `SE1L`, bit 12.
    pub const SE1L: &FieldSpec = &super::REGISTERS[56].fields[12];
    /// `SE2L`, bit 13.
    pub const SE2L: &FieldSpec = &super::REGISTERS[56].fields[13];
    /// `ELCL`, bit 14.
    pub const ELCL: &FieldSpec = &super::REGISTERS[56].fields[14];
    /// `IWTGL`, bit 15.
    pub const IWTGL: &FieldSpec = &super::REGISTERS[56].fields[15];
    /// `WTL`, bit 16.
    pub const WTL: &FieldSpec = &super::REGISTERS[56].fields[16];
    /// `AWL`, bit 17.
    pub const AWL: &FieldSpec = &super::REGISTERS[56].fields[17];
    /// `CERL`, bit 18.
    pub const CERL: &FieldSpec = &super::REGISTERS[56].fields[18];
}

/// The fields of `FDCAN_TTOST`.
pub mod fdcan_ttost {
    use super::FieldSpec;
    /// `EL`, bits 0..=1.
    pub const EL: &FieldSpec = &super::REGISTERS[57].fields[0];
    /// `MS`, bits 2..=3.
    pub const MS: &FieldSpec = &super::REGISTERS[57].fields[1];
    /// `SYS`, bits 4..=5.
    pub const SYS: &FieldSpec = &super::REGISTERS[57].fields[2];
    /// `GTP`, bit 6.
    pub const GTP: &FieldSpec = &super::REGISTERS[57].fields[3];
    /// `QCS`, bit 7.
    pub const QCS: &FieldSpec = &super::REGISTERS[57].fields[4];
    /// `RTO`, bits 8..=15.
    pub const RTO: &FieldSpec = &super::REGISTERS[57].fields[5];
    /// `WGTD`, bit 22.
    pub const WGTD: &FieldSpec = &super::REGISTERS[57].fields[6];
    /// `GFI`, bit 23.
    pub const GFI: &FieldSpec = &super::REGISTERS[57].fields[7];
    /// `TMP`, bits 24..=26.
    pub const TMP: &FieldSpec = &super::REGISTERS[57].fields[8];
    /// `GSI`, bit 27.
    pub const GSI: &FieldSpec = &super::REGISTERS[57].fields[9];
    /// `WFE`, bit 28.
    pub const WFE: &FieldSpec = &super::REGISTERS[57].fields[10];
    /// `AWE`, bit 29.
    pub const AWE: &FieldSpec = &super::REGISTERS[57].fields[11];
    /// `WECS`, bit 30.
    pub const WECS: &FieldSpec = &super::REGISTERS[57].fields[12];
    /// `SPL`, bit 31.
    pub const SPL: &FieldSpec = &super::REGISTERS[57].fields[13];
}

/// The fields of `FDCAN_TURNA`.
pub mod fdcan_turna {
    use super::FieldSpec;
    /// `NAV`, bits 0..=17.
    pub const NAV: &FieldSpec = &super::REGISTERS[58].fields[0];
}

/// The fields of `FDCAN_TTLGT`.
pub mod fdcan_ttlgt {
    use super::FieldSpec;
    /// `LT`, bits 0..=15.
    pub const LT: &FieldSpec = &super::REGISTERS[59].fields[0];
    /// `GT`, bits 16..=31.
    pub const GT: &FieldSpec = &super::REGISTERS[59].fields[1];
}

/// The fields of `FDCAN_TTCTC`.
pub mod fdcan_ttctc {
    use super::FieldSpec;
    /// `CT`, bits 0..=15.
    pub const CT: &FieldSpec = &super::REGISTERS[60].fields[0];
    /// `CC`, bits 16..=21.
    pub const CC: &FieldSpec = &super::REGISTERS[60].fields[1];
}

/// The fields of `FDCAN_TTCPT`.
pub mod fdcan_ttcpt {
    use super::FieldSpec;
    /// `CT`, bits 0..=5.
    pub const CT: &FieldSpec = &super::REGISTERS[61].fields[0];
    /// `SWV`, bits 16..=31.
    pub const SWV: &FieldSpec = &super::REGISTERS[61].fields[1];
}

/// The fields of `FDCAN_TTCSM`.
pub mod fdcan_ttcsm {
    use super::FieldSpec;
    /// `CSM`, bits 0..=15.
    pub const CSM: &FieldSpec = &super::REGISTERS[62].fields[0];
}

/// The fields of `FDCAN_TTTS`.
pub mod fdcan_ttts {
    use super::FieldSpec;
    /// `SWTDEL`, bits 0..=1.
    pub const SWTDEL: &FieldSpec = &super::REGISTERS[63].fields[0];
    /// `EVTSEL`, bits 4..=5.
    pub const EVTSEL: &FieldSpec = &super::REGISTERS[63].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 64] = [
    RegisterSpec { name: "FDCAN_CREL", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DAY", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MON", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "YEAR", bit: 16, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SUBSTEP", bit: 20, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STEP", bit: 24, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REL", bit: 28, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_ENDN", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ETV", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_DBTP", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DSJW", bit: 0, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTSEG2", bit: 4, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTSEG1", bit: 8, width: 5, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBRP", bit: 16, width: 5, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDC", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TEST", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LBCK", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TX", bit: 5, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RX", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_RWD", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WDC", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WDV", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_CCCR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "INIT", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ASM", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSA", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MON", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DAR", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEST", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FDOE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BSE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PXHD", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EFBI", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXP", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NISO", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_NBTP", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSEG2", bit: 0, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NTSEG1", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBRP", bit: 16, width: 9, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NSJW", bit: 25, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TSCC", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSS", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCP", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TSCV", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TSC", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TOCC", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ETOC", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TOS", bit: 1, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TOP", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TOCV", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TOC", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_ECR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TEC", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TREC", bit: 8, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RP", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CEL", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_PSR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LEC", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACT", bit: 3, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EP", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EW", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BO", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DLEC", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RESI", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBRS", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REDL", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PXE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDCV", bit: 16, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TDCR", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TDCF", bit: 0, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDCO", bit: 8, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_IR", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RF0N", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF0W", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF0F", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF0L", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1N", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1W", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1F", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1L", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HPM", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TC", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCF", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEF", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFN", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFW", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFF", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFL", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSW", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MRAF", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TOO", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DRX", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ELO", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EP", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EW", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BO", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WDI", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PEA", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PED", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARA", bit: 29, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_IE", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RF0NE", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF0WE", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF0FE", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF0LE", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1NE", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1WE", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1FE", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1LE", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HPME", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCE", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCFE", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFE", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFNE", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFWE", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFFE", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFLE", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSWE", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MRAFE", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TOOE", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DRXE", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BECE", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BEUE", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ELOE", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EPE", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EWE", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOE", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WDIE", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PEAE", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PEDE", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARAE", bit: 29, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_ILS", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RF0NL", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF0WL", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF0FL", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF0LL", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1NL", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1WL", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1FL", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1LL", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HPML", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCL", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCFL", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFL", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFNL", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFWL", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFFL", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFLL", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSWL", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MRAFL", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TOOL", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DRXL", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BECL", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BEUL", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ELOL", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EPL", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EWL", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOL", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WDIL", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PEAL", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PEDL", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARAL", bit: 29, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_ILE", offset: 0x5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EINT0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EINT1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_GFC", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RRFE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RRFS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ANFE", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ANFS", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_SIDFC", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FLSSA", bit: 2, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSS", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_XIDFC", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FLESA", bit: 2, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSE", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_XIDAM", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EIDM", bit: 0, width: 29, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_HPMS", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BIDX", bit: 0, width: 6, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSI", bit: 6, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FIDX", bit: 8, width: 7, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLST", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_NDAT1", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ND0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND2", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND3", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND5", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND6", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND7", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND8", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND9", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND10", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND11", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND12", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND13", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND14", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND15", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND16", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND17", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND18", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND19", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND20", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND21", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND22", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND23", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND24", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND25", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND26", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND27", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND28", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND29", bit: 29, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND30", bit: 30, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND31", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_NDAT2", offset: 0x9C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ND32", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND33", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND34", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND35", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND36", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND37", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND38", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND39", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND40", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND41", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND42", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND43", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND44", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND45", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND46", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND47", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND48", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND49", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND50", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND51", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND52", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND53", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND54", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND55", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND56", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND57", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND58", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND59", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND60", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND61", bit: 29, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND62", bit: 30, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ND63", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_RXF0C", offset: 0xA0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "F0SA", bit: 2, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F0S", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F0WM", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_RXF0S", offset: 0xA4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "F0FL", bit: 0, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F0G", bit: 8, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F0P", bit: 16, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F0F", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF0L", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_RXF0A", offset: 0xA8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FA01", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_RXBC", offset: 0xAC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RBSA", bit: 2, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_RXF1C", offset: 0xB0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "F1SA", bit: 2, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F1S", bit: 16, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F1WM", bit: 24, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_RXF1S", offset: 0xB4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "F1FL", bit: 0, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F1GI", bit: 8, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F1PI", bit: 16, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F1F", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RF1L", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMS", bit: 30, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_RXF1A", offset: 0xB8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "F1AI", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_RXESC", offset: 0xBC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "F0DS", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F1DS", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBDS", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXBC", offset: 0xC0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TBSA", bit: 2, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NDTB", bit: 16, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TFQS", bit: 24, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TFQM", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXFQS", offset: 0xC4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TFFL", bit: 0, width: 6, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TFGI", bit: 8, width: 5, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TFQPI", bit: 16, width: 5, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TFQF", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXESC", offset: 0xC8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TBDS", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXBRP", offset: 0xCC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TRP", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXBAR", offset: 0xD0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXBCR", offset: 0xD4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXBTO", offset: 0xD8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TO", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXBCF", offset: 0xDC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CF", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXBTIE", offset: 0xE0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIE", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXBCIE", offset: 0xE4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CF", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXEFC", offset: 0xF0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EFSA", bit: 2, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EFS", bit: 16, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EFWM", bit: 24, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXEFS", offset: 0xF4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EFFL", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EFGI", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EFPI", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EFF", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEFL", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TXEFA", offset: 0xF8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EFAI", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTTMC", offset: 0x100, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TMSA", bit: 2, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TME", bit: 16, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTRMC", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RID", bit: 0, width: 29, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "XTD", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RMPS", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTOCF", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OM", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TM", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LDSDL", bit: 5, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IRTO", bit: 8, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EECS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWL", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EGTF", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECC", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EVTP", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTMLM", offset: 0x10C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCM", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSS", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXEW", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ENTT", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TURCF", offset: 0x110, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NCL", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DC", bit: 16, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ELT", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTOCN", offset: 0x114, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SGT", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWP", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWS", bit: 3, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TMC", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TTIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GCS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FGP", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TMG", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NIG", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ESCN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCKC", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CAN_TTGTP", offset: 0x118, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NCL", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTP", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTTMK", offset: 0x11C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TM", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TICC", bit: 16, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCKM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTIR", offset: 0x120, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SBC", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMC", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSM", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOG", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTMI", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TTMI", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GTW", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GTD", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GTE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXU", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXO", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE1", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE2", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ELC", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IWTG", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WT", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AW", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CER", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTIE", offset: 0x124, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SBCE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMCE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSME", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOGE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTMIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TTMIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWEE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GTWE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GTDE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GTEE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXOE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE1E", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE2E", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ELCE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IWTGE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WTE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWE", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CERE", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTILS", offset: 0x128, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SBCL", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMCL", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSML", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOGL", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTMIL", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TTMIL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWEL", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GTWL", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GTDL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GTEL", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUL", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXOL", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE1L", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SE2L", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ELCL", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IWTGL", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WTL", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWL", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CERL", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTOST", offset: 0x12C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EL", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MS", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYS", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GTP", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "QCS", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTO", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WGTD", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GFI", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TMP", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GSI", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WFE", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWE", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WECS", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPL", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TURNA", offset: 0x130, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NAV", bit: 0, width: 18, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTLGT", offset: 0x134, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LT", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GT", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTCTC", offset: 0x138, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CT", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC", bit: 16, width: 6, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTCPT", offset: 0x13C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CT", bit: 0, width: 6, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWV", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTCSM", offset: 0x140, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CSM", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FDCAN_TTTS", offset: 0x300, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SWTDEL", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EVTSEL", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];