rigless 0.2.1

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `DBG` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `DBGMCU_IDCODE` at offset `0x0`, resets to `0x1000_6411`, read-only.
    DbgmcuIdcode = 0,
    /// `DBGMCU_CR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    DbgmcuCr = 1,
    /// `DBGMCU_APB1_FZ` at offset `0x8`, resets to `0x0000_0000`, read-write.
    DbgmcuApb1Fz = 2,
    /// `DBGMCU_APB2_FZ` at offset `0xC`, resets to `0x0000_0000`, read-write.
    DbgmcuApb2Fz = 3,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 4] = [Self::DbgmcuIdcode, Self::DbgmcuCr, Self::DbgmcuApb1Fz, Self::DbgmcuApb2Fz];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `DBGMCU_IDCODE`.
pub mod dbgmcu_idcode {
    use super::FieldSpec;
    /// `DEV_ID`, bits 0..=11.
    pub const DEV_ID: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `REV_ID`, bits 16..=31.
    pub const REV_ID: &FieldSpec = &super::REGISTERS[0].fields[1];
}

/// The fields of `DBGMCU_CR`.
pub mod dbgmcu_cr {
    use super::FieldSpec;
    /// `DBG_SLEEP`, bit 0.
    pub const DBG_SLEEP: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `DBG_STOP`, bit 1.
    pub const DBG_STOP: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `DBG_STANDBY`, bit 2.
    pub const DBG_STANDBY: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `TRACE_IOEN`, bit 5.
    pub const TRACE_IOEN: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `TRACE_MODE`, bits 6..=7.
    pub const TRACE_MODE: &FieldSpec = &super::REGISTERS[1].fields[4];
}

/// The fields of `DBGMCU_APB1_FZ`.
pub mod dbgmcu_apb1_fz {
    use super::FieldSpec;
    /// `DBG_TIM2_STOP`, bit 0.
    pub const DBG_TIM2_STOP: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `DBG_TIM3_STOP`, bit 1.
    pub const DBG_TIM3_STOP: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `DBG_TIM4_STOP`, bit 2.
    pub const DBG_TIM4_STOP: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `DBG_TIM5_STOP`, bit 3.
    pub const DBG_TIM5_STOP: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `DBG_TIM6_STOP`, bit 4.
    pub const DBG_TIM6_STOP: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `DBG_TIM7_STOP`, bit 5.
    pub const DBG_TIM7_STOP: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `DBG_TIM12_STOP`, bit 6.
    pub const DBG_TIM12_STOP: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `DBG_TIM13_STOP`, bit 7.
    pub const DBG_TIM13_STOP: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `DBG_TIM14_STOP`, bit 8.
    pub const DBG_TIM14_STOP: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `DBG_WWDG_STOP`, bit 11.
    pub const DBG_WWDG_STOP: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `DBG_IWDEG_STOP`, bit 12.
    pub const DBG_IWDEG_STOP: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `DBG_J2C1_SMBUS_TIMEOUT`, bit 21.
    pub const DBG_J2C1_SMBUS_TIMEOUT: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `DBG_J2C2_SMBUS_TIMEOUT`, bit 22.
    pub const DBG_J2C2_SMBUS_TIMEOUT: &FieldSpec = &super::REGISTERS[2].fields[12];
    /// `DBG_J2C3SMBUS_TIMEOUT`, bit 23.
    pub const DBG_J2C3SMBUS_TIMEOUT: &FieldSpec = &super::REGISTERS[2].fields[13];
    /// `DBG_CAN1_STOP`, bit 25.
    pub const DBG_CAN1_STOP: &FieldSpec = &super::REGISTERS[2].fields[14];
    /// `DBG_CAN2_STOP`, bit 26.
    pub const DBG_CAN2_STOP: &FieldSpec = &super::REGISTERS[2].fields[15];
}

/// The fields of `DBGMCU_APB2_FZ`.
pub mod dbgmcu_apb2_fz {
    use super::FieldSpec;
    /// `DBG_TIM1_STOP`, bit 0.
    pub const DBG_TIM1_STOP: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `DBG_TIM8_STOP`, bit 1.
    pub const DBG_TIM8_STOP: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `DBG_TIM9_STOP`, bit 16.
    pub const DBG_TIM9_STOP: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `DBG_TIM10_STOP`, bit 17.
    pub const DBG_TIM10_STOP: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `DBG_TIM11_STOP`, bit 18.
    pub const DBG_TIM11_STOP: &FieldSpec = &super::REGISTERS[3].fields[4];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 4] = [
    RegisterSpec { name: "DBGMCU_IDCODE", offset: 0x0, width: Width::W32, reset: 0x1000_6411, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DEV_ID", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REV_ID", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DBGMCU_CR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DBG_SLEEP", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_STOP", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_STANDBY", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRACE_IOEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRACE_MODE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DBGMCU_APB1_FZ", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DBG_TIM2_STOP", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM3_STOP", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM4_STOP", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM5_STOP", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM6_STOP", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM7_STOP", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM12_STOP", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM13_STOP", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM14_STOP", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_WWDG_STOP", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_IWDEG_STOP", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_J2C1_SMBUS_TIMEOUT", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_J2C2_SMBUS_TIMEOUT", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_J2C3SMBUS_TIMEOUT", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_CAN1_STOP", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_CAN2_STOP", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DBGMCU_APB2_FZ", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DBG_TIM1_STOP", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM8_STOP", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM9_STOP", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM10_STOP", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBG_TIM11_STOP", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];