rigless 0.2.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `Ethernet_MMC` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `MMCCR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Mmccr = 0,
    /// `MMCRIR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Mmcrir = 1,
    /// `MMCTIR` at offset `0x8`, resets to `0x0000_0000`, read-only.
    Mmctir = 2,
    /// `MMCRIMR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Mmcrimr = 3,
    /// `MMCTIMR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Mmctimr = 4,
    /// `MMCTGFSCCR` at offset `0x4C`, resets to `0x0000_0000`, read-only.
    Mmctgfsccr = 5,
    /// `MMCTGFMSCCR` at offset `0x50`, resets to `0x0000_0000`, read-only.
    Mmctgfmsccr = 6,
    /// `MMCTGFCR` at offset `0x68`, resets to `0x0000_0000`, read-only.
    Mmctgfcr = 7,
    /// `MMCRFCECR` at offset `0x94`, resets to `0x0000_0000`, read-only.
    Mmcrfcecr = 8,
    /// `MMCRFAECR` at offset `0x98`, resets to `0x0000_0000`, read-only.
    Mmcrfaecr = 9,
    /// `MMCRGUFCR` at offset `0xC4`, resets to `0x0000_0000`, read-only.
    Mmcrgufcr = 10,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 11] = [Self::Mmccr, Self::Mmcrir, Self::Mmctir, Self::Mmcrimr, Self::Mmctimr, Self::Mmctgfsccr, Self::Mmctgfmsccr, Self::Mmctgfcr, Self::Mmcrfcecr, Self::Mmcrfaecr, Self::Mmcrgufcr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `MMCCR`.
pub mod mmccr {
    use super::FieldSpec;
    /// `CR`, bit 0.
    pub const CR: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `CSR`, bit 1.
    pub const CSR: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `ROR`, bit 2.
    pub const ROR: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `MCF`, bit 3.
    pub const MCF: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `MCP`, bit 4.
    pub const MCP: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `MCFHP`, bit 5.
    pub const MCFHP: &FieldSpec = &super::REGISTERS[0].fields[5];
}

/// The fields of `MMCRIR`.
pub mod mmcrir {
    use super::FieldSpec;
    /// `RFCES`, bit 5.
    pub const RFCES: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `RFAES`, bit 6.
    pub const RFAES: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `RGUFS`, bit 17.
    pub const RGUFS: &FieldSpec = &super::REGISTERS[1].fields[2];
}

/// The fields of `MMCTIR`.
pub mod mmctir {
    use super::FieldSpec;
    /// `TGFSCS`, bit 14.
    pub const TGFSCS: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `TGFMSCS`, bit 15.
    pub const TGFMSCS: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `TGFS`, bit 21.
    pub const TGFS: &FieldSpec = &super::REGISTERS[2].fields[2];
}

/// The fields of `MMCRIMR`.
pub mod mmcrimr {
    use super::FieldSpec;
    /// `RFCEM`, bit 5.
    pub const RFCEM: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `RFAEM`, bit 6.
    pub const RFAEM: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `RGUFM`, bit 17.
    pub const RGUFM: &FieldSpec = &super::REGISTERS[3].fields[2];
}

/// The fields of `MMCTIMR`.
pub mod mmctimr {
    use super::FieldSpec;
    /// `TGFSCM`, bit 14.
    pub const TGFSCM: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `TGFMSCM`, bit 15.
    pub const TGFMSCM: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `TGFM`, bit 16.
    pub const TGFM: &FieldSpec = &super::REGISTERS[4].fields[2];
}

/// The fields of `MMCTGFSCCR`.
pub mod mmctgfsccr {
    use super::FieldSpec;
    /// `TGFSCC`, bits 0..=31.
    pub const TGFSCC: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `MMCTGFMSCCR`.
pub mod mmctgfmsccr {
    use super::FieldSpec;
    /// `TGFMSCC`, bits 0..=31.
    pub const TGFMSCC: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `MMCTGFCR`.
pub mod mmctgfcr {
    use super::FieldSpec;
    /// `TGFC`, bits 0..=31.
    pub const TGFC: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `MMCRFCECR`.
pub mod mmcrfcecr {
    use super::FieldSpec;
    /// `RFCFC`, bits 0..=31.
    pub const RFCFC: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `MMCRFAECR`.
pub mod mmcrfaecr {
    use super::FieldSpec;
    /// `RFAEC`, bits 0..=31.
    pub const RFAEC: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `MMCRGUFCR`.
pub mod mmcrgufcr {
    use super::FieldSpec;
    /// `RGUFC`, bits 0..=31.
    pub const RGUFC: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 11] = [
    RegisterSpec { name: "MMCCR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CR", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSR", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROR", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCP", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCFHP", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMCRIR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RFCES", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RFAES", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RGUFS", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMCTIR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TGFSCS", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TGFMSCS", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TGFS", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMCRIMR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RFCEM", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RFAEM", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RGUFM", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMCTIMR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TGFSCM", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TGFMSCM", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TGFM", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMCTGFSCCR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TGFSCC", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMCTGFMSCCR", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TGFMSCC", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMCTGFCR", offset: 0x68, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TGFC", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMCRFCECR", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RFCFC", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMCRFAECR", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RFAEC", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MMCRGUFCR", offset: 0xC4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RGUFC", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];