rigless 0.0.6

// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `Ethernet_MAC` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `MACCR` at offset `0x0`, resets to `0x0000_8000`, read-write.
    Maccr = 0,
    /// `MACFFR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Macffr = 1,
    /// `MACHTHR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Machthr = 2,
    /// `MACHTLR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Machtlr = 3,
    /// `MACMIIAR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Macmiiar = 4,
    /// `MACMIIDR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Macmiidr = 5,
    /// `MACFCR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Macfcr = 6,
    /// `MACVLANTR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Macvlantr = 7,
    /// `MACPMTCSR` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Macpmtcsr = 8,
    /// `MACDBGR` at offset `0x34`, resets to `0x0000_0000`, read-only.
    Macdbgr = 9,
    /// `MACSR` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Macsr = 10,
    /// `MACIMR` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    Macimr = 11,
    /// `MACA0HR` at offset `0x40`, resets to `0x0010_FFFF`, read-write.
    Maca0hr = 12,
    /// `MACA0LR` at offset `0x44`, resets to `0xFFFF_FFFF`, read-write.
    Maca0lr = 13,
    /// `MACA1HR` at offset `0x48`, resets to `0x0000_FFFF`, read-write.
    Maca1hr = 14,
    /// `MACA1LR` at offset `0x4C`, resets to `0xFFFF_FFFF`, read-write.
    Maca1lr = 15,
    /// `MACA2HR` at offset `0x50`, resets to `0x0000_FFFF`, read-write.
    Maca2hr = 16,
    /// `MACA2LR` at offset `0x54`, resets to `0xFFFF_FFFF`, read-write.
    Maca2lr = 17,
    /// `MACA3HR` at offset `0x58`, resets to `0x0000_FFFF`, read-write.
    Maca3hr = 18,
    /// `MACA3LR` at offset `0x5C`, resets to `0xFFFF_FFFF`, read-write.
    Maca3lr = 19,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 20] = [Self::Maccr, Self::Macffr, Self::Machthr, Self::Machtlr, Self::Macmiiar, Self::Macmiidr, Self::Macfcr, Self::Macvlantr, Self::Macpmtcsr, Self::Macdbgr, Self::Macsr, Self::Macimr, Self::Maca0hr, Self::Maca0lr, Self::Maca1hr, Self::Maca1lr, Self::Maca2hr, Self::Maca2lr, Self::Maca3hr, Self::Maca3lr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `MACCR`.
pub mod maccr {
    use super::FieldSpec;
    /// `RE`, bit 2.
    pub const RE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `TE`, bit 3.
    pub const TE: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `DC`, bit 4.
    pub const DC: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `BL`, bits 5..=6.
    pub const BL: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `APCS`, bit 7.
    pub const APCS: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `RD`, bit 9.
    pub const RD: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `IPCO`, bit 10.
    pub const IPCO: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `DM`, bit 11.
    pub const DM: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `LM`, bit 12.
    pub const LM: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `ROD`, bit 13.
    pub const ROD: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `FES`, bit 14.
    pub const FES: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `CSD`, bit 16.
    pub const CSD: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `IFG`, bits 17..=19.
    pub const IFG: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `JD`, bit 22.
    pub const JD: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `WD`, bit 23.
    pub const WD: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `CSTF`, bit 25.
    pub const CSTF: &FieldSpec = &super::REGISTERS[0].fields[15];
}

/// The fields of `MACFFR`.
pub mod macffr {
    use super::FieldSpec;
    /// `PM`, bit 0.
    pub const PM: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `HU`, bit 1.
    pub const HU: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `HM`, bit 2.
    pub const HM: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `DAIF`, bit 3.
    pub const DAIF: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `RAM`, bit 4.
    pub const RAM: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `BFD`, bit 5.
    pub const BFD: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `PCF`, bit 6.
    pub const PCF: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `SAIF`, bit 7.
    pub const SAIF: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `SAF`, bit 8.
    pub const SAF: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `HPF`, bit 9.
    pub const HPF: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `RA`, bit 31.
    pub const RA: &FieldSpec = &super::REGISTERS[1].fields[10];
}

/// The fields of `MACHTHR`.
pub mod machthr {
    use super::FieldSpec;
    /// `HTH`, bits 0..=31.
    pub const HTH: &FieldSpec = &super::REGISTERS[2].fields[0];
}

/// The fields of `MACHTLR`.
pub mod machtlr {
    use super::FieldSpec;
    /// `HTL`, bits 0..=31.
    pub const HTL: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `MACMIIAR`.
pub mod macmiiar {
    use super::FieldSpec;
    /// `MB`, bit 0.
    pub const MB: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `MW`, bit 1.
    pub const MW: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `CR`, bits 2..=4.
    pub const CR: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `MR`, bits 6..=10.
    pub const MR: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `PA`, bits 11..=15.
    pub const PA: &FieldSpec = &super::REGISTERS[4].fields[4];
}

/// The fields of `MACMIIDR`.
pub mod macmiidr {
    use super::FieldSpec;
    /// `TD`, bits 0..=15.
    pub const TD: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `MACFCR`.
pub mod macfcr {
    use super::FieldSpec;
    /// `FCB`, bit 0.
    pub const FCB: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `TFCE`, bit 1.
    pub const TFCE: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `RFCE`, bit 2.
    pub const RFCE: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `UPFD`, bit 3.
    pub const UPFD: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `PLT`, bits 4..=5.
    pub const PLT: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `ZQPD`, bit 7.
    pub const ZQPD: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `PT`, bits 16..=31.
    pub const PT: &FieldSpec = &super::REGISTERS[6].fields[6];
}

/// The fields of `MACVLANTR`.
pub mod macvlantr {
    use super::FieldSpec;
    /// `VLANTI`, bits 0..=15.
    pub const VLANTI: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `VLANTC`, bit 16.
    pub const VLANTC: &FieldSpec = &super::REGISTERS[7].fields[1];
}

/// The fields of `MACPMTCSR`.
pub mod macpmtcsr {
    use super::FieldSpec;
    /// `PD`, bit 0.
    pub const PD: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `MPE`, bit 1.
    pub const MPE: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `WFE`, bit 2.
    pub const WFE: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `MPR`, bit 5.
    pub const MPR: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `WFR`, bit 6.
    pub const WFR: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `GU`, bit 9.
    pub const GU: &FieldSpec = &super::REGISTERS[8].fields[5];
    /// `WFFRPR`, bit 31.
    pub const WFFRPR: &FieldSpec = &super::REGISTERS[8].fields[6];
}

/// The fields of `MACDBGR`.
pub mod macdbgr {
    use super::FieldSpec;
    /// `CR`, bit 0.
    pub const CR: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `CSR`, bit 1.
    pub const CSR: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `ROR`, bit 2.
    pub const ROR: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `MCF`, bit 3.
    pub const MCF: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `MCP`, bit 4.
    pub const MCP: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `MCFHP`, bit 5.
    pub const MCFHP: &FieldSpec = &super::REGISTERS[9].fields[5];
}

/// The fields of `MACSR`.
pub mod macsr {
    use super::FieldSpec;
    /// `PMTS`, bit 3, read-only.
    pub const PMTS: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `MMCS`, bit 4, read-only.
    pub const MMCS: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `MMCRS`, bit 5, read-only.
    pub const MMCRS: &FieldSpec = &super::REGISTERS[10].fields[2];
    /// `MMCTS`, bit 6, read-only.
    pub const MMCTS: &FieldSpec = &super::REGISTERS[10].fields[3];
    /// `TSTS`, bit 9.
    pub const TSTS: &FieldSpec = &super::REGISTERS[10].fields[4];
}

/// The fields of `MACIMR`.
pub mod macimr {
    use super::FieldSpec;
    /// `PMTIM`, bit 3.
    pub const PMTIM: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `TSTIM`, bit 9.
    pub const TSTIM: &FieldSpec = &super::REGISTERS[11].fields[1];
}

/// The fields of `MACA0HR`.
pub mod maca0hr {
    use super::FieldSpec;
    /// `MACA0H`, bits 0..=15.
    pub const MACA0H: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `MO`, bit 31, read-only.
    pub const MO: &FieldSpec = &super::REGISTERS[12].fields[1];
}

/// The fields of `MACA0LR`.
pub mod maca0lr {
    use super::FieldSpec;
    /// `MACA0L`, bits 0..=31.
    pub const MACA0L: &FieldSpec = &super::REGISTERS[13].fields[0];
}

/// The fields of `MACA1HR`.
pub mod maca1hr {
    use super::FieldSpec;
    /// `MACA1H`, bits 0..=15.
    pub const MACA1H: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `MBC`, bits 24..=29.
    pub const MBC: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `SA`, bit 30.
    pub const SA: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `AE`, bit 31.
    pub const AE: &FieldSpec = &super::REGISTERS[14].fields[3];
}

/// The fields of `MACA1LR`.
pub mod maca1lr {
    use super::FieldSpec;
    /// `MACA1LR`, bits 0..=31.
    pub const MACA1LR: &FieldSpec = &super::REGISTERS[15].fields[0];
}

/// The fields of `MACA2HR`.
pub mod maca2hr {
    use super::FieldSpec;
    /// `MAC2AH`, bits 0..=15.
    pub const MAC2AH: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `MBC`, bits 24..=29.
    pub const MBC: &FieldSpec = &super::REGISTERS[16].fields[1];
    /// `SA`, bit 30.
    pub const SA: &FieldSpec = &super::REGISTERS[16].fields[2];
    /// `AE`, bit 31.
    pub const AE: &FieldSpec = &super::REGISTERS[16].fields[3];
}

/// The fields of `MACA2LR`.
pub mod maca2lr {
    use super::FieldSpec;
    /// `MACA2L`, bits 0..=30.
    pub const MACA2L: &FieldSpec = &super::REGISTERS[17].fields[0];
}

/// The fields of `MACA3HR`.
pub mod maca3hr {
    use super::FieldSpec;
    /// `MACA3H`, bits 0..=15.
    pub const MACA3H: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `MBC`, bits 24..=29.
    pub const MBC: &FieldSpec = &super::REGISTERS[18].fields[1];
    /// `SA`, bit 30.
    pub const SA: &FieldSpec = &super::REGISTERS[18].fields[2];
    /// `AE`, bit 31.
    pub const AE: &FieldSpec = &super::REGISTERS[18].fields[3];
}

/// The fields of `MACA3LR`.
pub mod maca3lr {
    use super::FieldSpec;
    /// `MBCA3L`, bits 0..=31.
    pub const MBCA3L: &FieldSpec = &super::REGISTERS[19].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 20] = [
    RegisterSpec { name: "MACCR", offset: 0x0, width: Width::W32, reset: 0x0000_8000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DC", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BL", bit: 5, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "APCS", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RD", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IPCO", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DM", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LM", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROD", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FES", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSD", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFG", bit: 17, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JD", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WD", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSTF", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACFFR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PM", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HU", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HM", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DAIF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RAM", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BFD", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCF", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SAIF", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SAF", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HPF", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RA", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACHTHR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HTH", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACHTLR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HTL", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACMIIAR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MB", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MW", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CR", bit: 2, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR", bit: 6, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PA", bit: 11, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACMIIDR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TD", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACFCR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FCB", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TFCE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RFCE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UPFD", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLT", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ZQPD", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PT", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACVLANTR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "VLANTI", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VLANTC", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACPMTCSR", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PD", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MPE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WFE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MPR", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WFR", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GU", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WFFRPR", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACDBGR", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CR", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSR", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROR", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCP", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCFHP", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACSR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PMTS", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MMCS", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MMCRS", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MMCTS", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSTS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACIMR", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PMTIM", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSTIM", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA0HR", offset: 0x40, width: Width::W32, reset: 0x0010_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MACA0H", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MO", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA0LR", offset: 0x44, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MACA0L", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA1HR", offset: 0x48, width: Width::W32, reset: 0x0000_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MACA1H", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBC", bit: 24, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SA", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AE", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA1LR", offset: 0x4C, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MACA1LR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA2HR", offset: 0x50, width: Width::W32, reset: 0x0000_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MAC2AH", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBC", bit: 24, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SA", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AE", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA2LR", offset: 0x54, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MACA2L", bit: 0, width: 31, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA3HR", offset: 0x58, width: Width::W32, reset: 0x0000_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MACA3H", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MBC", bit: 24, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SA", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AE", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MACA3LR", offset: 0x5C, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MBCA3L", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];